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JPH0220142B2 - - Google Patents
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JPH0220142B2 - - Google Patents

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Publication number
JPH0220142B2
JPH0220142B2 JP58095231A JP9523183A JPH0220142B2 JP H0220142 B2 JPH0220142 B2 JP H0220142B2 JP 58095231 A JP58095231 A JP 58095231A JP 9523183 A JP9523183 A JP 9523183A JP H0220142 B2 JPH0220142 B2 JP H0220142B2
Authority
JP
Japan
Prior art keywords
film
wiring
alloy
wiring layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58095231A
Other languages
Japanese (ja)
Other versions
JPS59219940A (en
Inventor
Shohei Shima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP9523183A priority Critical patent/JPS59219940A/en
Publication of JPS59219940A publication Critical patent/JPS59219940A/en
Publication of JPH0220142B2 publication Critical patent/JPH0220142B2/ja
Granted legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、電極配線層としてアルミニウム
(Al)膜またはAlを主成分とする合金膜を用いた
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device using an aluminum (Al) film or an alloy film containing Al as a main component as an electrode wiring layer.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来より半導体装置の電極配線層としてAlが
広く使われている。第1図はAl配線を用いた2
層配線構造を示す素子断面図である。シリコン基
板11上に絶縁膜12を形成した後、第1層目の
Al配線層13を形成する。次いで層間の絶縁膜
14を堆積させ、この上に第2層目のAl配線層
15を形成して2層配線構造が得られる。
Al has been widely used as an electrode wiring layer of semiconductor devices. Figure 1 shows 2 using Al wiring.
FIG. 3 is an element cross-sectional view showing a layer wiring structure. After forming the insulating film 12 on the silicon substrate 11, the first layer is
An Al wiring layer 13 is formed. Next, an interlayer insulating film 14 is deposited, and a second Al wiring layer 15 is formed thereon to obtain a two-layer wiring structure.

このような構造を得る場合層間絶縁膜14は通
常400℃程度でCVD法により形成する。この際第
1層目のAl配線層13上にはヒロツク16を生
じ易い。このヒロツク16は、層間絶縁膜14の
異常成長を引き起こす結果、絶縁膜14の機械的
強度が弱くなり、クラツク17を生ずる。クラツ
ク17は、層間絶縁膜13上の第2層目のAl配
線層15と第1のAl配線層13との間の短絡の
原因となつたり、クラツクを通しての薬品の侵入
などによるAl配線の腐食を引き起こす為にAl配
線の信頼性を著しく低下させる。
In order to obtain such a structure, the interlayer insulating film 14 is usually formed at about 400° C. by the CVD method. At this time, hills 16 are likely to be formed on the first Al wiring layer 13. These hillocks 16 cause abnormal growth of the interlayer insulating film 14, which weakens the mechanical strength of the insulating film 14 and causes cracks 17. The crack 17 may cause a short circuit between the second Al wiring layer 15 on the interlayer insulating film 13 and the first Al wiring layer 13, or corrosion of the Al wiring due to penetration of chemicals through the crack. This causes a significant decrease in the reliability of Al wiring.

このようにAlのヒロツクは多層配線において
解決しなければならない重要な問題点である。こ
の解決策についてはここ10数年間種々検討されて
いるが、未だ完全な方法は見い出されていない。
As described above, Al hillocks are an important problem that must be solved in multilayer wiring. Various solutions to this problem have been studied over the past ten years, but no perfect method has yet been found.

一方半導体集積回路では、素子の微細化、高集
積化に伴ないAl配線幅は、2μから1μへとますま
す微細化される方向にある。微細Al配線では電
流密度が高くなる為に、エレクトロマイグレーシ
ヨンによるAl配線の断線が大きな信頼性低下の
一因となる。従来、Al配線のエレクトロマイグ
レーシヨン防止対策として多くの方法が提案され
ている。例えばAl中にCuを数%含ませておいて、
熱処理を施こすことによつてAl−Cuの金属間化
合物をAl配線の結晶粒界に析出させて、これに
よりAl原子のマイグレーシヨンを防止する方法
が提案されている。しかしこの方法では、未だエ
レクトロマイグレーシヨン対策として十分でな
い。
On the other hand, in semiconductor integrated circuits, the Al wiring width is becoming smaller and smaller from 2μ to 1μ as elements become smaller and more highly integrated. Because the current density is high in fine Al interconnects, disconnection of Al interconnects due to electromigration is a major cause of reduced reliability. Many methods have been proposed to prevent electromigration of Al wiring. For example, if a few percent of Cu is included in Al,
A method has been proposed in which Al--Cu intermetallic compounds are precipitated at the grain boundaries of Al interconnects by heat treatment, thereby preventing migration of Al atoms. However, this method is still not sufficient as a countermeasure against electromigration.

更に、エレクトロマイグレーシヨンに対して強
い配線の形成方法として第2図に示す様な、Al
配線層24の中間にTi,Cr,V,Mo,などの金
属層25をを設ける方法がある。これは、シリコ
ン基板21中に拡散領域22を設けた後、絶縁膜
23を形成し、コンタクトホールをあけてAl配
線層241を堆積後、Tiなどの金属層25を設
け、さらにAl配線層242を形成したものであ
る。
Furthermore, as a method for forming interconnects that are resistant to electromigration, Al
There is a method of providing a metal layer 25 of Ti, Cr, V, Mo, etc. in the middle of the wiring layer 24. After providing a diffusion region 22 in a silicon substrate 21, forming an insulating film 23, making a contact hole and depositing an Al wiring layer 241 , a metal layer 25 such as Ti is provided, and then an Al wiring layer 241 is deposited. 24 2 was formed.

上記の様に配線層を積層構造にした後、熱処理
を施こすことにより、中間のTiとAlが反応し、
Alとの合金層が形成される。この合金属は、エ
レクトロマイグレーシヨンによるAl原子の流れ
を均一にする効果、Alヒロツクの成長を抑止す
る効果があり、結果としてAl配線の耐エレクト
ロマイグレーシヨン特性を強化する。
After forming the wiring layer into a laminated structure as described above, heat treatment causes the Ti and Al in the middle to react.
An alloy layer with Al is formed. This alloy metal has the effect of making the flow of Al atoms uniform due to electromigration and the effect of suppressing the growth of Al hills, and as a result, strengthens the electromigration resistance of the Al wiring.

しかしながら、この方法では、熱処理によつて
AlとTiが反応するだけでなく、それに加えてSi
との反応も起こす。すなわちAl−Si−Tiの3元
合金が形成される。このSiは、Al配線24とシ
リコン基板21との接触部であるコンタクトホー
ル部下の拡散層22から供給される為に、図示の
ようなスパイク26が形成され、これが接合破壊
を生じる原因となる。
However, in this method, heat treatment
Not only Al and Ti react, but also Si
It also causes a reaction. That is, a ternary alloy of Al-Si-Ti is formed. Since this Si is supplied from the diffusion layer 22 under the contact hole, which is the contact portion between the Al wiring 24 and the silicon substrate 21, spikes 26 as shown in the figure are formed, which causes junction breakdown.

〔発明の目的〕[Purpose of the invention]

本発明は以上の点を鑑みてなされたもので、ヒ
ロツクの発生を抑制し耐エレクトロマイグレーシ
ヨン特性を向上すると共に、コンタクトホール部
で接合破壊の生じない高い信頼性を有するAl配
線を実現する半導体装置の製造方法を提供するも
のである。
The present invention has been made in view of the above points, and is a semiconductor that suppresses the occurrence of hillocks, improves electromigration resistance characteristics, and realizes highly reliable Al interconnects that do not cause junction breakdown in contact hole areas. A method for manufacturing the device is provided.

〔発明の概要〕[Summary of the invention]

本発明はAl配線層の内部または表面の少なく
とも一方に、Al,Siと他の一種の金属の三元素
が混合された金属膜を形成し、熱処理を施こすこ
とにより、前記三元素からなる合金膜または金属
間化合物膜を形成せしめることを特徴とする。
The present invention forms a metal film containing a mixture of three elements, Al, Si, and another type of metal, on at least one of the inside or surface of an Al wiring layer, and heat-treats the metal film to form an alloy consisting of the three elements. It is characterized by forming a film or an intermetallic compound film.

ここで、Al,Siと共に加える他の金属として
は、TiやCr,V,Moなど、Al,Siと共に三元合
金を形成するものであればよい。また本発明の
Al配線層は純粋なAl膜だけでなく、Si,Cu等を
含むAlを主成分とする合金膜であつてもよい。
Here, other metals added together with Al and Si may be metals such as Ti, Cr, V, and Mo, as long as they form a ternary alloy with Al and Si. Also, the present invention
The Al wiring layer may be not only a pure Al film, but also an alloy film containing Si, Cu, etc., whose main component is Al.

〔発明の効果〕〔Effect of the invention〕

本発明により、Al配線層の内部または表面に
形成された合金層膜は、Al配線のヒロツク発生
を抑制し、耐エレクトロマイグレーシヨン特性を
大幅に向上させる効果を有する。しかも、これら
の合金膜または金属間化合物膜は予めSiを含ませ
てあるから熱処理工程で基板からのSiの供給がな
くなり、従つてコンタクトホール部での接合破壊
が防止される。以上により本発明によれば高信頼
性のAl配線を形成できる。
According to the present invention, the alloy film formed inside or on the surface of the Al wiring layer has the effect of suppressing the occurrence of hillocks in the Al wiring and greatly improving the electromigration resistance. In addition, since these alloy films or intermetallic compound films contain Si in advance, the supply of Si from the substrate is eliminated during the heat treatment process, thereby preventing bond breakdown at the contact hole portion. As described above, according to the present invention, highly reliable Al wiring can be formed.

〔発明の実施例〕[Embodiments of the invention]

以下に図面を参照して本発明の実施例を説明す
る。第3図a〜dは本発明の一実施例の製造工程
を説明する為の工程断面図である。先ず第3図a
に示す様に、P型シリコン基板31に拡散層32
を形成した後、絶縁膜33でおおつてコンタクト
ホールをあけ、Al膜またはAlを主成分とするCu
あるいはSiとのAl合金膜34を0.5〜1.0μの厚さ
で形成する。次いでAl膜34上にAl−Ti−Siの
三元素からなる金属膜35を100〜1000Åの厚み
で形成する(第3図b)。このAl−Ti−Siの三元
素からなる金属膜35の形成方法は例えばAx,
Ti,Si,を異なるソースから同時に蒸着する方
法、Ti,Al,Siを所定の量だけ含んでいるター
ゲツトからのスパツタによる形成方法などがあ
る。又Al−Ti−Siの組成比はAlが全体の1〜
5wt%で、残りの99〜50%はTiとSiの組成比が
TiSi2となる様な量が良い。このようにしてAl膜
34とAl−Ti−Si三元素からなる金属膜35の
積層膜を形成後、300〜500℃で熱処理をすると第
3図cに示す様に、上記2層が合金化する結果、
表面部にAl−Ti−Si合金膜(あるいはTi7Si12Al5
金属間化合物膜)35′が形成される。この合金
膜35′はAl膜34を上部から機械的におおつて
ヒロツクを抑制する効果を有する為に、ほぼ完全
にヒロツクを無くすことができる。次いで第1の
配線層をパターニングした後第3図dに示す様
に、第1の配線層上に層間絶縁膜36を形成後、
Al膜37を被着して第2の配線層を形成する。
Embodiments of the present invention will be described below with reference to the drawings. 3A to 3D are process sectional views for explaining the manufacturing process of an embodiment of the present invention. First, Figure 3a
As shown in the figure, a diffusion layer 32 is formed on a P-type silicon substrate 31.
After forming, it is covered with an insulating film 33, a contact hole is opened, and an Al film or a Cu film mainly composed of Al is formed.
Alternatively, an Al alloy film 34 with Si is formed with a thickness of 0.5 to 1.0 μm. Next, a metal film 35 made of the three elements Al--Ti--Si is formed on the Al film 34 to a thickness of 100 to 1000 Å (FIG. 3b). The method for forming the metal film 35 made of the three elements Al-Ti-Si is, for example, Ax,
There are methods of depositing Ti and Si simultaneously from different sources, and methods of forming by sputtering from a target containing predetermined amounts of Ti, Al, and Si. In addition, the composition ratio of Al-Ti-Si is 1 to 1% of the total.
5wt%, and the remaining 99-50% is the composition ratio of Ti and Si.
The amount should be such that TiSi 2 is obtained. After forming a laminated film of the Al film 34 and the metal film 35 made of the three elements Al-Ti-Si in this way, heat treatment at 300 to 500°C causes the two layers to become alloyed, as shown in Figure 3c. As a result,
Al-Ti-Si alloy film (or Ti 7 Si 12 Al 5
An intermetallic compound film) 35' is formed. Since this alloy film 35' mechanically covers the Al film 34 from above and has the effect of suppressing hillocks, hillocks can be almost completely eliminated. After patterning the first wiring layer, an interlayer insulating film 36 is formed on the first wiring layer, as shown in FIG. 3d.
A second wiring layer is formed by depositing an Al film 37.

この様にして得られた2層配線構造は、第1層
目の配線層上にヒロツクが全く見られない為に、
配線層間の短絡は全く無くなる。又、ヒロツクに
よる絶縁膜の破壊も無くなる為に、配線の腐食等
も生じなくなつた。更にはヒロツク成長が抑制さ
れる為に、エレクトロマイグレーシヨンにより生
じる不良も起きにくくなつて、配線寿命が長くな
る為に、より多くの電流を流すことができるよう
になつた。また合金膜35′の形成工程で基板3
1からのSiの供給がないため、コンタクトホール
部で拡散層32の接合破壊を生じることもなくな
る。
The two-layer wiring structure obtained in this way has no hills on the first wiring layer, so
Short circuits between wiring layers are completely eliminated. Furthermore, since the insulating film is no longer destroyed by hills, corrosion of the wiring and the like no longer occur. Furthermore, since hillock growth is suppressed, defects caused by electromigration are less likely to occur, and the life of the wiring is extended, allowing more current to flow. Also, in the process of forming the alloy film 35', the substrate 3
Since there is no supply of Si from 1, there is no possibility of junction breakdown of the diffusion layer 32 at the contact hole portion.

次に本発明の別の実施例を説明する。第4図
a,bはその実施例の工程断面図である。シリコ
ン基板41中に拡散層42を設けた後、拡散層4
2以外の部分に絶縁膜43を形成する。しかる後
にAl膜441を例えば0.4μの厚さで堆積させる。
次いで、Al−Ti−Si三元素からなる金属膜45
を500〜1000Åの厚さで形成する。このAl−Ti−
Siの三元素からなる金属膜45の形成方法および
条件は先の実施例と同様とする。この後再度Al
膜442を形成する(第4図a)。
Next, another embodiment of the present invention will be described. FIGS. 4a and 4b are process sectional views of the embodiment. After providing the diffusion layer 42 in the silicon substrate 41, the diffusion layer 4
An insulating film 43 is formed on portions other than 2. Thereafter, an Al film 44 1 is deposited to a thickness of, for example, 0.4 μm.
Next, a metal film 45 consisting of the three elements Al-Ti-Si is formed.
is formed with a thickness of 500 to 1000 Å. This Al−Ti−
The method and conditions for forming the metal film 45 made of the three elements Si are the same as in the previous embodiment. After this, Al again
A film 44 2 is formed (FIG. 4a).

上記の様なAl441/Al−Ti−Si45/Al44
積層膜を形成後、300〜500℃で熱処理を施こす
と、合金化して内部にAl−Ti−Si合金膜45′が
形成されたAl配線層が得られる(第4図b)。
Al44 1 /Al-Ti-Si45/Al44 as above
After the two laminated films are formed, heat treatment is performed at 300 to 500°C to obtain an Al wiring layer in which alloying occurs and an Al-Ti-Si alloy film 45' is formed inside (FIG. 4b).

この実施例によつても、合金膜45′はエレク
トロマイグレーシヨンによるAl原子の流れを均
一にする一方、Alヒロツクの成長を抑止する効
果があり、結果としてAl配線の耐エレクトロマ
イグレーシヨン特性を強化する。又、Siがあらか
じめ含まれている為に拡散接合部の破壊も生じな
い効果を有する。
In this embodiment as well, the alloy film 45' has the effect of making the flow of Al atoms uniform due to electromigration and suppressing the growth of Al hillocks, and as a result, strengthens the electromigration resistance characteristics of the Al wiring. do. Furthermore, since Si is included in advance, it has the effect of preventing destruction of the diffusion bond.

他の実施例を第5図および第6図により説明す
る。第5図の例は、拡散層52が形成されたシリ
コン基板51に絶縁膜53を形成した後、上記実
施例と同様の工程を繰返してAl−Ti−Si合金膜
551,552を内部と表面部に形成したAl膜54
により配線層を形成したものである。これによ
り、Al膜54のヒロツク発生防止と耐エレクト
ロマイグレーシヨン特性の向上がより効果的に達
成される。第6図の例は、拡散層62が形成され
たシリコン基板61に絶縁膜63を形成した後、
内部に2層のAl−Ti−Si合金膜651,652を形
成したAl膜64を形成したものである。このよ
うに、Al配線中に多層にわたつてAl−Ti−Si合
金膜を形成することで耐エレクトロマイグレーシ
ヨン特性は更に向上する。
Another embodiment will be explained with reference to FIGS. 5 and 6. In the example shown in FIG. 5, after an insulating film 53 is formed on a silicon substrate 51 on which a diffusion layer 52 is formed, the same process as in the above embodiment is repeated to form Al-Ti-Si alloy films 55 1 and 55 2 inside. and Al film 54 formed on the surface.
The wiring layer is formed using the following methods. This makes it possible to more effectively prevent the occurrence of hillocks in the Al film 54 and improve electromigration resistance. In the example of FIG. 6, after forming an insulating film 63 on a silicon substrate 61 on which a diffusion layer 62 is formed,
An Al film 64 is formed in which two layers of Al-Ti-Si alloy films 65 1 and 65 2 are formed. In this way, by forming a multilayer Al-Ti-Si alloy film in the Al wiring, the electromigration resistance is further improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は従来の製造方法による素
子の断面図、第3図a〜dは本発明の一実施例の
工程を示す素子断面図、第4図a,bは本発明の
他の実施例の工程を示す素子断面図、第5図およ
び第6図は更に他の実施例による素子断面図であ
る。 31,41,51,61……シリコン基板、3
2,42,52,62……拡散層、33,43,
53,63……絶縁膜、34,44,54,64
……Al膜、35,45……Al,Ti,Siからなる
金属膜、35′,45′,551,552,651
652……Al−Ti−Si合金膜。
1 and 2 are cross-sectional views of an element according to a conventional manufacturing method, FIGS. 3 a to d are cross-sectional views of an element showing steps of an embodiment of the present invention, and FIGS. FIGS. 5 and 6 are cross-sectional views of elements according to still other embodiments. 31, 41, 51, 61...Silicon substrate, 3
2, 42, 52, 62...diffusion layer, 33, 43,
53, 63... Insulating film, 34, 44, 54, 64
...Al film, 35,45...Metal film consisting of Al, Ti, Si, 35', 45', 55 1 , 55 2 , 65 1 ,
65 2 ...Al-Ti-Si alloy film.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板に絶縁膜を介してAl膜またはAl
を主成分とする合金膜からなる配線層を形成する
工程を含む半導体装置の製造方法において、前記
配線層の内部または表面層の少くとも一方にAl,
Siおよび他の金属の三元素が混合された金属膜を
形成し、熱処理を施して前記三元素からなる合金
膜または金属間化合物膜を形成する工程を有する
ことを特徴とする半導体装置の製造方法。
1 Al film or Al film is applied to the semiconductor substrate via an insulating film.
A method for manufacturing a semiconductor device including a step of forming a wiring layer made of an alloy film mainly composed of Al,
A method for manufacturing a semiconductor device, comprising the steps of forming a metal film containing a mixture of three elements, Si and other metals, and performing heat treatment to form an alloy film or an intermetallic compound film made of the three elements. .
JP9523183A 1983-05-30 1983-05-30 Manufacture of semiconductor device Granted JPS59219940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9523183A JPS59219940A (en) 1983-05-30 1983-05-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9523183A JPS59219940A (en) 1983-05-30 1983-05-30 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59219940A JPS59219940A (en) 1984-12-11
JPH0220142B2 true JPH0220142B2 (en) 1990-05-08

Family

ID=14131983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9523183A Granted JPS59219940A (en) 1983-05-30 1983-05-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59219940A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4200809C2 (en) * 1991-03-20 1996-12-12 Samsung Electronics Co Ltd Method for forming a metallic wiring layer in a semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380184A (en) * 1976-12-24 1978-07-15 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

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