JPH0220196B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of an optimal block detection circuit for a motion compensated interframe coding method for image data.

A motion compensated interframe coding method is used as a highly efficient coding method when image data is band-compressed and transmitted.

In this method, when the previous frame image that becomes the predicted value shown in Figure 2B moves to the current frame image shown in Figure 2A, the difference between the previous frame and the current frame is taken as is. Since there is a lot of information,
The frame is divided into blocks, and the block most similar to the image of block A shown in FIG. 2A is cut out from the previous frame shown in FIG. 2B, and
(In this case, it is assumed to be B.) Indicates the cumulative value of the difference value of pixels from block B of the previous frame, which is the predicted block, and the position of block B so that block B can be recognized on the receiving side. , vector information between block A and block B indicated by the arrow in FIG. 2A is transmitted.

Generally, the difference value of image data between frames is often statistically close to 0, and the vector representing the distance between a block and a predicted block is also often statistically close to 0.

Therefore, in order to reduce the transmission amount when transmitting the actual accumulated value and vector information of the above-mentioned difference values, in the case of difference values, as shown in Fig. 3, the closer the difference value is to 0, the more Reduce the number of bits assigned to the code,
The larger the difference value, the larger the number of bits allocated to the code is used.

In the case of vector information, as shown in Figure 4,
A variable length code is used in which the shorter the vector, the smaller the number of code bits allocated, and the longer the vector, the larger the number of code bits allocated.

Therefore, when detecting the optimal block from the previous frame, the code length of the sum of the cumulative value of the code using the variable length code as the difference value of the pixels in the block and the code using the vector information as the variable length code is If the shortest block is detected as the optimal block, the amount of transmitted information can be minimized.

It is desirable that the optimum block detection circuit for detecting this optimum block has a small circuit scale.

[Conventional technology]

FIG. 5 is a block diagram of a conventional optimal block detection circuit.

In Fig. 5, one block of the current frame is input to subtracter 1 (input block), and one block of the previous frame is input to subtracter 1 (input block).
The block is input to a subtracter 1 as a prediction block, a difference value is determined, and a code conversion circuit 2 converts it into a variable length code corresponding to this difference value, and sends it to an adder 3.

The output of the selector 11 is input to the other input of the adder 3, and the adder 3 adds both of them, resulting in 1
The output of the one data delay element (FF) 5 is sent to the adder 12 and is also input to the selector 11.

0 is also input to the selector 11, and the selector 11 selects 0 and inputs it to the adder 3 only when the first data of the difference value from the predicted block is transmitted from the subtracter 1. In other cases, the output of the 1-data delay element (FF) 5 is selected and input to the adder 3.

Therefore, the adder 3 calculates the cumulative value of the code using the pixel difference value between the input block and the prediction block as a variable length code, and inputs this to the adder 12.

On the other hand, the vector information is converted into a variable length code by the vector information code conversion circuit 4 and sent to the selector 8.
It is also input to the adder 12, and is added to the above cumulative value, and the flip-flop 6
is sent to and latched by the block clock.
It is input as A to the comparator circuit 7 and selector 8.

The comparison circuit 7 and the selector 8 are input with the value B obtained for the previous prediction block in the same manner as above, and the selector 8 is input with a code D obtained by converting the vector information of the previous prediction block into a variable length code. is input, the comparison circuit 7 compares A and B, and if the smaller value is, for example, A, the selector 8 selects A and C, adds the flip-flop 9, and converts the vector information into a variable length code. The added value of the code, the cumulative value obtained by converting the difference value into a variable length code, and the code obtained by converting vector information into a variable length code is latched and output.

By repeating this operation, it is possible to detect the optimal block, which is the predicted block with the smallest amount of code to be transmitted.

[Problem that the invention seeks to solve]

However, the optimum block detection circuit described above requires two adders and has a problem in that the circuit size is large.

An object of the present invention is to provide an optimal block detection circuit having a small circuit scale and capable of detecting an optimal block using only one adder.

[Means for solving problems]

The above problem is caused by a latch circuit that inputs the output of the code conversion circuit to an adder and latches the output in block units through a 1 data delay element, and also requires the output of the vector information code conversion circuit and the 1 data delay element.
The output of the data delay element is input to the selector, and when the difference value from the prediction block is first obtained, the output of the vector information code conversion circuit is selected from the selector, and at other times, the output of the vector information code conversion circuit is selected. Select the previous value of the output data and input it to the adder, and at the output of the latch circuit, the difference value for each pixel between the block of the current frame and the predicted block of the previous frame is code-converted. This problem can be solved by calculating the sum of the cumulative value of the code converted into a variable length code by the circuit and the code obtained by converting the vector of the prediction block into the variable length code by the vector information code conversion circuit.

[Effect]

According to the present invention, the output of the code conversion circuit is input to the adder, the output is added to one data delay element, and the output of the vector information code conversion circuit and the one
The output of the data delay element is input to the selector, and when the difference value from the prediction block is first obtained, the output of the vector information code conversion circuit is selected from the selector, and at other times, the output of the vector information code conversion circuit is selected. The output value of one data previous is selected and inputted to the adder, and the difference value for each pixel between the block of the current frame and the predicted block of the previous frame is converted into a variable length code by a code conversion circuit. Since the cumulative value of the prediction block and the code obtained by converting the vector of the prediction block into a variable length code using the vector information code conversion circuit are calculated, the number of adders can be reduced to one, and the circuit size can be reduced. It can be made smaller.

〔Example〕

FIG. 1 is a block diagram of an optimal block detection circuit according to an embodiment of the present invention.

The differences in Fig. 1 from the conventional example shown in Fig. 5 are as follows.
Except for the adder 12, the output of the 1-data delay element 5 and the selector 11 inputting 0 are connected to the output of the 1-data delay element 5 and the vector information code conversion circuit 4.
This is the point where the output of is converted to the input selector 10.

This different point will be mainly explained below.

In the case of FIG. 1, the output of the code conversion circuit 2 is input to the adder 3, the output is added to the 1 data delay element 5, and the output of the vector information code conversion circuit 4 and the output of the 1 data delay element 5. is input to the selector, and when the difference value from the predicted block is first calculated, the vector information code conversion circuit 4 is input from the selector 10 to the vector information code conversion circuit 4.
At other times, the value of one data previous, which is the output of the one data delay element 5, is selected and input to the adder 3.

Therefore, the adder 3 converts the pixel difference value between the input block and the prediction block into a variable-length code in the code conversion circuit 2, and outputs the cumulative value of the code and the vector of the prediction block to the vector information code conversion circuit 4. The value added to the code converted into a variable length code is calculated.

Therefore, the adder 12 shown in FIG. 5 can be removed and the circuit scale can be reduced.

〔Effect of the invention〕

As described above in detail, according to the present invention, an optimal block detection circuit with a small circuit scale can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an optimal block detection circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a motion compensated interframe coding method, and FIG. FIG. 4 is a diagram showing the relationship, FIG. 4 is a diagram showing the number of code allocation bits depending on the distance of vector information, and FIG. 5 is a block diagram of a conventional optimal block detection circuit. In the figure, 1 is a subtracter, 2 is a code conversion circuit,
3 and 12 are adders, 4 is a vector information code conversion circuit, 5 is one data delay element, 6 and 9 are flip-flops, 7 is a comparison circuit, and 8, 10, and 11 are selectors.

Claims (1)

[Claims] 1. In order to detect the optimal block of the motion compensated interframe coding method for image data, a code conversion circuit calculates the difference value for each pixel between the block of the current frame and the predicted block of the previous frame. Convert it into a variable length code to find the accumulated value in block units, and add the value obtained by converting the vector with the predicted block to the variable length code in a vector information code conversion circuit to the accumulated value, and perform the addition. The value
In the optimal block detection circuit, which detects the minimum prediction block of the added value by comparing it with the value added to the previous prediction block and selecting and holding the smaller value, the output of the code conversion circuit is sent to the adder. In addition to the latch circuit that latches the output in block units through one data delay element, the output of the vector information code conversion circuit and the one
The output of the data delay element is input to the selector, and when the difference value from the prediction block is first obtained, the output of the vector information code conversion circuit is selected from the selector, and at other times, the output of the vector information code conversion circuit is selected. Select the previous value of the output data and input it to the adder, and at the output of the latch circuit, the difference value for each pixel between the block of the current frame and the predicted block of the previous frame is code-converted. The optimum method is characterized in that the sum of the cumulative value of the code converted into a variable length code by the circuit and the code obtained by converting the vector of the predicted block into the variable length code by the vector information code conversion circuit is calculated. Block detection circuit.