JPH0547157B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A parallel processing circuit that performs processing such as intraframe interpolation encoding of images, which delays m phases of n phases of parallel input data using m delay elements. By doing so, equivalent parallel input data of (n+m) phases is created and parallel processing is performed.

[Fields of industrial advantage and use]

The present invention relates to a parallel processing circuit for image signals, etc.
The parallel processing circuit of the present invention is a parallel processing circuit that can relatively easily realize interpolation DPCM encoding of ultra-high-speed signals such as high-definition TV signals with a bandwidth of 20 MHz with a small-scale circuit consisting of low-speed arithmetic elements. Applicable.

In image data transmission, the transmission path may not have the bandwidth necessary for data transmission. As a means of sending data to be transmitted to a receiving side using such a transmission path, a means of compressing the data to within the bandwidth of the transmission path is adopted. For example, interpolation is one way to do this.
There is a DPCM encoding method.

Even with this interpolation DPCM encoding method, as the signal to be encoded becomes faster, the circuit elements for interpolation DPCM encoding processing are required to have higher speed.

Therefore, there is a need for the development of a means that can realize high-speed interpolation DPCM encoding of a signal to be encoded, even though the circuit scale is relatively small and the elements used therein are low-speed.

[Conventional technology]

A typical interpolation DPCM encoding method for image signals is
As shown in FIG. 6, with respect to the current value a ₁ , a left value a ₂ and a right value a ₃ on the same scanning line, a value directly above a ₄ on the upper scanning line, and a value immediately below a ₅ on the lower scanning line.
The purpose is to generate a predicted value using the four points and perform differential encoding. Specifically, the predicted value for the current value a ₁ is calculated by taking the average of each value a ₂ to a ₃ . ,
Furthermore, the difference between this predicted value and the current value _a1 is calculated and encoded.

FIG. 7 is a block diagram showing an interpolation DPCM encoder for implementing the above method. In the figure, the encoder delays the input signal by (1 scanning line - 1 sample) and outputs the left value a ₂ and the direct value a ₅ (1 line - 1 sample), delay elements 7 and 76, input Delay the signal by one sample and convert the current value a ₁ and the right value
1 sample delay elements 1 and 8 outputting a ₃ , each value a ₂
Adder 4 that adds ~ _a5 , 1/4 multiplier 5 that calculates the predicted value by calculating the average of each value _a2 ~ _a5 , and subtractor that calculates the difference (prediction error) between the predicted value and the current value. 3. It includes a quantizer 6 that quantizes the prediction error from the subtracter 3.

According to the configuration shown in FIG. 7, when the sampling frequency is up to about 20 MHz, the intended interpolation DPCM encoding can be achieved relatively easily using TTL or MOS devices.

However, when the input image signal becomes a high-definition TV signal with a bandwidth of about 20MHz, the sampling frequency needs to be at least 40MHz, so TTL or MOS is required.
The device uses its intended interpolation in terms of operating speed.
DPCM encoding cannot be realized. Furthermore, even when using an ECL device, it is difficult to realize this from the viewpoint of operating speed.

Therefore, in Japanese Patent Application No. 60-191311, the applicant
This paper discloses a parallel interpolation DPCM encoding circuit that can perform interpolation DPCM encoding of an ultra-high-speed encoded signal using a small-scale circuit consisting of low-speed elements.

FIG. 4 is a block diagram showing such a parallel interpolation DPCM encoding circuit. This encoding circuit performs interpolation encoding using four pixels on the upper, lower, left and right sides by four-phase expansion. That is, as shown in FIG. 5, the time series input data string is expanded into four phases of parallel input data (for example, N ₃ to _{N 4} , P ₁ to P ₄ , L ₁ to _{L 4} ), and each Interpolation DPCM encoding is performed in parallel for each phase. Its configuration is shown in Fig. 4, in which the input data of each phase, for example N ₁ to N ₄ , is delayed by (1 scanning line - 1 sample) and the left side value a ₂ of each phase is output (1 line - 1 sample). ) Delay elements 71 to 74, 1 sample delay elements 11 to 14 that delay the input data in each phase by one sample and output the current value _a1 , delay the input data in each phase by one sample and output the current value a1, respectively. 1-sample delay elements 81 to 84 each outputting ₃ , the first
A delay element 75 that delays the output of the phase 1 sample delay element 81 by (1 scanning line - 1 sample) and outputs the immediate value _a4 for the 4th phase (1 line - 1 sample), each value in each phase adders 41 to 44 that add values _{a 2} to _{a 5} ; 1/4 multipliers 51 to 54 that calculate a predicted value by calculating the average of each value a ₂ to _{a 5} in each phase;
It consists of subtractors 31 to 34 that take the difference (prediction error) between the predicted value and the current value in each phase, and quantizers 61 to 64 that quantize the prediction error from the subtractors 31 to 34 in each phase.

According to this configuration, the parallel input data P ₁ to P ₄ of the current cycle are sent to the output sides of the one-sample delay elements 11 to 14, and the parallel input data N ₁ to N _{4 of the next cycle are sent to the output sides of the one-sample delay elements 11 to 14.}
is (1 line - 1 sample) delay elements 71 to 74
The input data L ₁ in the parallel input data of the previous cycle is (1 line - 1 sample)
appears at the output of delay element 75. Therefore, the value _a4 directly above the current value _a1 of the input data _P1 is (1 line - 1 sample) the input data at the input of the delay element 74.
The value _{a 5 immediately} below the current value a ₁ of the input data P ₄ is obtained from the output data L ₁ on the output side of the delay element 75 (1 line - 1 sample), thereby interpolating in each phase. DPCM encoding becomes possible.

[Problem that the invention seeks to solve]

However, the encoding circuit with such a configuration is
(1 line - 1 sample) Many large-scale line memories are required as delay elements, leading to an increase in the size and price of the device.

[Means for solving problems]

FIG. 1 is a principle diagram of a parallel processing circuit according to the present invention. In the figure, 100 ₁ to 100 _n are delay elements that provide a delay of 1 data length, 101 ₁ to 101 _n are delay elements that provide a delay of x samples (x is 0 or a positive integer), and 102 ₁ to 102 _o are This is a processing circuit such as a prediction error signal generation circuit that generates a prediction error signal.

This parallel processing circuit receives n time series input data sequences.
(n is an integer of 2 or more) Parallel input data expanded into phases is input. m delay elements 100 ₁ ~
100 _n outputs delayed parallel input data of m phases by delaying parallel input data of m (m is an integer from 2 to n) phases by one data length among n phases.
Further, the processing circuits 102 ₁ to 102 _o generate n-phase processed outputs using (n+m)-phase parallel input data consisting of n-phase parallel input data and m-phase delayed parallel input data.

[Effect]

In addition to the n-phase parallel input data, m-phase delayed parallel input data obtained from m delay elements 100 ₁ to 100 _n are used to equivalently (n+m)
Create phase parallel input data. And this (n+
m) delay element 101 using phase parallel input data;
₁ to 101 _n-1 and 103 ₂ to 103 _n and processing circuit 1
02 ₁ to 102 _o , n-phase parallel output data such as a prediction error signal is generated.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing a parallel processing circuit as an embodiment of the present invention. In the figure, 10 to 15,
80 to 83 are each one sample time delay element, 20 and 21 are each one scanning line delay element, 30 to 33 are each a subtractor, 40 to 43
are adders, 50 to 53 are 1/4 multipliers, 6
0 to 63 are quantizers.

P ₁ to _{P 4} are parallel input signals expanded into four phases, respectively, and these parallel input signals P ₁ to _{P 4} are guided to delay elements 11 to 14, respectively, and among them, parallel input signals P ₃ and P ₄ is the delay element 20,
21 to delay elements 15 and 10, respectively. As a result, parallel input signals N ₃ and N ₄ corresponding to the third and fourth phase parallel input signals of the previous cycle appear on the output sides of the delay elements 20 and 21. As a result, N ₃ , N ₄ , P ₁ to P ₄ are equivalent to six-phase parallel input signals.

The input side of the delay elements 10 to 13 is the parallel input signal N ₄ , the left side value a ₂ of P ₁ to P ₃ , and the output side is the current value
a ₁ appears respectively, and by passing the current value a ₁ of the parallel input signals N ₄ , P ₁ to P ₃ further through the delay elements 80 to 83, the right value a ₃ appears on the output side, respectively.

Adders 40 to 43 add the current value a ₁ of the fourth phase of the previous cycle and the respective values a ₂ to a ₅ in the vicinity of the current value a ₁ of each of the first to third phases of the current cycle, respectively. Each output signal of adders 40 to 43 is divided into 1/4 by 1/4 multipliers 50 to 53 to obtain a predicted value (average value). Subtractors 30 to 33 calculate the difference (prediction error) between this predicted value and the current value for each phase.
This circuit calculates and outputs it to the quantizers 60 to 63.

The operation of the circuit of FIG. 2 will be explained below with reference to FIG. FIG. 3 is a diagram showing four-phase expanded parallel input signals, where N ₁ to _{N 4} are the parallel input signals of the previous cycle, P ₁ to _{P 4} are the parallel input signals of the current cycle,
_L1 to _L4 are parallel input signals for the next cycle.

In this circuit, the immediate value a ₄ for calculating the predicted value of the current value a ₁ of the parallel input signal P ₁ is used as the parallel input signal N corresponding to the fourth phase of the previous cycle obtained through the delay elements 2 and 10. Calculated using ₄ . Further, the predicted value of the current value a ₁ of the parallel input signal N ₄ is similarly calculated using the parallel input signal N ₃ corresponding to the third phase of the previous cycle obtained through the delay elements 20 and 15. In addition, parallel input signals of other phases
Predicted values of P ₂ and P ₃ are calculated using respective values of neighboring phases.

The predicted value is obtained as described above, and the parallel prediction error signal is obtained as the output signal after four-phase parallel interpolation predictive coding.
Try to get E ₁ to _{E 4} .

Various modifications are possible in carrying out the invention. For example, in the above-mentioned embodiment, an image signal expanded into four phases was explained, but it may be a signal expanded into other multiphases. In addition, in the embodiment of the present invention, for the current value a ₁ , the left value a ₂ and the right value a ₃
is used, but if this is not used, 10 to 1
The one sample time delay elements 4, 15, 80 to 83 are no longer necessary. In addition, in the embodiment of the present invention, only the value a ₄ directly above and the value directly below a ₅ are used for the current value a ₁ , but in addition, the value of the upper phase and the value of the lower phase are used for processing. Good too. In this case, the number of delay elements for one scanning line needs to be increased depending on the number of phases used. Furthermore, the present invention can be applied to systems other than interpolation coding as described in the embodiments, and can be applied to devices that perform processing using information spanning multiple lines in a frame in parallel, and can be used, for example, in two-dimensional filters. can.

〔Effect of the invention〕

According to the present invention, it is possible to process an ultra-high-speed coded signal such as a high-definition image signal using DPCM or the like using a small-scale circuit made up of low-speed elements. Furthermore, the device of the present invention does not require a large number of line memories, and the device can be made even smaller and less expensive.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram of a parallel processing circuit as an embodiment of the present invention, and Fig. 3 is a block diagram of a parallel processing circuit as an embodiment of the present invention.
The figure is a diagram for explaining the operation of the circuit in Figure 2.
FIG. 4 is a block diagram showing a parallel interpolation DPCM encoding circuit as a related technology; FIG. 5 is a diagram for explaining the operation of the circuit shown in FIG. 4; The figure is an explanatory diagram of the interpolation DPCM encoding method, and FIG. 7 is a block diagram of the interpolation DPCM encoder of the technique. 10-15, 80-84...1 sample time delay element, 20, 21...1 scanning line delay element, 3
0-34...Subtractor, 40-44...Adder, 5
0...1/4 multiplier, 60-64...quantizer.

Claims (1)

[Claims] 1 Time series input data sequence is n (n is an integer of 2 or more)
Parallel input data P ₁ to _{P o} expanded into phases is input, and the parallel input data of m (m is an integer between 2 and more and n or less) phase among the n phases is delayed by one data length, and the parallel input data of m phase is Output delayed parallel input data m
Using delay elements 100 ₁ to 100 _n and (n+m)-phase parallel input data consisting of the n-phase parallel input data and the m-phase delayed parallel input data, the n-phase processing output E A parallel processing circuit comprising n processing circuits 102 ₁ to 102 _o that obtain ₁ to E _o .