JPH022341B2 - - Google Patents

Description

Claim 1 A plurality of line adapters 400, 500; LA0, LA1, connected to a host computer (not shown) and a plurality of remote terminals (not shown), respectively.
A microprocessor means 600 controls the data transfer operation between LA2 and LA3, and each line adapter
LA0 to LA3 are USART508, 510, 51
2,514 addressable registers and timers 507, 509, 511, 513 addressable registers, and said microprocessor means 600 has multiplexer means 504, 5
06 to said line adapters LA0-LA3, and includes an I/O bus means 10 having separate bit lines connected to said line adapters LA0-LA3 via a bus controller transceiver 503 and data bus means (DAL bus). A data communications subsystem (FIG. 1, 30
0), the USART508,510,5
12,514 and timer 507,509,51
a read/write system for communicating with selected ones of 1,513 registers, the system comprising: (a) said microprocessor means 600 for executing data transfer instructions from said host computer; , said microprocessor means 6
00 is (a1) address data (i) for selecting one of the registers of the USART 508 or the register of the timer 507, a specific line adapter (one of LA0 to LA3), and the multiplexer means 504, 506. a microprocessor 6 for generating control data (ii) for selecting the relevant specific multiplexer of the
00, the microprocessor 600
(a1a) means for reading data from or writing data to a selected one of said USART 508 registers or timer 507 registers in said selected line adapter LA0 (FIG. 3); (a1b) The line adapters LA0 to LA3 and the multiplexer means 504, 506
said first and second output control registers 37, 38 for holding said control data and said address data for communicating to said microprocessor means 600, further comprising: (a2) said selected associated (a2a) said I/O bus means 10 having a plurality of separate bit lines for conveying data from a particular multiplexer to said microprocessor 600; 600, the line adapter LA0~LA3
said read/write system comprises a series of jumpers for conveying service request signals from each of said I/O bus means 10 via gate means G ₀ to _{G 3} to a separate bit line of said I/O bus means 10; (b) further comprising a plurality of said line adapters LA0-LA3, each of said line adapters being connected for data transfer to and from a remote data terminal, said line adapters LA0-LA3 being connected for data transfer to and from said remote data terminals, said bus controller transceiver means 503; connected for data transfer from the microprocessor 600 and further providing said I/O from a selected line adapter to said microprocessor 600 via said bus controller transceiver means 503 and said selected associated particular multiplexer. connected for data transfer by bus means 10 and said line adapter LA0
(b1) a plurality of registers of said timer 507 for receiving and holding data for adjusting the time sequence of data transfer operations to and from said remote data terminal; b2) a plurality of registers of said USART 508 for receiving and holding data for controlling data transfer operations to and from said selected line adapter; and (b3) via said associated gating means. means G ₀ to G ₃ for generating said service request signal to said microprocessor; (b4) activating an identifier input to said associated multiplexer to generate a timer register or
means for identifying to the microprocessor which USART registers are to be written to or read by the microprocessor, the read/write system comprising: (c) the multiplexer means 504; 506, each of said multiplexers associated with each of said line adapters for receiving output data from said selected line adapter LA0 for passing to said microprocessor 600, said multiplexer means 504, 506
(c1) the bus controller transceiver 50;
(c2) said data bus means (ROUT) from said selected line adapter for conveying line adapter output data to said selected associated multiplexer via a plurality of said multiplexers; (c2a) inputting an identifier for identifying the type of function of the related line adapter; and (c2b) inputting an identifier for identifying the type of function of the related line adapter.
(d) an input from said gating means indicating whether a USART register or a timer register is requesting service of said microprocessor 600; , said associated multiplexer, and associated gating means G ₀ ~
( _d1 ) activated by the microprocessor means 600 to select a specific line adapter LA;
(d2) selecting said timer register or said USART register in said selected line adapter to enable said microprocessor; 60
(e) component selection logic means (DESF) for activating said address data from zero to select a particular register; said bus controller transceiver means 5 connected to receive said control and address data from a microprocessor 600;
03, the bus controller transceiver means includes: (e1) means for receiving and forwarding data from the selected line adapter LA0 to the selected associated multiplexer, and the read/write system comprises: (f) further comprising the plurality of gate means G ₀ to G ₃ ;
Each of said gating means is associated with each of said line adapters and is operative to generate said service request signal to said microprocessor 600 for a particular line adapter in need of service; (g) a read/write system further comprising the host computer connected to the microprocessor 600 and generating data transfer commands to the microprocessor means; 2 (a) further comprising a plurality of automatic calling device output registers ( _ACUOR0 to _ACUOR3 ), each of the line adapters LA0 to LA3 receiving dialing data from the microprocessor 600 and transmitting telephone calls to the associated line adapter. a dedicated automatic paging device output register is provided that can be used to dial a line connection; (b) receiving dialing data from said dedicated automatic paging device output register and transmitting said remote data from said associated line adapter; automatic calling device 50 for establishing a telephone line connection to the terminal;
5. The system of claim 1, further comprising: 5 m. FIELD OF THE INVENTION This disclosure relates to data communication systems that use multiple line adapters, each handling separate communication circuits to data terminals. CROSS-REFERENCE TO RELATED PATENT APPLICATIONS This disclosure also includes references to Richard A. Loskorn, Philip
Invented by D. Biehl and Robert D. Catiller, United States Patent Application No. 355135 and
Also related are two applications entitled "Byte-Based Line Adapter System" and "Bit-Based Line Adapter System," filed March 5, 1983 as No. 355,134. Several patents are incorporated by reference that form the background and description of the microprocessor used in the line adapter of this disclosure. These patents included in the references are U.S. Pat. ” United States Patent No.
4291372, United States Patent No. 4291372, entitled “Microprocessor System to Facilitate Instruction Repetition”
4292667, and “Input for Digital Data Processing Systems −
No. 4,189,769 entitled ``Output Subsystem.'' SUMMARY OF THE INVENTION A read and write system for reading data from or writing data from selected registers of each of a plurality of line adapters. , I/O controlled by microphone processor
form a subsystem. Each line adapter is connected to a remote data terminal for data transmission,
A selection means is provided for selecting one of the internal registers installed in the specific line adapter, its USART device, and timer device. After the microprocessor selects a particular line adapter, which is ``designated'' by turning on the ``designated'' flip-flop associated with the selected line adapter, the microprocessor stores the register address via a PUT operation instruction. and loads one of its output control registers (38, FIG. 3).
The other PUT operation instruction is initiated by the microprocessor and transfers the pointer (USART chip selection) to the other output control register (37, Figure 3).
Load into. Then, by using the PUT and GET operators, the readable signal transfers data from the selected register of the USART to the I/O bus for input to the microprocessor after the chip select signal is removed. let In a similar manner, selected registers in the timer device of the selected line adapter are “read”
can be done. Control information data may then similarly be "written" to selected registers of the USART device or timer device of the selected line adapter to control the line adapter's operation with its remote data terminal.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a data communications input/output subsystem with a slide-in card that fits into the backplane of the base module and has a frontplane connection therebetween. FIG. 2 is a block diagram of a multiline adapter card. FIG. 3 is a block diagram of the state machine processor that controls the operation of the line adapter. FIG. 4 is a block diagram of a single byte standard line adapter. FIG. 5 is a diagram of the logic circuitry used to select memory or other components for any line adapter. FIG. 6 is a schematic diagram of a circuit for identifying a line adapter or its subcomponents. FIG. 7 is a timing diagram for dialing the automatic calling unit (ACU). Figure 8a shows circuitry for addressing and loading selected ACU output registers. FIG. 8b is a timing diagram showing the sequence of operations. FIG. 9 is a block diagram showing the overall configuration of a read/write system according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The line adapter selection means of this disclosure is designed for use as part of a line subprocessor (often referred to as a frame validating data link processor) as part of a data communications input/output subsystem. Ru. FIG. 1 illustrates a data communications input/output subsystem in which a state machine processor card 600 operates in a manner comparable to various types of line adapters. Single line adapter circuit 700 connects card 4
Quaternary line adapters such as those designated 00 and 500 are used similarly. These quaternary line adapters constitute a system of four addressable line adapters, and each line adapter can handle a single data communication line terminal via an electrical interface. FIG. 4 shows a block diagram of a "single" byte-based line adapter system. The remote data set or data input-output terminal is configured with a timer 50.
7 and USART 508. This input-output circuit has input/output
Along output bus 10 is a state machine processor 600.
Alternatively, it is coupled to a transceiver bus controller 503 that can route data to multiplexer 504 for communication to RAM buffer 550m. Data in the state machine processor is transferred from state machine output control registers 38 (FIG. 3) to bus 17 for transmission to input-output circuit means.
2 to the transceiver bus controller 503. Multiplexer 504 receives control signals from data link interface (DLI) device 700 of FIG. 1 in addition to other control signals that identify the device within the line adapter system. Also provided is an autocaller output register 505 that can receive signals useful for dialing remote terminals on the telephone line. FIG. 2 is a block diagram of a "quad" line adapter used for byte-based protocol operation. Input-output circuit means coupled to remote terminals include 507, 508 (timer 0 and USART
It consists of four basic devices such as 0). Similarly, input-output services to remote terminals are provided by timers 509 and USART1 designated 510. Similarly, devices 511 and 512 constitute operating devices for other remote terminals, as devices 513 and 514 do for other remote terminals. As discussed with reference to FIG. 4, the line adapter uses a transceiver bus controller 503 and a set of multiplexers 504 and 506.
Multiplexers such as 504 and 506 are
It is essentially a set of "dual" operating multiplexers that receive control signals from two different input-output units. Multiplexer 504 receives input signals from line adapters 0 and 1 while multiplexer 506 receives input signals from line adapters 2 and 3 of FIG. In response to the automatic pager output register of FIG. 4, the quad line adapter of FIG. 2 uses four such ACU output registers. Also provided in the Quaternary Line Adapter (FIG. 2) are special sets of RAM buffer memory designated 550m ₁ and 550m ₂ . FIG. 3 is a block diagram of a state machine microprocessor used to control a single line adapter or multiple line adapters. The state machine processor (often designated as a UIO state machine) is mounted on a chip circuit board that can be inserted as a slide-in card into a base module (FIG. 1) that couples to the backplane. The state machine is connected to the application logic circuitry through a front plane connector as shown in FIG. A detailed description of the elements and use of the UIO state machine is the subject of several prior art articles included in the references. These patents were invented by Robert D. Catiller and Brian K. Forbes and are entitled "Digital System for Data Transfer Using a General Purpose Input-Output Microprocessor," United States Patent No.
4293909, invented by Brian K. Forbes and Robert D. Catiller, and entitled “Microprocessor System with Specified Instruction Format,” U.S. Patent No. 4291372, invented by Robert D. Catiller and Brian K. Forbes. No. 4,292,667 entitled "Microprocessor System to Facilitate Instruction Repetition". The use of a higher-level computer to operate in conjunction with an input/output subsystem that uses unique instructions called input/output descriptors, data link descriptors, and result descriptors is referred to as the “input-output subsystem for digital data processing systems.” ”, Darwen J. Cook and Donald A. Millers,
U.S. Pat. Figure 5 shows the RAM for a single line adapter card.
Certain logical states on the DLI/LA card 700 that are used to select or "designate" a buffer memory or a selected memory within a particular one of the four line adapter memories on the quad line adapter card. This is a diagram. Shown as RAM storage means 550m in FIG. 5 is the specific memory used for a single line adapter. However, in the “multiple” line adapter state,
Each line adapter has local RAM memory 5
50 m ₁ , 550 m ₂ and has a similar selection system for selecting the particular memory associated with that line adapter, as shown in FIG. In Figure 5, the address line (MADDRnn) from the state machine processor is connected to comparator 1.
Connected to 00c and RAM buffer 550m. The chip selection signal CS/ is the comparator 10
0c and the buffer memory 550 by means of logic signals from the designated flip-flop (DESF).
is activated for m. A proprietary jumper bit provides input from input/output bus 10 to a designated flip-flop to specifically identify any selected buffer memory in the system. The particular bit line of input/output bus 10 is
The selection to be made is set by state machine processor 600 of FIG. “Byte-oriented” line adapter Line subprocessor (frame recognition data link processor and/or line subprocessor)
The functional section of DLP (also known as DLP) is a line adapter called a "byte-based line adapter." This is also often referred to as a "character-based line adapter." A data communications line adapter essentially interfaces on one end to a data communications line "electrical interface" and on the other end.
A device that interfaces with a processor is designated as UIO state machine 600 (UIOSM).
The primary functions of a line adapter are to serialize ``bit'' information into ``byte'' information and from ``byte'' information to ``bit'' information, provide timing, generate requests for service, provide RAM memory, An automatic paging interface is provided and a connection is provided to a data communication line and a compatible level converter. Byte-based line adapters also (i)
It is configured into two basic shapes designated as (ii) a quadruple line adapter and (ii) a single line adapter. The single line adapter is part of the line subprocessor, and the single line adapter is allocated on the same board as the data link interface (DLI) circuitry. Line adapters are required regardless of the amount of lines being controlled by the line subprocessor. A quad line adapter essentially includes four line adapters on a board. These boards are typically 10 inch by 13 inch boards that are connected to the backplane of the base connection module (FIG. 1). As shown in FIG. 1, each of the line adapter cards 400, 500 includes a state machine processor 6.
00 and DLI/LA 700 (Data Link Interface - Single Line Adapter). As shown in FIGS. 2 and 4, the connection to the data communication line is through an electrical interface (EI) that connects to a line adapter. There are various types of electrical interface boards that exist and are mounted in different combinations on the quad line adapter. Thus, the only change required is in the electrical characteristics of the electrical interface, while the line adapter remains the same, depending on the electrical characteristics of the data communication circuit. Line adapters 1 through 16 are addressed differently by state machine processor 600, thus each line adapter is uniquely jumped to identify its address. The line adapter must be "designated" to communicate with the state machine processor. Some addressable components may contain write/read data, or in the form of "state" or "control".
Contained on the line adapter with which the state machine processor communicates. The addressable components of a byte-based line adapter are: (i) USART (508, 510, 512, 514,
(Figure 2) (ii) Timer (507, 509, 511, 513,
(Fig. 2) (iii) Automatic call output registers 505 ₀ , 505 ₁ , 5
05 ₂ , 505 ₃ (iv) Automatic call state ACU ₀ , for each ACU
ACU ₁ , ACU ₂ , ACU ₃ (v) Component requirements (devices inside the USART and timers) (vi) Memory (RAM) (single card LA RAM or quad card LA RAM) USART (universal synchronous/asynchronous The receiver/transmitter (formula receiver/transmitter) receives data "bytes" from state machine processor 600 and converts them into serial "bits" for transmission; it also receives serial bit data and converts this into parallel data bytes. Convert to A USART device is initialized by writing to two internal control registers that specify the manner in which it operates. Preferred typical USART for this purpose
Western Digital Corporation, 3128
Redhill A venue, Newport Beach,
Manufactured by California92663 and
It is called the UC1671 and is described in the August 1978 Technical Manual as the UC1671 Asynchronous/Synchronous Receiver/Transmitter. Various bits in this USART unit's internal control registers specify the following: These are synchronous/asynchronous mode, number of bits per character, parity, baud rate, transmission method, and echo mode. Timers used on byte-based line adapters serve two basic functions. (i) as a program timer; and (ii) as a baud rate generator for asynchronous operation. Three independent internal timers are included in each chip, two of which are used by the software for timing purposes with respect to line operations for "transmit" and "receive" operations. A third timer is used to generate a square wave clock signal used by the USART for asynchronous operation. Each timer is independently initialized to indicate the "mode" in which it should operate. Two program timers can activate flag signals to state machine processor 600 when predetermined timing values are reached. Automatic call output register (ACUOR50) in Figure 2
5) are registers loaded with "dial digits" and control information by the state machine processor. The output of this register is the logic signal EIA
Drives a parallel conversion chip that converts to RS-232 voltage. These signals are used by automated calling units (ACUs) such as the Bell 801, which provide dialing capabilities.
to drive. Automatic call state (ACUST0, ACUST in Figure 2)
1, ACUST3) is a means for providing the state or status of the input line from the automatic calling unit (ACU) to the state machine processor 600. The line from the ACU is received by a level converter chip that converts the EIA voltage to TTL logic levels. These logic levels are read by the state machine processor to determine the current situation. The component requests from the line adapter are as follows. That is, (i) USART, (ii) program timer 1, and (iii) program timer 2. These three components can generate "service requests" independently of the others at their own times with respect to their initialization. "Service Request" sends a flag signal to the state machine processor indicating that the line adapter requests service. After the state machine determines which line adapter is requesting service, it must determine which "component" on a particular line adapter is requesting service. The memory on the line adapter consists of 2048 x 17 bit words of RAM for each line. Therefore, each quad line adapter card actually has 8192 x 17 bit words of RAM.
Contains. Single line adapter card (4th
(Figure) includes a RAM 550m of 4096 words, or 1/2 of the data communication line, and the remainder for the DLI 700. Used by software for transmission/reception of RAM message buffers, tables and instructions regarding line operations. Byte-Oriented Line Adapter Operations Designation: When state machine processor 600 executes code for an addressable component on a line adapter (LA), the LA must be "designated." Each line adapter (Figure 5)
includes a flip-flop, the input of which is jumped to a particular bit of the I/O bus of FIG.
To "designate" a line adapter, the state machine processor performs a PUT operation with strobe number 1 and the corresponding bit on the I/O bus must be equal to one. Performing the same operation with the I/O bus bit equal to 0 resets the designated flip-flop, typically shown as "DESF" in FIG. Flag operations: Various components of the line adapter can generate "service requests."
These "service requests" are essentially ORed together to drive a common flag line for all line adapters. The signal line, flag 2/, when active low, informs state machine processor 600 that some line adapter is requesting service. The state machine processor can determine which line adapter is requesting service by performing a GET operation with various fields V-FLD(4:5) equal to 00001. A line adapter does not need to be "designated" to perform this operation. “Register address” in line adapter
The (RESADRn) signals are the five V-FLD signals from the state machine processor. The flag operation associated with FIG. 6 is completed by flag 2/line when low active signals the state machine processor that the line adapter is requesting service. For example, in FIG. 6, if line adapter 0 requests service, then NOR gate G ₀ is activated;
Flag 2/Provides a signal (low) on the line. Upon receiving this signal, the state machine processor initiates a GET operation on the GET flag ID line. This makes the output signal of gate G ₀ , when read by the state machine, identify the particular line adapter, in this case line adapter 0.
Sent to a particular line on the O bus (dedicated to a particular one of the line adapters). Similarly, each line adapter such as 1, 2, 3, etc. has a gate G ₁ , G ₂ or G ₃ that fires flag 2/line and causes the state machine to select the I/O associated with that line adapter. Causes a particular "jumper" connection to be "read" for a line on the bus. Data Bus Structure: With the exception of RAM (Figure 5) or memory 550 m ₁ , m ₂ , all data sent to addressable components on the line adapter is sent to the "second" output control in the state machine processor. Generated from register 38 (FIG. 3).
With the exception of RAM, all data "read" by the state machine processor from addressable components on the line adapter is stored on the I/O bus 10.
to the state machine processor. Referring to FIG. 4 (DLI/LA Data Bus Structure), a signal line adapter data bus structure is shown. As shown in FIG. 4, the second output control register 38 (FIG. 3) line 17 ₂ (OCREG20n)
is coupled directly to the input of autocaller output register 505, and also directly to transceiver bus controller chip 503, which provides bidirectional bus drive. The automatic calling device output register 505 is a 6-bit “D” type flip-flop register (DR).
6n). When the clock input is enabled, the data from the second output register 38 is
Strobed by ACUOR505. The data sent to both timer 507 and USART 508 of FIG. 4 originates from the second output register 38 in the state machine processor (FIG. 3) and is transmitted to transceiver bus controller 503.
and then to the addressed component. The data line to the timer component is high active and the data line to the USART component is low active. Since both components share the same data bus, data to one of the components must be inverted. Timer 507 is “inverted”
It is used to receive data, ie, 1=0 and 0=1, while the USART 508 receives the typical format. Thus, a "1" bit from the second output register 38 in the state machine processor (FIG. 3) appears as a "1" bit for the USART (active low) and as a "0" bit for the timer. Transceiver bus controller 500 is a three-stage device, but is not used in its third or high impedance state. It is the first output control register 3 in the state machine processor.
It is used to drive either DIN (data in) to DOUT (data out) or DOUT to ROUT depending on the state of the RE signal generated from bit 4 of 7. When bit 4 of register 37 is on, signal RE is positive and signals in the DOUT direction via transceiver bus controller 503 are on.
“Activate” DIN. Reading information from the line adapter (excluding RAM reading) is performed by a decoded GET operation, and the read information is transferred to the I/O bus 10.
is valid on at least the significant 8 bits of 8
-1 multiplexer 504 is the source of the read information. On a “single” line adapter (Figure 4),
Four of the eight inputs to multiplexer (MUX) 504 are used by line adapters;
The remainder is used by the data line interface (DLI). V-FLD(3:2) equals “11” and V-FLD(4:1) equals 0(DLI
GET) or the specified flip-flop (DESF) is on (LA GET), the multiplexer (MUX) during the GET operation.
is selected (low level). On the "quad" line adapter card (FIG. 2), there are 16 multiplexers, each with an 8-1 ratio. There are eight multiplexers for each "pair" of line adapters. 8 to MUX 504, as shown in FIG.
The input lines are split in half so that four lines are coupled to the DLI (Data Link Interface) and four lines are coupled to the line adapter. Similarly in FIG. 2, in a quad line adapter, the eight input lines of each group of eight multiplexers are split in half, thereby creating four groups, similar to a single line adapter. A “designated flip-flop” (DESF) in which any group of four input lines is in the on state
(Fig. 5)). The selection of any of the four lines in which group is done using the GET operation V-
This is done by at least two important bits of the FLD. In the line adapter (Figures 2 and 5)
The data to be “written” to RAM memory is
It is transmitted over I/O bus 10 in a 16-bit pulse parity format. in line adapter
The data “read” from RAM memory is 16
Placed on MEMOUT with bits + parity. Component address: As shown in Figure 4,
The output of the component to be “read” is the I/O
8-1 multiplexer 504 driving bus 10
input. There are five components on the line adapter that are "read" by the state machine processor. These five components on the line adapter are read: Component Request ID (CRID) USART 508 Timer 507 Automatic Calling Unit Status (ACUST) Adapter Type ID (ADPT.ID) These five components on the line adapter are read:
share the same input line (ROUT) to the multiplexer. The selection of one of the four inputs into either group (of inputs to the 8-1 multiplexer) is performed by at least two significant bits of the V-FLD of the GET operation. V
-FLD(3:4) is equal to IIXX and the selection of one of the four inputs is determined as shown in Table Y-1.

In FIG. 4, the single line adapter multiplexer 504 allows three components on the line adapter to be written (not including RAM). They are,
Automatic calling device output register 505 (ACUOR),
USART 508 and timer 507. Addressing these three components is done in two different formats. That is, the decoding of the V-FLD of the PUT operation and the first output control register 3 in the state machine processor (Fig. 3).
This is the decoding of bits from 7. One of the eight decoders _80P in Figure 8a is 01111
ACUOR 505 is addressed when strobe No. 2 is sent from the state machine processor. This decoding is performed only on a single line adapter card and is sent to other line adapter cards via the frontplane connector. This decoded signal is received by a three input NOR gate (N3, FIG. 8a) in each line adapter (the other inputs being a clock and a designated flip-flop). The output of this gate drives the clock input of the 6-bit ACU output register. Data from the second output control register 38 (Figure 3) is then strobed into the ACUOR 505 of Figure 8a. In FIG. 8a, the decoder _80P receives as inputs 0-4 from the decoder control device 23 of FIG.
and also receives the strobe #2 signal from state machine processor 600.
When register address RA=01111,
NOR gate N3 clocks data (from register 38 in FIG. 3) into ACU output register 505. FIG. 8b thereby shows the PUT strobe,
The register address and the ACUOR-CLK signal illustrate the timing sequence for loading the ACU-output register 505. Specification of the use of the ACU-output registers for their function of sending dialed numbers and control signals to the automatic calling device 505 _U is as follows: (a) The state machine 600 uses its second The output register register 38 is used. (b) State machine 600 uses PUT strobe 2 to load the dial number and control bits into second output control register 38 (FIG. 3).
Start a PUT operation. The fields used are calculation V-FLD D-FLD data PUT 01110 X001 XXnn nn is the data input to the second output control register 38.