JPH0224391B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a Hall element having a MOS structure (hereinafter referred to as a MOS type Hall element), and particularly to a method for providing a Hall output terminal thereof.

MOS Hall elements are easier to manufacture than bipolar Hall elements, can be integrated on the same substrate in the same process as the amplifier circuit, and have the advantage of being able to obtain high output voltages due to their thin channel thickness.

Conventionally, the arrangement of the Hall output terminals of this type of MOS type Hall element is known as shown in FIG. However, this arrangement can be replaced by a method in which the gate electrode pattern itself is used as a diffusion mask, such as in a so-called polysilicon gate process in which the gate electrode and the drain/source parts are self-aligned (hereinafter simply referred to as self-aligned gate process). During manufacturing, the hole terminal location from the source electrode is determined by the alignment of the field oxide pattern and the polysilicon mask. Therefore, misalignment of the Hall terminal positions occurs due to alignment errors between the respective masks, and as a result, there is a drawback that this appears as an offset voltage. FIGS. 1 and 2 are a plan view and a sectional view along AA' of a conventional MOS type Hall element. Semiconductor substrate 12
The region 1 delineated above is an active region of a MOS type Hall element, and its outer periphery is covered with a thick field oxide film 13 to separate it from other adjacent regions. Polysilicon film 2 forms a gate electrode. Impurities are diffused into portions 3, 4, 5, and 6 inside region 1 that do not overlap with polysilicon film 2, forming drain electrode 3, source electrode 4, and hole output terminals 5 and 6, respectively. 7,
8, 9, 10, and 11 are metal layers for wiring. 1
6 is a thin gate oxide film.

If such a conventional structure were to be manufactured using a so-called self-aligned gate process, the structure would not be covered with the thick field oxide film 13 when performing impurity diffusion or impurity implantation to form the source electrode 4 and drain electrode 3. Moreover, since the impurity is added to the regions 5 and 6 not covered by the gate electrode 2 at the same time, an impurity-doped region to be used as a hole output terminal can be formed.
This is very convenient from the viewpoint of process simplification. Metal interconnections 9 and 10 are taken out from the impurity doped regions 5 and 6 thus formed through so-called contact holes. When a bias voltage is applied to the gate electrode 2, an inversion layer 1 is formed on the surface of the semiconductor substrate directly under the gate electrode.
5 is formed, and when a magnetic field perpendicular to the plane including the inversion layer 15 is applied, a Hall electromotive force is generated between the Hall output terminal pair 5 and 6.

Now, the problem here is the alignment error of the polysilicon film 2 that occurs in the above process. In particular, there is a problem with misalignment that occurs when the mutual positions of the mask (not shown) required to form the polysilicon film 2 and the region 1 are shifted in a rotational relationship within the plane of the figure, and this occurs at this time. The difference between the distance measured from the source end 14 to the Hall output terminal 5 and the distance to the Hall output terminal 6 is critical. This difference in distance acts in the same way as a mismatch in the channel voltages applied to each location, resulting in the generation of an offset voltage.

This point will be explained in more detail as follows. That is, the channel voltage V _C of a MOS transistor operating in the triode region can be expressed by the following equation.

In equation (1), V _G is the gate voltage, V _D is the drain voltage,
L is the channel length, y is the Hall terminal position measured from the source end 14, and y/L is an index indicating the Hall output terminal position measured from the source end 14.

From equation (1), the offset voltage due to mismatching of the Hall terminal positions is becomes. Here, Δy indicates the magnitude of the positional deviation of the Hall terminal measured from the source end.

Figure 3 shows that V _D = V _G = 5V, V _T = 1.0V, Δy =
This figure shows the correlation between the channel length L and the offset voltage when it is 0.1 μm, using y/L as a parameter. As is clear from Fig. 3, the shorter the channel length L, the larger ΔV _C becomes; for example, L=W
=50μm, y/L=0.7, ΔV _C =7.3mV.

FIG. 4 shows the gate electrode 2 in the conventional example shown in FIG.
The figure shows a case where the rotation angle θ is shifted from the region 1 by the rotation angle θ. In the figure, metal wiring is omitted. Now, assuming that the channel width is W, the deviation Δy of the Hall terminal position is W·tanθ.

An object of the present invention is to provide a method for manufacturing a MOS Hall element in which the offset voltage caused by the alignment error described above is not generated even if the alignment error exists.

According to the present invention, in the method for manufacturing a MOS type Hall element, the gate electrode is formed in a constricted shape in the channel width direction so as to penetrate into the active region, and the impurity is diffused using the gate electrode as a mask. It is characterized by forming an impurity diffusion region that becomes a Hall output terminal in the constricted part.
A method for manufacturing a MOS Hall element is obtained.

FIG. 5 is a plan view of an embodiment shown for explaining the present invention. Symbols 21, 22, 2 in the diagram
3, 24, 25, 26, 27, 28, 29, 3
0, 31, 32, 33, 34 are the symbols 1, 2, 3, 4, and 3 shown in FIG. 1 and FIG. 2, respectively.
5, 6, 7, 8, 9, 10, 11, 12, 13,
It is basically equivalent to the one marked with 14. just,
The shapes of the active regions marked 1 and 21 are different from the shapes of the polysilicon films constituting the gate electrodes marked 2 and 22, and therefore the hole output terminals 5,
The apparent difference is that the concave and convex shapes that define 6, 25, and 26 are complementary. In other words, the point that the impurity doped region constituting the Hall output terminal is constructed from the portions of regions 1 and 21 that are not covered by the polysilicon films 2 and 22 and protrudes from the edges and is exposed is different from both. Although they are common, whether the protruding and exposed portion is formed by protruding a part of the end of region 1 or by recessing a part of the end of polysilicon film 22 is different between both methods. There is a difference. Therefore, if a cross-sectional view of the Hall output terminals 25 and 26 is drawn in FIG. 5, the Hall output terminal 2
The distance between 5 and 26 is shortened by a length corresponding to the difference between the protrusion and the recess, and the outline thereof is the same as that in FIG. 2. Naturally, the above-mentioned self-aligned gate process can also be applied to the manufacturing process as is.

The apparent difference between the conventional structure and the structure obtained by the manufacturing method of the present invention is as explained above, and at first glance, it may not seem like a big difference. However, the difference in effects brought about by these differences is so large that it depends on whether or not the MOS type Hall element will be put into practical use. That is, even if the mutual positions of the mask (not shown) required to form the polysilicon film 22 and the region 21 are shifted by the rotation angle θ in the plane of the figure, as shown in FIG. The distance y from the end 34 to the Hall output terminal 25 and the distance y from the Hall output terminal 26 are determined only by the shape and dimensions of the mask, and are completely independent of the rotation angle θ. However, the precision in terms of manufacturing technology for determining the shape and dimensions of the mask is much smaller than the alignment precision and can be virtually ignored, so in equation (2) above, Δy=0,
The offset voltage ΔV _C will also become zero.
Therefore, according to the present invention, even if the product is manufactured using inferior manufacturing technology that can only achieve poorer alignment accuracy, it is theoretically possible to eliminate the offset voltage, and from an economic point of view, it is The above effects will be outstanding.

There are very few restrictions to be imposed when implementing the invention. For example, in the embodiment shown in FIG. 5, a part of the end of the polysilicon film 22 is recessed into a rectangular shape to define the shape of the impurity doped region for the Hall output terminal, but the shape of the recess is not necessarily rectangular. The shape is not required. Furthermore, the shape of the end of region 1, which defines the impurity doped region for the Hall output terminal together with the recess provided at the end of the polysilicon film, is also defined by the end of the drain electrode 23 and the source electrode, as shown in FIG. There is no necessity to use a straight line connecting the end sides of 24. If it is more convenient to curve it appropriately,
There's nothing wrong with doing it that way. There is also no reason to limit the constituent material of the gate electrode to polysilicon. However, those that make the so-called self-aligned gate process difficult should be avoided. The thick field oxide film 33 also has a thin gate oxide film (fifth
Although it does not appear in the figure, it corresponds to Figure 2 16)
Although both are expressed as oxide films in accordance with common practice, these also do not need to be oxide films in the strict sense. Of course, it may be a deposited oxide, or it may be a nitride, as long as it has good insulating properties and does not present any difficulties in manufacturing technology.

[Brief explanation of drawings]

FIG. 1 is a plan view of a conventional MOS Hall element. FIG. 2 is a sectional view of section AA' in FIG. 1.
FIG. 3 is a diagram showing an example of the channel length dependence of offset voltage caused by mismatching of Hall terminal positions. FIG. 4 is a diagram when the mask forming the gate electrode is shifted by θ in the rotational direction with respect to the active region. FIG. 5 is a plan view of an embodiment of the present invention. FIG. 6 is a diagram in the embodiment shown in FIG. 5 when the mask forming the gate electrode is shifted by θ in the rotational direction with respect to the active region. 1, 21... Active region, 2, 22... Gate electrode, 3, 23... Drain electrode, 4, 24... Source electrode, 5, 6, 25, 26... Impurity doped region constituting the Hall output terminal. ,7,8,9,1
0, 11, 27, 28, 29, 30, 31... Wiring metal, 12, 32... Semiconductor substrate, 13, 33
... Thick field oxide film, 14, 34 ... Source end, 15 ... Inversion layer, 16 ... Thin gate oxide film.

Claims (1)

[Claims] 1. In a method for manufacturing a MOS Hall element, a gate electrode is formed in a constricted shape in the channel width direction so as to penetrate into the active region, and impurities are diffused using the gate electrode as a mask.
A method for manufacturing a MOS type Hall element, comprising forming an impurity diffusion region that becomes a Hall output terminal in the constricted portion.