JPH0225586B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to an electronic switching system using a distributed processing method, in which a failure occurs when a failure occurs in communication between a central processing unit and each processor that is controlled in a distributed manner. This relates to display methods.

(2) Background of the technology Generally, as a method of distributed control in electronic exchanges, a central processing unit that controls the exchange network is used.
A technology has been developed in which a line processor LPR is built into each subscriber circuit LC under the control of the CPR, and control information, data, etc. are exchanged between the line processor and the central processing unit via a network.

(3) Prior art and problems In this method, the conventional central processing unit CPR
Communication between the line processor LPR and the line processor is CPR or
When the LPR or CPR has finished receiving the data sent from the LPR, the buffer full signal on the line interface is turned off, and the CPR
Alternatively, the LPR detects that the corresponding LPR or CPR has completed receiving the transmitted data due to the disappearance of this buffer busy signal. However, when a failure occurs during communication, this failure indication is provided separately from the buffer busy signal.

Therefore, when transmission data is taken into the CPR or LPR, if the transfer buffer becomes empty even if there is data or abnormal data, the receiving device is notified that the reception is complete, and by checking the received data in the CPR or LPR, the abnormality is detected. Not only is the procedure complicated, but also requires a large number of interfaces between the processing devices.

(4) Object of the Invention An object of the present invention is to solve the above-mentioned problems and to provide a fault display method that allows communication faults between processing devices to be displayed using easy means.

(5) Structure of the Invention In order to achieve the above object, the present invention provides a first processing device CPR that controls a switching network of an electronic exchange using a distributed processing method, and a second processing device disposed in a distributed manner. In inter-processing device communication in which communication between LPRs is performed via the highway interface HWINF, a buffer register BR for accumulating transmission signals is provided between a first processing device CPR and a second processing device LPR; When a transmission signal is stored in the buffer register BR from the first processing unit CPR, the arrival of the transmission signal is detected and a busy signal is generated to receive error information from the parity check circuit of the second processing unit LPR. A buffer flip-flop BFF/F for turning on/off the busy signal is provided in the highway interface HWINF, and the first processing unit CPR is a buffer flip-flop
The feature is that the busy signal of the BF F/F is monitored, and if the busy signal continues for a certain period of time, it is detected that the second processing unit LPR is unable to normally receive the transmitted information.

(6) Examples of the invention The present invention will be explained in detail below with reference to Examples.

FIG. 1 is a system configuration diagram as an embodiment for explaining the fault display method of the present invention. In the figure, NW is a time division network, which includes communication path memory SPM, control memory CM, and memory for received data.
It consists of an RSM, a memory for sending data SSM, a data extractor D from the highway, a data inserter I, etc., and an SRD is a signal receiving and distributing device that sends control information, data, etc. from the central processing unit CPR to the network NW, a and b are the down highway and up highway, HWINF is the highway interface between the network NW and the subscriber circuit (or trunk circuit) LC, and SUB is the subscriber. The subscriber circuit LC includes, for example, a line processor LPR that controls circuits for eight subscribers in one package.
It is equipped with a memory (not shown), etc., and has functions such as monitoring subscriber calls and decoding dialed numbers, and sends and receives voice to subscriber SUB using digital-to-analog conversion circuit D/A and analog-to-digital conversion circuit A/ This is done via D. Also the central processing unit
Data exchange between the CPR and the line processor LPR is carried out via the buffer BR of the highway interface HWINF, and the diagram in particular shows an example of communication from CPR to LPR.
The same applies to LPR→CPR communication. BF
F/F is a buffer flip-flop, and PC is a parity check circuit.

Now, when I try to perform CPR→LPR communication, CPR
sends the necessary data via the SRD, and the sent data passes through the NW and downstream HWa to the BR in HWINF.
is stored in At this time, HWINF detects that data has been sent, turns on (sets) the BF F/F, and generates a buffer busy signal. The following
When the LPR learns that data has been transferred to itself, the LPR designated to fetch data from the RB issues a shift clock for data fetching to the RB and fetches the data.

In the conventional method, the buffer busy signal was turned off at this point regardless of whether or not there was data imported into the LPR, and the CPR was notified of completion of reception. Therefore, CPR could not determine from the buffer busy signal whether the communication it had just made was successful or not, and had to use other information to detect the failure. In this invention, when LPR imports data from BR, at the same time
Check whether there are any errors in the data on the PC, and if there are no errors in the output of this PC, BF F/
Turn off (reset) F and if there is an error,
Leave BF F/F on. The buffer busy signal is inserted into the uplink highway HWb,
Since the data is sent to the CPR, the CPR can tell whether there is a problem with the communication that just occurred by looking at the buffer busy signal after a certain period of time (the time until the buffer busy signal turns off (reset) during normal operation) after sending the data to the LPR. can be determined.

As described above, according to the present invention, a communication failure can be easily indicated by using a buffer full signal, thereby eliminating the need for a dedicated failure indication line. In the above explanation
PC means not only a parity check but also something that generally detects communication failures.

FIG. 2 shows a time chart of the buffer busy signal in the control of the fault indication method of the present invention.
In the figure, figure A shows normal reception and figure B shows the case of failure. First, when data is written to BR by sending data from CPR, BF F/F in figure 1 is set and a buffer busy signal is sent. be done.

The data in this BR is sequentially loaded into the LPR by the shift clock, and when the loading is completed, the data in the BR is transferred to the BF/F/
F is reset. During this capture operation, the LPR checks whether the data is received correctly.

If a data abnormality is detected during data acquisition
Since LPR does not reset BF F/F, CPR
Then, when it is detected (determined) that this buffer busy signal continues for a predetermined period of time or more, it is known that a failure has occurred.

(7) Effects of the Invention As explained above, according to the present invention, in communication between processing devices, it is possible for the sending device to know whether or not data reception is being performed normally or not using a simple method. In the hardware configuration, there is no need to provide a separate line for failure notification as in the past, so it is possible to achieve economical efficiency.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram as an example for explaining the fault display method of the present invention, and Fig. 2 is a time chart of the fault display.
B indicates an abnormal situation. HWINF: Highway Interface,
CPR: central processing unit, LPR: line processor,
BR: Buffer register, BF F/F: Buffer full flip-flop.

Claims (1)

[Scope of Claims] 1. Communication between a first processing device CPR that controls a switching network of an electronic exchange using a distributed processing method and a second processing device LPR distributed in a distributed manner is carried out via a highway interface HWINF. In inter-processing device communication performed by
When the transmission signal is stored in the buffer register BR from the first processing device CPR, the second processing device detects that the transmission signal is received and raises a busy signal.
The highway interface HWINF is provided with a buffer flip-flop BFF/F that turns on/off the busy signal based on error information from the parity check circuit of the first processing unit LPR. The busy signal of the flop BF F/F is monitored, and if the busy signal continues for a certain period of time, the second processing device
A failure notification method characterized by detecting that LPR is unable to normally receive transmitted information.