JPH0226316B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated memories, and more particularly to:
The present invention relates to a large capacity integrated memory having a gate transistor between a sense amplifier and a digit line.

Please note that the following explanations are all for n channel for convenience.
It is done with MOS transistor, but p channel
It goes without saying that the present invention can be applied to MOS transistors and any other types of transistors as they are essentially the same.

An example of a conventional integrated memory is shown in FIG. In a conventional integrated memory as shown in FIG. 1, when the address line selected by the Cell information of one of the memory cells is on digit line 1 or 2.
The reference potential generating circuit generates a potential between high and low levels on the other digit line. That is, when address line 3 is selected, for example, information in memory cell 5 is read out to digit line 1, and a reference potential is generated on digit line 2 by reference potential generation circuit 8.

Conversely, when the address line 4 is selected, the information in the memory cell 6 is read out onto the digit line 2, and a reference potential is generated on the digit line 1 by the reference potential generation circuit 7. As a result, digit lines 1 and 2 have the memory cell capacitance C _S and the digit line capacitance
A minute potential difference determined by the capacitance division of CB is generated, and the minute potential difference is amplified by activating the sense amplifier 9. Thereafter, the input/output transistor T1 selected by the Y decoder 11 is made conductive to output information on one digit line, and reading of the memory cell information is completed. In writing, information is written to the digit line and memory cell through the input/output transistor T1.

In a conventional one-transistor type integrated memory as shown in FIG. 1, a large number of memories are coupled to one digit line. However, in such a configuration, as the memory capacity increases, the number of memory cells coupled to the digit line increases, and as the parasitic capacitance _CB of the digit line increases, the division ratio ^CB _CS with respect to the memory cell storage capacity C _S also increases. Because of this, the signal potential difference appearing on the digit line pair during cell readout becomes very small, resulting in a disadvantage that malfunctions are likely to occur unless a highly sensitive sense amplifier is used.

It is an object of the present invention to provide an integrated memory that can increase the capacity without using a highly sensitive sense amplifier, and another object of the present invention is to provide an integrated memory that is extremely unlikely to malfunction. It is to be.

The integrated memory according to the present invention has a memory cell arranged at the intersection of an address line and a digit line, and a plurality of digit line pairs are provided for each sense amplifier, and a selected pair of digit lines is connected to the memory cell. It is characterized in that it is connected to two inputs of a sense amplifier, and that two digit lines run above each memory cell.

According to the integrated memory of the present invention, the selected one
By connecting only a paired digit line to its sense amplifier, the effective digit line parasitic capacitance C _B connected to the sense amplifier is reduced,
By reducing ^CB _CS , it is possible to increase the signal voltage transmitted from the memory cell to the digit line, thereby reducing sense amplifier malfunctions.

In the present invention, since two digit lines pass above each memory cell, the pitch of the digit lines can be reduced, making it suitable for higher density.
Furthermore, when using the integrated memory of the present invention and a sense amplifier with the same sensitivity as the conventional one,
This has the advantage that the area of the memory cell can be reduced, which is convenient for increasing the capacity of the memory.

Moreover, in the integrated memory of the present invention, by arranging the memory cell at only one of the plurality of intersections between each address line and each set of digit lines, the memory cell can be selected at the time of address line selection. Information can be prevented from being destroyed.

Hereinafter, the present invention will be described in detail using examples in order to better understand the present invention.

FIG. 2 shows an embodiment of the present invention. In an integrated memory including such a memory cell matrix, a sense amplifier, an 2
Gate transistors T21, T22, T at the input
23, T24, ..., one pair of digit lines 23, 24, and another pair of digit lines 2
It is combined with 5, 26, .... For example, the digit lines 23 and 25 are connected to one input node N21 of the sense amplifier, respectively, through a transistor T21 whose gate is connected to the clock signal line φ1 and a transistor T23 whose gate is connected to the gate lock signal line φ2. Ru. Similarly, digit lines 24 and 26 are respectively connected to the other input node N22 via transistors T22 and T24 whose gates are connected to clock signal lines .phi.1 and .phi.2, respectively. Also, nodes N21 and N2
2 are connected to reference potential generation circuits 35 and 36, respectively. The same number of memory cells are connected to each digit line. Information in the memory cell is transmitted to the outside by transistors T25 and T26.

In addition, in FIG. 2, the reference potential generation circuits 35 and 3
6 and data input/output transistors T25 and T
26 is connected to nodes N21 and N22,
This does not limit the invention in any way, and the digit lines 23 and 25 and 24 and 26 may be connected.

In that case, one reference potential generation circuit 35 and 36 and one transistor T25 and T26 are required for each pair of digit lines, which is twice as many as in the case of FIG.

Next, the operation of the circuit shown in FIG. 2 will be explained using the waveforms shown in FIG. 3 as follows. For example, when the address line 27 selected by the X decoder 38 goes high at time t1, the clock φ2 drops from a high level to a low level, but the clock φ1 remains at a high level. Therefore, digit line 2
3 and 24 are connected to the sense amplifier, and the information of the memory cell 31 is transmitted to the digit line 23, and further transmitted to the node N21 via the transistor T21.
It is transmitted to On the other hand, a potential intermediate between high and low binary levels is generated at the node N22 by the reference potential generation circuit 36. When the sense amplifier 37 is activated at time t2 when the potential difference between the nodes N21 and N22 reaches its maximum, the potential difference between the nodes N21 and N22 is amplified.
After the potential difference between the nodes N21 and N22 is amplified to the maximum, the digit line selected by the Y decoder 39 and the selection line 40 become high level at time t3.
At the same time that memory cell information is transmitted to the outside as complementary signals through transistors T25 and T26,
The original memory cell information is rewritten into the memory cell 31. When address line 29 is selected and goes high, clock signal φ1 falls from high level to low level, clock signal φ2 remains at high level, and digit line pair 25, 26 is connected to the sense amplifier. connected to. Therefore, the information in the memory cell 33 is transmitted to the digit line 25 and the node N21.
It is transmitted to On the other hand, an intermediate potential is generated at node N22 from the reference potential generation circuit 36, and nodes N21 and N
A slight potential difference is created between the memory cells 22 and 22, and this is amplified and transmitted to the outside, and at the same time information is rewritten into the memory cell. When address line 28 or 30 is selected, reference potential generation circuit 35 operates,
After a slight potential difference occurs between nodes N21 and N22, the same operation as described above is performed.

As is clear from Figure 2, address 29 is 1
Since it intersects both of the two sets of digit lines 23 and 25, it has two points of intersection, but the memory cell 33 is arranged at only one of the points of intersection. Address line 27 also intersects digit lines 23 and 25, but memory cell 31 is arranged only at one of the intersections. Similarly, address line 28 is connected to its digit line 2.
The memory cell 32 is located only at one of the intersections with 4 and 25.
A memory cell 34 is arranged only at one of the two intersections of the digit lines 24 and 26 where the address line 30 intersects. By arranging the memory cell at only one of the intersections between the address line and each set of digit lines, information in the memory cell is prevented from being destroyed.

If the digit line is aluminum wiring,
The present invention is particularly effective. FIG. 4 shows an example of a mask pattern (memory cell portion only) for an embodiment of the present invention in which the digit line is an aluminum wiring and the word line is a polycrystalline silicon wiring. In the figure, 41 is a polycrystalline silicon wiring;
2 is the aluminum wiring, 43 is the diffusion layer, 44
45 is a contact region, 46 is an address line region, 47 is a digit line region, and 48 is a MOS transistor region. As can be seen from the figure, if two aluminum wires, that is, two digit lines, pass through the memory cell, the pitch of the memory cell section will not increase even if the digit lines are divided, and the area of the memory matrix section will be smaller than that of the conventional method. remains unchanged. In this case, the parasitic capacitance of the digit line is dominated by the junction capacitance of the diffusion layer and the overlap capacitance of the transistor rather than the aluminum wiring, so when the digit line is divided into two as shown in Figure 4, it is not divided. In this case, the parasitic capacitance of the digit line is approximately halved. Therefore, assuming that the memory cell capacity C _S is the same as before, C _B /C _S will be reduced to 1/2, and the potential difference between nodes N21 and N22 in Fig. 2 will be approximately twice as large. , sense amplifier malfunctions are reduced.

Furthermore, when C _B /C _S is made equal to the conventional size, the number of memory cells can be reduced to about half, which is convenient for reducing the chip size or increasing the memory capacity.

The above explanation assumes only the case where a large number of digit line pairs are divided into two digit line pairs as one set, but when implementing the present invention to configure an even larger capacity memory, By dividing a larger number of digit line pairs into multiple sets of three or more pairs without increasing the number of sense amplifiers, and reducing the effective parasitic capacitance of the digit line, the digit line from the memory cell can be easily connected. In addition to obtaining the advantage of being able to increase the signal transmitted to the memory cell, if C _B /C _S is kept constant, the memory cell can also be made smaller.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram for explaining a conventional integrated memory, in which digit lines 1 and 2 are connected to
are address lines, 5 and 6 are memory cells, and 7 and 8 are
9 is a reference potential generation circuit, 9 is a sense amplifier,
10 represents an X decoder, and 11 represents a Y decoder. FIG. 2 is a circuit diagram for explaining a typical embodiment of the present invention, and FIG. 3 is a signal waveform diagram prepared for explaining its operation. In both figures, N21, N22 are the left and right nodes, T21,
T22, T23, T24, T25, T26 are transistors, 23, 24, 25, 26 are digit lines, 27, 28, 29, 30 are address lines, 31, 32, 33, 34 are memory cells, 3
5 and 36 are reference potential generation circuits, and 37 is a sense voltage generator.
38 is an X decoder, 39 is a Y decoder, 40 is an address line, and φ1 and φ2 are clock signals. Figure 4 shows an example of a mask pattern (memory cell part only) when the circuit in Figure 2 is integrated and realized, 41 is a polycrystalline silicon wiring, 42 is an aluminum wiring, and 43 is an aluminum wiring. 44 is a contact region, 45 is a storage capacitor region, 46 is an address line region, 47 is a digit line region, and 48 is a MOS transistor region.

Claims (1)

[Claims] 1. A memory in which a plurality of pairs of digit lines are provided for each of a plurality of sense amplifiers, and a selected pair of digit lines among the plurality of pairs of digit lines is connected to two inputs of each sense amplifier,
A memory cell is placed at only one of the intersections between multiple pairs of digit lines provided for each sense amplifier and each address line, and two digit lines are placed over each memory cell. An integrated memory characterized by: