JPH059876B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated memories, and more particularly to:
The present invention relates to a large capacity integrated memory having a gate transistor between a sense amplifier and a digit line.

For convenience of explanation, all of the following explanations will be made using n-channel MOS transistors, but it is of course that the present invention can be applied to p-channel MOS transistors or any other types of transistors as they are essentially the same. It is.

An example of a conventional integrated memory is shown in FIG. In a conventional integrated memory as shown in FIG. 1, when the address line selected by the Cell information of one of the memory cells is on digit line 1 or 2.
The reference potential generating circuit generates a potential between high and low levels on the other digit line. That is, when address line 3 is selected, for example, information in memory cell 5 is read out onto digit line 1, and a reference potential is generated on digit line 2 by reference potential generation circuit 8.

Conversely, when the address line 4 is selected, the information in the memory cell 6 is read out onto the digit line 2, and a reference potential is generated on the digit line 1 by the reference potential generation circuit 7. As a result, digit lines 1 and 2 have the memory cell capacitance C _S and the digit line capacitance
A minute potential difference determined by the capacitance division of CB is generated, and the minute potential difference is amplified by activating the sense amplifier 9. Thereafter, the input/output transistor T1 selected by the Y decoder 11 is made conductive to output information on one digit line, and reading of the memory cell information is completed. In writing, information is written to the digit line and memory cell through the input/output transistor T1.

In a conventional one-transistor type integrated memory as shown in FIG. 1, a large number of memories are coupled to one digit line. However, in such a configuration, as the capacity of the memory increases, the number of memory cells coupled to the digit line increases, and as the parasitic capacitance C _B of the digit line increases, the division between the memory cell storage capacity C _S and the storage capacity C _S of the memory cell increases. Since C _S also increases, the signal potential difference appearing on the digit line pair during cell readout becomes extremely small, resulting in a disadvantage that malfunctions are likely to occur unless a highly sensitive sense amplifier is used.

It is an object of the present invention to provide an integrated memory that can increase the capacity without using a highly sensitive sense amplifier, and another object of the present invention is to provide an integrated memory that is extremely unlikely to malfunction. It is to be.

The integrated memory according to the present invention has a memory cell arranged at the intersection of an address line and a digit line, a pair of digit lines are connected to two inputs of a sense amplifier, and one of the two inputs receives information of the memory cell. However, in a circuit where the reference potential is supplied to the other side,
The above-mentioned digit lines are divided into a plurality of groups each consisting of a plurality of pairs of digit lines, and a sense amplifier is provided for each group. A plurality of pairs of switch circuits are connected between the plurality of pairs of digit lines of each group and two inputs of the sense amplifier of the group, and the plurality of pairs of switch circuits and each of the sense amplifiers are connected to each other. A pair of reference potential generating circuits connected to the connection points with the two inputs of each sense amplifier are further provided, and only one pair of switch circuits among the plurality of pairs of switch circuits connected to the two inputs of each sense amplifier is made conductive. Therefore, the present invention is characterized in that a pair of digit lines connected to this switch circuit are connected to two inputs of the sense amplifier.

According to the integrated memory of the present invention, a large number of digit line pairs are divided into a plurality of groups so that one group has a plurality of digit line pairs, and one sense amplifier is provided for each group. 1 selected in
By connecting only a pair of digit lines to the sense amplifier of that pair, the effective parasitic capacitance C _B of the digit line connected to the sense amplifier is reduced.
By reducing C _B /C _S , the signal voltage transmitted from the memory cell to the digit line can be increased, and malfunctions of the sense amplifier can be reduced.

Further, when using the integrated memory of the present invention and a sense amplifier having the same sensitivity as the conventional one, there is an advantage that the area of the memory cell can be reduced, which is convenient for increasing the capacity of the memory.

Moreover, in the integrated memory of the present invention, regardless of the number of digit line pairs allocated to each sense amplifier, only one pair of reference voltage generation circuits need be provided for this pair, which is advantageous in terms of high density. be.

Hereinafter, the present invention will be described in detail using examples in order to better understand the present invention.

FIG. 2 shows an embodiment of the present invention. In an integrated memory including such a memory cell matrix, a sense amplifier, an 2
Gate transistors T21, T22, T at the input
23, T24, ..., one pair of digit lines 23, 24, and another pair of digit lines 2
It is combined with 5, 26, .... For example, the gates of the digit lines 23 and 25 are connected to the lock signal line φ.
Transistor T21 connected to gate lock signal line φ2 and transistor T21 connected to gate lock signal line φ2
23, each is connected to one input node N21 of the sense amplifier. Similarly, the gates of the digit lines 24 and 26 are connected to the clock signal line φ1.
and the transistor T connected to φ2, respectively.
22 and T24, respectively, to the other input nodes N
22. Further, reference potential generation circuits 35 and 36 are connected to nodes N21 and N22, respectively. The same number of memory cells are connected to each digit line. Information in the memory cell is transmitted to the outside by transistors T25 and T26.

In addition, in FIG. 2, the reference potential generation circuits 35 and 3
6 and data input/output transistors T25 and T
26 is connected to nodes N21 and N22. Therefore, the number of reference potential generation circuits can be reduced.

Next, the operation of the circuit shown in FIG. 2 will be explained using the waveforms shown in FIG. 3 as follows. For example, when address line 27 selected by X decoder 38 goes high at time t1, clock φ2 drops from high level to low level, but clock φ1 remains at high level. Therefore, digit line 2
3 and 24 are connected to a sense amplifier, and the information of the memory cell 31 is transmitted to the digit line 23.
Furthermore, it is transmitted to node N21 via transistor T21. On the other hand, the reference potential generation circuit 3 is connected to the node N22.
6, a potential intermediate between high and low binary levels is generated. When the sense amplifier 37 is activated at time t2 when the potential difference between nodes N21 and N22 reaches its maximum, the potential difference between nodes N21 and N22 is amplified. Node N
After the potential difference between 21 and N22 is amplified to the maximum, the digit line selected by the Y decoder 39 and the selection line 40 become high level at time t3, and the memory cell information is output to the outside as complementary signals through transistors T25 and T26. At the same time, the original memory cell information is rewritten into the memory cell 31. When address line 29 is selected and goes high, clock signal φ1 falls from high level to low level, clock signal φ2 remains at high level, and digit line pair 25, 26 is connected to the sense amplifier. Connected. Therefore, the information in memory cell 33 is transmitted to digit line 25 and node N21. On the other hand, the reference potential generation circuit 36 is connected to the node N22.
An intermediate potential is generated between the nodes N21 and N22, and a slight potential difference is created between the nodes N21 and N22.This is amplified and transmitted to the outside, and at the same time information is rewritten into the memory cell. When the address line 28 or 30 is selected, the reference potential generation circuit 35 is activated and the node N
After a slight potential difference is generated between 21 and N22, the same operation as described above is performed.

As is clear from Figure 2, address 29 is 1
Since it intersects both of the two sets of digit lines 23 and 25, it has two points of intersection, but the memory cell 33 is arranged at only one of the points of intersection. Address line 27 also intersects digit lines 23 and 25, but memory cell 31 is arranged only at one of the intersections. Similarly, address line 28 is connected to its digit line 2.
The memory cell 32 is located only at one of the intersections with 4 and 25.
A memory cell 34 is arranged only at one of the two intersections of the digit lines 24 and 26 where the address line 30 intersects. By arranging the memory cell at only one of the intersections between the address line and each set of digit lines, information in the memory cell is prevented from being destroyed.

If the digit line is aluminum wiring,
The present invention is particularly effective. FIG. 4 shows an example of a mask pattern (memory cell portion only) for an embodiment of the present invention in which the digit line is an aluminum wiring and the word line is a polycrystalline silicon wiring. In the figure, 41 is a polycrystalline silicon wiring;
2 is the aluminum wiring, 43 is the diffusion layer, 44
45 is a contact region, 46 is an address line region, 47 is a digit line region, and 48 is a MOS transistor region. As can be seen from the figure, if two aluminum wires run through a memory cell, the pitch of the memory cell section will not increase even if the digit lines are divided, and the area of the memory matrix section will remain the same as in the conventional system. In this case, the parasitic capacitance of the digit line is dominated by the junction capacitance of the diffusion layer and the overlap capacitance of the transistor rather than the aluminum wiring, so when the digit line is divided into two as shown in Figure 4, it is not divided. In this case, the parasitic capacitance of the digit line is approximately halved.
Therefore, assuming that the memory cell capacity C _S is the same as before, C _B /C _S will be reduced to 1/2, and the potential difference between nodes N21 and N22 in Fig. 2 will be approximately twice as large. , sense amplifier malfunctions are reduced.

Furthermore, when C _B /C _S is made equal to the conventional size, the number of memory cells can be reduced to about half, which is convenient for reducing the chip size or increasing the memory capacity.

The above explanation assumes only the case where a large number of digit line pairs are divided into two digit line pairs as one set, but when implementing the present invention to configure an even larger capacity memory, Connect more digit line pairs to 1 instead of 3 or more without increasing the number of sense amplifiers.
By dividing the digit lines into multiple sets and reducing the effective parasitic capacitance of the digit line, the signal transmitted from the memory cell to the digit line can be increased, and C _B /C _S can be reduced. If kept constant, we also have the advantage of being able to make the memory cells even smaller. Furthermore, as can be seen from Figure 2, the sense amplifier and the pair of reference potential generation circuits only need to be placed within the layout pitch of the two digit lines; The area for the reference potential generation circuit that was required when arranging the sense amplifier can now be placed in the empty area created when one sense amplifier is placed on two digit lines. There is an advantage that the area overhead of the reference potential generation circuit is substantially eliminated. This advantage becomes even more advantageous as the number of digit line pairs connected to one sense amplifier increases to three or more, and in effect, the area of the reference potential generation circuit can be reduced by connecting the sense amplifier to the layout pitch of multiple pairs of digit lines. This is because it can be used to fill the empty area created by arranging it in . According to the present invention, not only can the number of reference potential generation circuits (number of digit line pairs per sense amplifier - 1) be omitted, but also the area of the reference potential generation circuit directly connected to the sense amplifier can be reduced by the area of the sense amplifier. Since the reference potential generation circuit is included in the chip, it has the special effect that the area of the reference potential generation circuit does not contribute to an increase in chip size, which is very useful for practical use.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining a conventional integrated memory, in which digit lines 1 and 2 are connected to
are address lines, 5 and 6 are memory cells, and 7 and 8 are
9 is a reference potential generation circuit, 9 is a sense amplifier,
10 represents an X decoder, and 11 represents a Y decoder. FIG. 2 is a circuit diagram for explaining a typical embodiment of the present invention, and FIG. 3 is a signal waveform diagram prepared for explaining its operation. In both figures, N21, N22 are the left and right nodes, T21,
T22, T23, T24, T25, T26 are transistors, 23, 24, 25, 26 are digit lines, 27, 28, 29, 30 are address lines, 31, 32, 33, 34 are memory cells, 3
5 and 36 are reference potential generation circuits, and 37 is a sense voltage generator.
38 is an X decoder, 39 is a Y decoder, 40 is an address line, and φ1φ2 is a clock signal. Figure 4 shows an example of a mask pattern (memory cell part only) when the circuit in Figure 2 is integrated and realized, 41 is a polycrystalline silicon wiring, 42 is an aluminum wiring, and 43 is an aluminum wiring. 44 is a contact region;
45 is a storage capacity area, 46 is an address line area, 47 is a digit line area, and 48 is a digit line area.
The MOS transistor regions are shown respectively.

Claims (1)

[Claims] 1 It has a memory cell placed at the intersection of an address line and a digit line, and a pair of digit lines are connected to two inputs of a sense amplifier, and one of the two inputs has the information of the memory cell, and the other has a reference potential. In the supplied circuit, the digit lines are divided into a plurality of groups each consisting of a plurality of pairs of digit lines, a sense amplifier is provided for each group, and a plurality of intersections between each address line and the digit lines of each group are provided. arranging a memory cell at only one of the intersections, and connecting a plurality of pairs of switch circuits between the plurality of pairs of digit lines of each set and the two inputs of the sense amplifier of that set;
A pair of reference potential generation circuits are further provided connected to the connection points between the plurality of pairs of switch circuits and the two inputs of each of the sense amplifiers.
A pair of digit lines connected to the switch circuit are connected to two inputs of the sense amplifier by making only one pair of the switch circuits conductive among the plurality of pairs of switch circuits connected to the input. integrated memory.