JPH0226888B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The input signal of the PCM code is corrected by the companding law signal indicating the μ-law or A-law companding law, and the segment boundary value corresponding to the segment bit is corrected. It selects and outputs the step width signal corresponding to the step bit, adds the segment boundary value and the step width signal, and converts it to a linear code.The shared part allows expansion from PCM code to linear code using the companding rule. This can be realized with an economical configuration.

[Industrial application field]

The present invention is based on the companding law of μ-law or A-law.
This relates to a digital expansion circuit that expands a PCM code into a linear code.

In order to convert an audio signal into a digital signal and transmit it, a method is known in which the signal is converted into a PCM code using either the μ-law or the A-law companding law.
When such a PCM signal is further subjected to compression encoding or synthesis processing, it is necessary to convert it into a linear code. Various expansion circuits have been proposed for this purpose.

[Conventional technology]

In order to expand a PCM code using the companding rule into a linear code, a table lookup method using a read-only memory that reads out the digital signal of the linear code using the input signal of the PCM code as an address signal has been known. There is. This conventional method has a configuration using a read-only memory dedicated to μ-law or A-law.

In addition, the expansion circuit is configured by a gate circuit,
A configuration is also known in which a PCM code input signal is converted and outputted to a linear code digital signal by a conversion logic gate circuit. This expansion circuit also
A logic circuit dedicated to μ-law or A-law is configured.

[Problem that the invention seeks to solve]

There are two types of companding rules for compressing and encoding audio signals and transmitting them: μ-law and A-law. Both companding rules are
A total of 8 bits, including 1 sign bit, 3 segment bits, and 4 step bits.
It has a bit structure. 8 like this
Further compressing and encoding the bit PCM code
When converting to ADPCM code, converting directly from PCM code will result in a large error, so first
~ After converting to a 16-bit linear code, the difference will be found and encoded. Also 8 bits
When performing synthesis processing etc. on PCM code,
Once converted to a linear code, compositing processing etc. are performed, and then the code is converted to a PCM code.

Also, depending on the audio signal transmission system, a system based on the μ-law companding law and a system based on the A-law companding law may coexist. Even in such a transmission system, when performing synthesis processing or conversion to ADPCM, it is necessary to first convert to a linear code.

However, in the past, the decompression circuit was either dedicated to the μ-law or dedicated to the A-law, so the decompression circuit had to be configured according to the type of companding law, which had the disadvantage of increasing costs. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a decompression circuit that can accommodate both μ-law and A-law companding laws.

[Means for solving problems]

The digital decompression circuit of the present invention will be described with reference to FIG. 1. In accordance with the companding law signal indicating the companding law of the input signal, a predetermined bit of the input signal is inverted, that is, the μ-law input signal is Invert all bits,
The A-law input signal is converted into a segment boundary value signal by the first correction circuit 1 which inverts even bits, the segment bits of the signal corrected by this first correction circuit 1, and the companding law signal. A segment boundary value output circuit 2 that outputs a companding law signal is A-law, and when the segment bit corrected by the first correction circuit 1 means the lowest segment, it is replaced with the second segment. a step width output circuit that outputs a step width signal using the step bits of the signal corrected by the first correction circuit 1 and the segment bits corrected by the second correction circuit 3; 4, the segment boundary value signal according to the companding rule from the segment boundary value output circuit 2, and the step width signal according to the companding rule from the step width output circuit 4, and outputting a linear code. It is equipped with a circuit 5.

[Effect]

The first correction circuit 1 corrects the input signal by bit inversion according to the μ-law or A-law companding law, and the segment boundary value output circuit 2 corrects the input signal by bit inversion according to the companding law signal of the μ-law or A-law. outputting a segment boundary value signal, and performing correction by a second correction circuit 3 to replace it with a second segment when the companding law signal is A-law and the segment bit means the lowest segment; By adding the corrected segment bits to the step width output circuit 4, it is possible to correct the difference in step width signals in the lowest segment between the μ-law and the A-law. Then, by adding the segment boundary value signal according to the companding rule and the step width signal in an adder circuit 5 and outputting the result, it is possible to convert the signal into a digital signal of a linear code.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 10 is a latch circuit, 11 is a first correction circuit,
12 is a segment boundary value output circuit, 13 is a second correction circuit, 14 is a step width output circuit, 15 is an addition circuit, 16 is an identification circuit for identifying segments,
17 is a complement circuit. The input signal is an 8-bit companding PCM signal received via the transmission line.
This is a code digital signal, and as shown in Fig. 3, it consists of 1 sign bit S, 3 bits segment bit SEG, and 4 bits step bit STEP.
represents "1" as positive and "0" as negative.

In addition, both μ-law and A-law are divided into 8 segments, and the above-mentioned 3-bit segment bits are divided into 8 segments.
Segments are specified by SEG, and each segment is divided into 16 steps, and each segment is divided into 16 steps.
This is specified by the bit step STEP. Also, in the correspondence between the μ-law and the linear code, the linear code may be 0, but in the correspondence between the A-law and the linear code,
There are no cases where the linear code becomes 0.
Also, although the step width for each segment is different, only in the A-law, the step widths for the lowest segment and its upper segment are the same.

Figure 4 is an explanatory diagram of μ-law expansion, and Figure 5 is an explanatory diagram of A-law expansion.
It shows a bit segment boundary value signal and a 12-bit step width signal, and SEGA and STEPA are A-
The 13-bit segment boundary value signal and 12-bit step width signal of the rule are shown. Also, the x mark indicates a 4-bit step bit. As mentioned above, the step width signals STEDμ and STEPA are different in the lowest segment, and in the A-law, the lowest segment and its upper segment (second segment) are different as described above. Same value “0000 00××
XX00”.

The linear code shown in FIG. 3 is composed of a 1-bit sign bit S and a 13-bit two's complement number.

The 8-bit input signal is latched in the latch circuit 10, and the companding law signal LAW indicating the companding law, μ-law or A-law, is sent to the first correction circuit 11 and the segment boundary value output circuit 12. and the second correction circuit 13. Sign bit S is applied from latch circuit 10 to complement circuit 17. Also segment bit
SEG and step bit STEP are applied to the first correction circuit 11.

When transmitting a PCM code based on the companding rule, μ-
In the case of the A-law, the segment bit SEG and the step bit STEP are inverted and transmitted, and in the case of the A-law, even bits 0, 2, 4, and 6 are inverted and transmitted. Therefore, the first correction circuit 11 uses the companding law signal LAW to invert all 7 bits in the case of the μ-law, and invert the even numbered bits in the case of the A-law. This is to be corrected.

The 3-bit segment bit SEG of the corrected signal is applied to the identification circuit 16, the segment is identified, and the 8-bit segment identification information is sent to the segment boundary value output circuit 12 and the second correction circuit 13. added to. A companding signal HLAW is also added to the segment boundary value output circuit 12,
A 13-bit segment boundary value signal corresponding to μ-law or A-law is output. Therefore, the segment boundary value output circuit 12 can be constituted by a read-on memory that reads out the segment boundary value signal using the 8-bit segment identification information and the companding law signal LAW as address signals. Further, the companding law signal LAW is also applied to the second correction circuit 13, and when the companding law signal LAW indicates μ-law and the segment identification information means the lowest segment, the step width signal STEP μ is “0000”. However, when the companding law signal LAW indicates the A-law and the segment identification information means the lowest segment, the step width signal STEPA becomes "0000 00×
× ××00”, and its upper segment (second
segment). Therefore, when the companding law signal LAW is A-law and the segment identification information indicates the lowest segment, correction is performed to replace it with the second segment.

The step width output circuit 14 includes 4 step bits corrected by the first correction circuit 11,
The 8-bit segment identification information corrected by the second correction circuit 13 is added to produce a 12-bit step width signal corresponding to the companding rule shown in FIG. 4 or FIG.
SETPμ and STEPA are output. Therefore, the step width output circuit 14 uses the 4-bit step bits and the 8-bit segment identification information corrected by the second correction circuit 13 as address signals, and is constituted by a read-only memory that reads out the step width signal. can do.

In the case of the μ-law, as shown in FIG. 4, the segment boundary value signal SEGμ corresponding to the segment bit SEG and the step width signal STEPμ corresponding to the step bit STEP are applied to the adder circuit 15,
In the case of A-law, as shown in Figure 5, the segment boundary value signal corresponding to the segment bit SEG
SEGA and a step width signal STEPA corresponding to the step bit STEP are applied to an adder circuit 15, and the addition output signal is applied to a complement circuit 17.
This complement circuit 17 receives the sign bit S of the input signal.
is added, and when the sign bit S is "0", the output signal is a 14-bit linear code in two's complement representation, and when the sign bit S is "1", it is not a complement and is output as a linear code. The output signal is

Therefore, by the companding law signal LAW, both the 8-bit PCM signal according to the μ-law and the 8-bit PCM signal according to the A-law can be expanded into a 14-bit linear code signal.

FIG. 6 is a block diagram of another embodiment of the present invention, in which the same reference numerals as in FIG. 2 indicate the same parts, and 12
A and 12b are segment boundary value output circuits compatible with μ-law and A-law, and 12c is a selector. Three segment bits of the signal corrected by the first correction circuit 11 are applied to the identification circuit 16 to output segment identification information, and the 8-bit segment identification information is applied to the segment boundary value output circuit 12a, 12b and the second correction circuit 13, respectively. Therefore, from the segment boundary value output circuits 12a and 12b, μ-law and A
- A segment boundary value signal corresponding to the rule is output and applied to the selector 12c.

The companding law signal LAW is applied to the selector 12c, and in the case of μ-law, the μ-law segment boundary value signal is selectively output, and in the case of A-law, A
- The segment boundary value signal of the rule is selectively output,
It is added to the adder circuit 15. Since the step width output circuit 14 outputs a step width signal as in the previous embodiment, the adder circuit 15 adds the segment boundary value signal and the step width signal, and
The complement circuit 17 determines whether or not to complement the signal in accordance with the sign bit S, resulting in a 14-bit linear code output signal.

〔Effect of the invention〕

As explained above, the present invention utilizes μ-law and A-
For any companding law PCM code,
By performing correction and conversion using the companding law signal LAW, there is an advantage that it can be expanded into a linear code. Therefore, it is possible to make the PCM interface part more versatile.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the code, and Figs. 4 and 5 are expansions of μ-law and A-law. The explanatory drawing, FIG. 6, is a block diagram of another embodiment of the present invention. 1 and 11 are first correction circuits, 2 and 12 are segment boundary value output circuits, 3 and 13 are second correction circuits, 4 and 14 are step width output circuits, 5 and 15 are addition circuits, and LAW is a companding circuit. 10 is a latch circuit, 16 is an identification circuit, and 17 is a complement circuit.

Claims (1)

[Claims] 1. In a digital expansion circuit that expands a PCM code according to the companding rule into a linear code, a predetermined bit of the input signal is determined in accordance with a companding rule signal indicating the companding rule of the input signal. a segment boundary that outputs a segment boundary value signal based on the segment bits of the output signal of the first correction circuit 1 and a companding rule signal indicating the companding rule of the input signal; When the segment bit of the output signal of the value output circuit 2 and the first correction circuit 1 means the lowest segment, and the companding rule signal indicating the companding rule of the input signal is the A-law, a second correction circuit 3 that corrects segment bits by replacing them with second segments; and step bits of the output signal of the first correction circuit 1 and segment bits of the output signal of the second correction circuit 3. The step width output circuit 4 outputs a width signal, and the addition circuit 5 adds the respective output signals of the segment boundary value output circuit 2 and the step width output circuit 4 to output a linear code. Features a digital expansion circuit.