JPH0243376B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Utilizing the similarity between μ-law and A-law PCM codes, the PCM code format is converted into a type that is easy to correct for encoding, and after the correction, it is reversed to the original type. Convert.

[Industrial application field]

The present invention relates to, for example, a 32Kbps ADPCM system,
Especially in the coding correction circuit in tandem connection, μ
The present invention relates to an encoding correction circuit that can accommodate both the - law and the A- law.

Conventional encoding correction methods have the drawbacks of being time-consuming when processed using software, and large in circuit size when processed using hardware, and there has been a strong demand for improvement.

[Conventional technology]

FIG. 3a is a block diagram showing an example of an encoder in the conventional ADPCM system, and FIG. 3b is a block diagram showing an example of a decoder.

In the figure, 1 is an expansion circuit, 2 is a quantizer, 3 is an inverse quantizer, 4 is a predictor, 5 and 6 are arithmetic units, and 10
is an inverse quantizer, 11 and 14 are arithmetic units, 12 is a compression circuit, 13 is an expansion circuit, 15 is a quantizer, 1
6 is a coding correction circuit, and 17 is a predictor. The same symbols represent the same objects throughout all the figures below.

The operation of the encoder of FIG. 3a will be summarized.

The PCM code S becomes a linear code SL in the expansion circuit 1, and becomes an error signal D by calculating the difference from the predicted value SE in the arithmetic unit 5. The error signal D is quantized into an ADPCM code I in a quantizer 2 and output.

On the other hand, the ADPCM code I is inputted to the inverse quantizer 3 to become a reproduced error signal DQ, which is added to the predicted value SE in the arithmetic unit 6 to become a reproduced signal SR.

The reproduced error signal DQ and the reproduced signal SR are input to a predictor 4, which outputs a predicted value SE for the next sample.

The operation of the decoder of FIG. 3b will be summarized.

The ADPCM code I is converted into a reproduction error signal DQ by the inverse quantizer 10, and is input to the predictor 17.

On the other hand, the reproduced error signal DQ is added to the predicted value SE output from the predictor 17 by the arithmetic unit 11 to form the reproduced signal SR. The reproduced signal SR is converted into PCM code by the compression circuit 12.
It becomes SP and is input to the predictor 17, where it is used to calculate the predicted value SE for the next sample.

The processing up to this point in the decoder is processing without encoding correction, and the PCM code SP is the output of the decoder.

In this case, PCM code S → ADPCM code I →
It is known that a deviation of "±1" occurs between PCM code S and PCM code SP during the conversion process of PCM code SP, and as a result of this, PCM→
If the ADPCM→PCM connection is made in multiple stages, the transmission characteristics will deteriorate significantly.

Transcoding is performed to correct this.

This general method of transcoding is the third
It is shown in the right half of figure b.

That is, the PCM code SP undergoes the same processing as the encoder in the decompression circuit 13, the arithmetic unit 14, and the quantizer 15 to become the ADPCM code IX, which is converted into the ADPCM code I and the PCM code input to the decoder.
The code is input together with SP to the encoding correction circuit 16, and the PCM code SD corrected here is output.

FIG. 4 shows an algorithm for encoding correction.

By comparing the magnitude of IM and ID, which are the inverted sign bits of ADPCM code I and ADPCM code IX, it is possible to determine whether the PCM code SP‖ is on the positive side or the PCM code SP‖ is on the negative side. It is also determined whether the PCM code is the original PCM code SP, and it is corrected as shown in the correspondence diagram of the μ-law shown in FIG. 4a and the A-law shown in FIG. 4b.

[Problem that the invention seeks to solve]

However, in conventional hardware-based processing circuits, separate processing circuits are provided for each μ-law and A-law, which has the disadvantage of increasing the circuit scale of the encoding correction circuit.On the other hand, in the case of software-based processing, had the disadvantage that the processing time was very long.

An object of the present invention is to provide an encoding correction circuit with a small hardware scale by commonly processing μ-law and A-law.

[Means for solving problems]

The above problem is solved in the PCM code encoding correction circuit in the adaptive differential decoder of the adaptive differential PCM method. adaptive differential
A PCM code I, a PCM code SP obtained by adaptive differential decoding of the adaptive differential PCM code I, and a readaptive differential PCM obtained by adaptive differential encoding of the PCM code SP again.
A first complement circuit 23 receives code IX and inverts data bits other than the sign bit according to the format instruction signal LAW and the sign bit in the PCM code SP; a detection circuit 24 that detects "0" and all "1"; and the adaptive differential PCM code I and the re-adaptive differential PCM code IX.
a comparator circuit 28 for comparing the outputs of the comparator circuit 28 and the output of the detection circuit 24; and an adder circuit for adding either "1", "1" or "-1" to the output of the complement circuit 23 based on the output of the comparator circuit 28 and the output of the detection circuit 24. 2
5, the inversion of each data bit other than the sign bit in the output of the adder circuit 25 is controlled by the format instruction signal LAW, the sign bit, and the sign bit in the output of the adder circuit 25, and the sign is corrected. P.C.M.
This problem is solved by an encoding correction circuit characterized in that it is composed of a second complement circuit 29 that outputs the code SD.

[Effect]

According to the invention, the similarity of μ-law and A-law PCM codes is exploited.

That is, in Fig. 4, for example, +3 of the N ₀ term
is 11111101 in μ-law SP, while A
-The SP of the rule is 10000010. Therefore, if the 7 bits except the first sign bit 1 are replaced with 0 and 1, the μ-law becomes the A-law, and conversely, the A-law becomes μ
- becomes the rule. This similarity between μ-law and A-law PCM codes is utilized.

In other words, by converting the PCM code into a type that allows easy encoding correction and then converting it back to the original type after correction, the circuit scale can be significantly reduced and the versatility of the system can be increased. Benefits arise.

〔Example〕

FIG. 1 is a diagram showing an embodiment of an encoding correction circuit according to the present invention.

Figure 2 a is PCM code, Figure 2 b is ADPCM
The bit configuration of each code is shown below.

In the figure, 20, 21, 22 are latch circuits, 2
3 is a complement circuit, 24 is an all "0" and "1" detection circuit, 25 is an adder circuit, 26 and 27 are inverters, 28 is a comparator, and 29 is a complement circuit.

The details of the present invention will be explained below with reference to the drawings.

The PCM code SP is stored in the latch circuit 20,
ADPCM code I is stored in the latch circuit 22,
ADPCM code IX is stored in latch circuit 21.

The PCM code SP is in the complement circuit 23,
Based on the EOR output of the PCM code format designation signal LAW and the sign bit, it is determined whether or not to invert the 7 bits other than the sign bit. Furthermore, complement circuit 23
is composed of eight EOR gates from a to h,
The EOR gate in a is for the code, and the 7 gates from b to h are
The EOR gate is for signal bits.

That is, in the case of the μ-law, when LAW="0" and the sign bit s is "1", the 7 bits other than the sign bit s are inverted.

In the case of A-law, LAW="1" and sign bit s
When is "0", the 7 bits other than the sign bit s are inverted.

As a result, in both types of PCM codes, the most negative polarity code is "00000000" and the most positive polarity code is "11111111", and correction can be easily performed.

The output of the complement circuit 23 is all “0” and “1”
The signal is input to a detection circuit 24 and an addition circuit 25. As can be seen from the figure, the all "0" and "1" detection circuit 24 is an all "0" detection circuit 24a (OR circuit).
and all “1” detection circuit 24b (NAND circuit)
The respective outputs enter an adder circuit 25.

On the other hand, in the ADPCM code IX stored in the latch circuit 21, only its sign bit s is connected to the inverter 26.
The ADPCM code I, which is inverted to ID and stored in the latch circuit 22, has its sign bit s.
only is inverted by the inverter 27 and becomes IM.

Both the IM and ID enter the comparator 28, where their sizes are compared.

The adder circuit 25 includes an adder HA for sign bits, seven adders FA for signal bits, and an AND gate 2.
5a and 25b, and an OR gate 25c. In the adder circuit 25, "1", "0", and "-1" are detected from the outputs of the all "0" and "1" detection circuit 24 and the comparator 28. Complement circuit 2
Add to the output of 3.

In this case, adding “0” is When ID>IM detects all “0”, When all “1” is detected with ID<IM, and when ID=IM.

“1” is added when ID<IM and all “1”s are not detected.

"-1" is added when ID>IM and all "0"s are not detected.

The complement circuit 29 has eight EOR gates a to h,
It is composed of an ENOR gate 29x, an OR gate 29y, and an AND gate 29z. EOR gate a is for the sign bit, and seven EOR gates b to h are for the signal bit.

The complement circuit 29 divides the output of the adder circuit 25 into even bits and odd bits and decides whether to invert or not, based on the PCM code format designation signal LAW and the sign bit input/output of the adder circuit 25. This is because only in the case of the A-law, it is guaranteed that the even numbered bits of the PCM code SD shown in FIG. 4b will be inverted and output. That is, in the case of LAW="0" and the μ-law, if the sign bit s is "1", the 7 bits other than the sign bit s are inverted, but when LAW="1"
In the case of the A-law, if the sign bit s is "1", the even numbered bits are inverted, and if the sign bit s is "0", the odd numbered bits are inverted.

〔Effect of the invention〕

As explained in detail above, according to the present invention, μ-
The ability to perform common processing for both the A-law and A-law PCM codes has the effect of reducing the circuit scale and increasing the versatility of the system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of an encoding correction circuit according to the present invention. FIG. 2a shows the bit structure of the PCM code, and FIG. 2b shows the bit structure of the ADPCM code. FIG. 3a is a block diagram showing an example of an encoder in the conventional ADPCM system. FIG. 3b is a block diagram showing an example of a decoder in the conventional ADPCM system. FIG. 4 shows an algorithm for encoding correction. In the figure, 1 is an expansion circuit, 2 is a quantizer, 3 is an inverse quantizer, 4 is a predictor, 5 and 6 are arithmetic units, and 10
is an inverse quantizer, 11 and 14 are arithmetic units, 12 is a compression circuit, 13 is an expansion circuit, 15 is a quantizer, 1
6 is a coding correction circuit, 17 is a predictor, 20, 2
1 and 22 are latch circuits, 23 is a complement circuit, and 2
4 is an all "0" and "1" detection circuit, 25 is an adder circuit, 26 and 27 are inverters, 28 is a comparator, and 29 is a complement circuit.

Claims (1)

[Claims] 1. In a PCM code encoding correction circuit in an adaptive differential decoder using an adaptive differential PCM method, the encoding correction circuit includes a format instruction signal LAW indicating whether the PCM code is A-law or μ-law. and adaptive differential
A PCM code I, a PCM code SP obtained by adaptive differential decoding of the adaptive differential PCM code I, and a readaptive differential PCM obtained by adaptive differential encoding of the PCM code SP again.
A first complement circuit 23 receives code IX and inverts data bits other than the sign bit according to the format instruction signal LAW and the sign bit in the PCM code SP; a detection circuit 24 that detects "0" and all "1"; and the adaptive differential PCM code I and the re-adaptive differential PCM code IX.
a comparator circuit 28 for comparing the outputs of the comparator circuit 28 and the output of the detection circuit 24; and an adder circuit for adding either "1", "0", or "-1" to the output of the complement circuit 23 based on the output of the comparator circuit 28 and the output of the detection circuit 24. 2
5, the inversion of each data bit other than the sign bit in the output of the adder circuit 25 is controlled by the format instruction signal LAW, the sign bit, and the sign bit in the output of the adder circuit 25, and the sign is corrected. P.C.M.
An encoding correction circuit comprising a second complement circuit 29 that outputs a code SD.