JPH0226900B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a terminal device and a processing device that have any number of ports, for example, 30, 60, 120, or 240, and perform time-division synchronous communication using a baseband bus. The present invention relates to a transmitting device used in an intercommunication system.

(2) Background of the Technology The inventor of the present application has developed an interconnection system between a terminal and a processing device that is suitable for use in an environment consisting of many laboratories, such as a university.

The system is NTSC (National Television
System Committee) It is characterized by information transmission in a time division multiplexing system that allocates time slots using synchronization signals, and as shown in FIG.
, a coaxial cable 1 that connects these and supplies a baseband channel, a cable insertion device (inserter) 6 and a terminal device 7 disposed in this coaxial cable 1 to enable access to the coaxial cable 1, and a processing device. The tap device 4 has an interface with the inserter 8 and is connected to the inserter 6 by a data line 5.

In time slot allocation in the above system, frame synchronization is performed using a vertical synchronization signal generated every 16.67ms among the NTSC synchronization signals.
Slot synchronization is performed using horizontal synchronization signals generated every 63.4μs. Figure 2 is a partially cutaway waveform diagram of the frame synchronization pulse and slot synchronization pulse, and the slot S defined by the slot synchronization pulse Ps is
There are 262.5 slots defined in one frame defined by the frame synchronization pulse Pf, of which 240 slots are allocated for transmission and the remaining 22.5 slots are allocated for transmission preparation.

The transmission data in each slot S is, for example, a continuous 20-bit packet 1 as shown in FIG.
1, the first one is the start bit 12, the last one is the stop bit 13, and the middle two bits are 1.
4 is used as a control bit, and of the remaining two sets of 8 bits 15 and 16, 8 bits numbered 15 are used as data bytes, and 8 bits numbered 16 are used as data or address information bytes.

In the time slot allocation described above, if the number of tap devices is 30, for example, 8 (240÷30) slots can be allocated to each terminal in one frame. In other words, it is possible to obtain eight transmission opportunities per frame, and the frequency of the vertical synchronization signal is
Since it is 60Hz, there are 480 transmission opportunities per second, resulting in a transmission speed of 9600 bps (20 bits x 480/sec).
can be achieved. At this time, the 240 slots in one frame are divided into eight sets of 30 slots, and each slot in one set is sequentially assigned from the beginning according to the own address of the tap device. Therefore, in FIG. 2, for example, the data of the terminal connected to the tap device with the own address M is stored in the Mth slot from the beginning of the first set.
Sm1, the Mth slot of the next set Sm2, and so on, for a total of eight slots. Note that the interval between the slots Sm1, Sm2, . . . is equal to the number N of slots included in one set (30 in the above description).

In the above time slot allocation,
In addition to the above 30 terminals, it is possible to connect 60, 120 or 240 terminals within the range of transmission speeds up to 1200 bps.

(3) Purpose of the Invention The purpose of the present invention is to provide a transmitting device used in an interconnection system between a terminal and a processing device that allocates time slots using, for example, the above-mentioned NTSC synchronization signal and performs time-division synchronized communication. shall be.

(4) Structure of the Invention According to the present invention, the present invention provides a transmitting device used in an interconnection system between a terminal device and a processing device that performs time-division synchronized communication using an NTSC synchronizing signal, in which the total number N of tap devices is A self-address setting circuit that sets the number of terminals to be set, a self-address setting circuit that sets the self-address M of the tap device connected to the terminal or processing device, a flip-flop circuit that performs the initial setting of time division when the vertical synchronization signal VSYNC is generated, and a self-address setting circuit of the tap device that is connected to the terminal or processing device. A scanner that selects an address M, a subtraction counter that loads the own address M, and when a horizontal synchronization signal HSYNC is generated, adds this signal and subtracts 1 from the set own address M, converts the parallel information signal into serial information. A shift register that converts the serial information signal into a signal and outputs one bit every time the allocated output time is divided by the number of information bits, and checks whether the count number of the counter is the maximum number of slots. Consists of a comparator and a vertical synchronization signal
VSYN performs the above-mentioned initialization of time division and selection of the terminal's own address M, and then the horizontal synchronization signal HSYNC repeats the countdown of the number of own addresses, and outputs the serial information signal and selects the number of terminals at the timing of borrow occurrence. The number of terminals is counted down repeatedly by the subsequent horizontal synchronization signal, and the serial information signal is output and the number of terminals is selected at the timing of a borrow occurrence.Then, the number of terminals is selected and the serial information signal output is set every time a borrow occurs. This is achieved by a transmitter for time division synchronous communication characterized in that it is configured to perform time division synchronous communication on a frame-by-frame basis by repeating the transmission within the range of the maximum number of slots.

(5) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram of the main part of the transmitting device according to the present invention, in which block 21 is a self-grounding circuit for setting the self-address M of the tap device connected to the terminal or processing device, and block 22 is the self-grounding circuit for setting the self-address M of the tap device connected to the terminal or processing device. 23 is a scanner, 24 is a subtraction counter, 25 is a shift register for serial-to-parallel conversion of data, 2 is a terminal number setting circuit for setting the total number N;
6 is the shift register 2 for parallel data from the terminal.
5 is an output data set register that is inputted, 27 is a counter that counts the number of slots in one frame,
28 is a comparator 2 that checks whether the count number of the counter 27 is the maximum number of slots.
8 and 29 are maximum slot number setting circuits; 30 is a flip-flop circuit that stores 1-bit data;
D is input, CK is clock pulse, Q, Q are output,
R indicates a reset input.

In the device configured as described above, the vertical synchronization signal for frame synchronization is first included in the NTSC synchronization signal.
When VSYNC occurs, this signal is applied to the reset input R of the flip-flop circuit 30 to initialize the time division, and is also applied to the scanner 23 at the same time. The scanner 23 uses this signal to select the own address M of the transmitting tap device, and loads this into the subtraction counter 24. Note that the self address M of the tap device and the total number N of tap devices (for example,
30) is the self-address setting circuit 21 before the above initial setting.
and has already been set by the terminal number setting circuit 22.

Next, the horizontal synchronization signal for slot synchronization is
When HSYNC occurs, this signal is added to the subtraction counter 24 and the counter 27, and this signal causes the subtraction counter 24 to select the set self address M.
The counter 27 adds 1 to the count, and the comparator 28 checks whether the addition result is less than or equal to the set maximum number of slots, for example 240. Thereafter, each time a horizontal synchronization signal is generated, the above self-address M is subtracted, the count number is added, and the number of slots is checked. Then, parallel data is input from the output data set register 26 to the shift register 5, where it is converted into serial data to which a start bit and a stop bit of "1" are added, and then output.

Referring to FIG. 2, the timing at which a borrow occurs from the subtraction counter 24 is the slot pulse at the Mth (absolute address) equal to the own address.
This is when Ps occurs, and the above serial data is transmitted in slot Sm1 assigned to the terminal with the own address M defined by this slot pulse. For example, if the serial data is 20
In the case of a packet of bits, the time allocated by the slot (self-time) is divided into 20 equal parts, and one bit is output as a serial signal starting from the start bit every 1/20th of an hour. In the figure, the next slot Sm2 assigned to the terminal with the own address M is defined by the slot pulse N places ahead (relative address).

On the other hand, due to the occurrence of the borrow, the scanner 23 selects the set total number N of tap devices and loads it into the subtraction counter 24. The total number N is counted down every time a horizontal synchronizing signal is generated, and when a borrow occurs, the serial data is outputted, the total number N of tap devices is loaded into the subtraction counter 24 again by the scanner 23, and the same process is repeated. In this way, the slots Sm1, which are assigned in each set of N slots in one frame,
A serial information signal is transmitted in Sm2...

Note that when the count number of the counter 27 exceeds the set maximum number of slots, the signal from the comparator 28 is added to the clock pulse CK of the flip-flop circuit 30, and the signals from the outputs Q and Q cause the subtraction counter 24 and the counter The contents of 27 are cleared, and slots exceeding the set maximum number of slots are ignored. Then, the next vertical synchronization signal causes the initial setting and the selection of the own address M to be performed again, and the above-mentioned data transmission is performed.

By the way, in the above-mentioned transmitting device, the set value N of the total number of tap devices is set to 60, 120, etc. other than 30, for example.
Or by setting 240, slot assignment will be done automatically, and the serial data to be output will be 20.
This is not limited to bit packets.

(6) Effects of the invention As explained in detail above, according to the present invention,
It is possible to easily configure information transmission using a time division multiplexing method that allocates time slots using NTSC synchronization signals, and to configure an interconnection system between terminals and processing equipment using the above information transmission method. It is highly effective in providing work systems.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of an interconnection system between a terminal and a processing device according to the present invention, Fig. 2 is a waveform diagram of a frame synchronization signal and a slot synchronization signal, Fig. 3 is a diagram of the bit configuration of a packet, and Fig. 4 1 is a block diagram of a transmitter according to the present invention; FIG. 1... Coaxial cable, 2... Synchronous generator, 3...
...Terminator, 4...Tap device, 5...Data line, 6...Inserter, 7...Terminal, 8
...Processing device, 11...Packet, 12...Start bit, 13...Stop bit, 14...
Control bit, 15...Data byte, 16...Data or address information byte, 21...Self address setting circuit, 22...Number of terminal setting circuit, 23...
... Scanner, 24 ... Subtraction counter, 25 ... Shift register, 26 ... Output data set register, 27 ... Counter, 28 ... Comparator, 29 ...
...Maximum slot setting circuit, 30...Flip-flop circuit.

Claims (1)

[Scope of Claims] 1. A terminal number setting circuit for setting the total number N of tap devices 4, which is a transmitting device used in a mutual communication system between a terminal device 7 and a processing device 8 that perform time-division synchronized communication using an NTSC synchronization signal. 22. Self-address setting circuit 2 for setting the self-address M of the tap device 4 connected to the terminal 7 or the processing device 8
1. Flip-flop circuit 30 that performs time division initialization when the vertical synchronization signal VSYNC is generated; Scanner 2 that selects the own address M of tap device 4;
3. Load the self-address M and send the horizontal synchronization signal
When HSYNC occurs, the signal is added to a subtraction counter 2 that subtracts 1 from the set own address M.
4. A shift register 25 that converts the parallel information signal into a serial information signal and outputs the serial information signal one bit at a time every time the allocated output time is divided by the number of information bits, and a counter 27 whose count number is maximum. It consists of a comparator 28 that checks whether or not it is the number of slots.It initializes the time division and selects the own address M of the terminal 7 using the vertical synchronizing signal VSYNC, and then selects the own address M using the horizontal synchronizing signal HSYNC. The countdown is repeated, and the serial information signal is output and the number of terminals is selected at the timing of borrow occurrence.The countdown of the number of terminals is repeated by the subsequent horizontal synchronization signal, and the serial information signal is output and the number of terminals is selected at the timing of borrow occurrence. The present invention is characterized in that the time-division synchronized communication is performed in frame units by repeatedly selecting the number of terminals and outputting the serial information signal within the set maximum number of slots every time a borrow occurs. Transmitting device in split synchronous communication. 2. The serial information to be output has a 20-bit packet structure consisting of a 1-bit start bit, 8-bit data byte, 2-bit control bits, 8-bit data or address information, and 1-bit stop bit. A transmitting device in time division synchronous communication according to claim 1. 3. A transmitting device for time division synchronous communication according to claim 1 or 2, characterized in that the number of terminals to be set is 30, 60, 120, or 240.