JPH0326576B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a terminal device and a processing device that have any number of ports, for example, 30, 60, 120, or 240, and perform time-division synchronous communication using a baseband bus. The present invention relates to a receiving device used in an intercommunication system.

(2) Background of the Technology The inventor of the present application has developed an interconnection system between a terminal and a processing device that is suitable for use in an environment consisting of many laboratories, such as a university.

The system is NTSC (National Television
System Committee) It is characterized by information transmission in a time division multiplexing system that allocates time slots using synchronization signals, and as shown in FIG.
, a coaxial cable 1 that connects these and supplies a baseband channel, a cable insertion device (inserter) 6 that is disposed in this coaxial cable 1 and allows access to the coaxial cable 1, a terminal device 7, or a processing device. The tap device 4 is connected to the inserter 6 by a data line 5.

In time slot allocation in the above system, frame synchronization is performed using a vertical synchronization signal generated every 16.67 ms among the NTSC synchronization signals.
Slot synchronization is performed using horizontal synchronization signals generated every 63.4μs. Figure 2 is a partially cutaway waveform diagram of the frame synchronization pulse and slot synchronization pulse, and the slot S defined by the slot synchronization pulse Ps is
There are 262.5 slots defined in one frame defined by the frame synchronization pulse Pf, of which 240 slots are allocated for transmission and the remaining 22.5 slots are allocated for transmission preparation.

The transmission data in each slot S is, for example, a continuous 20-bit packet 1 as shown in FIG.
1, the first one is the start bit 12, the last one is the stop bit 13, and the middle two bits are 1.
4 is used as a control bit, and of the remaining two sets of 8 bits 15 and 16, 8 bits numbered 15 are used as data bytes, and 8 bits numbered 16 are used as data or address information bytes.

In the time slot allocation described above, if the number of tap devices is 30, for example, 8 (240÷30) slots can be allocated to each terminal in one frame. In other words, 8 transmission opportunities can be obtained per frame, and since the frequency of the vertical synchronization signal is 60Hz, a final transmission opportunity of 480 times per hour can be obtained, and the transmission speed is 9600 (20 bits x 480/sec).
bps can be achieved. At this time, the 240 slots in one frame are divided into eight sets of 30 slots, and each slot in one set is sequentially assigned from the beginning according to the own address of the tap device. Therefore, in Fig. 2, for example, the data of the terminal connected to the tap device with the own address M is the Mth slot from the head of the first set.
Sm1, the Mth slot of the next set Sm2, and so on, for a total of eight slots. Note that the interval between each slot Sm1, Sm2, . . . is equal to the number N of slots included in one set (30 in the above explanation).

In the above time slot allocation,
In addition to the above 30, it is possible to connect 60, 120 or 240 terminals within the range of transmission speeds up to 120 bps.

A transmitting device for transmitting packet information in accordance with the time slot allocation described above was developed by the inventor of the present application, and is characterized by the configuration shown in FIG. That is, it includes a terminal number setting circuit 22, a terminal self-address setting circuit 21, a scanner 23 for initial setting of time division, selection of the terminal's own address M or the number of terminals N related to reception, and subtraction. A subtraction counter 24 converts the parallel information signal into a serial information signal, and converts the parallel information signal into a serial information signal, and converts the parallel information signal into a serial information signal by 1 every time the allocated output time is divided by the number of information bits.
Output data set register 2 that outputs bit by bit
6 and a shift register 25, and a maximum slot number determination circuit consisting of a counter 27, a comparator 28, and a maximum slot number setting circuit 29, and uses the vertical synchronization signal VSYNC to initialize the time division and to set the terminal's own address M. The countdown is repeated, and the serial information signal is output and the number of terminals N is selected at the timing of a borrow occurrence.The countdown of the number of terminals N is then repeated by the horizontal synchronization signal HSYNC, and the serial information signal is output and the terminal is selected at the timing of a borrow occurrence. This is a transmitting device that performs time-division synchronized communication in frame units by selecting the number N of terminals and repeating the selection of the number N of terminals and outputting serial information signals within the range of the set maximum number of slots every time a borrow occurs. . In the same figure, the reference numeral 30 indicates a flip-flop circuit,
VSYNC and HSYNC are synchronous generator 2 in Figure 1.
The output from the shift register 25 in FIG. 4 is output to the coaxial cable 1 in FIG. 1.

(3) Purpose of the Invention The present invention provides a receiving device used in an interconnection system between a terminal device 7 and a processing device 8 that allocates time slots using, for example, the above-mentioned NTSC synchronization signal and performs time-division synchronized communication. With the goal.

(4) Structure of the Invention According to the present invention, this object uses an NTSC synchronization signal and a vertical synchronization signal (VSYNC) of the signal.
A transmitting device comprising a circuit including a scanner for initial setting operation of time division used for time division synchronization communication in which frame synchronization is performed by a horizontal synchronization signal (HSYNC) and slot synchronization is performed by a horizontal synchronization signal (HSYNC), and a maximum slot number determination circuit. A combined device includes a circuit including a counter, a shift clock, and a shift register that captures serial packet information one bit at a time when the slot time width is divided by the number of packet bits and converts it into parallel information, and a circuit that includes a counter, a shift clock, and a shift register, and It is equipped with a circuit that includes a comparator that determines the self-address based on address information, and a circuit that includes a subtraction counter that selects and subtracts the number of terminals. Then, every time a horizontal synchronization signal (HSYNC) is generated, a comparator is used to capture serial packet information, convert it to parallel information, and determine the self address, and when the self address matches, the captured information is processed and the number of terminals is selected. The number of terminals is counted down using a subtraction counter every time a horizontal synchronization signal is generated. After processing the acquired information and selecting the number of terminals using a scanner at the timing of a borrow, the horizontal synchronization signal is counted down again using a register. The number of terminals is counted down using the synchronization signal (HSYNC), and the frame is created by repeatedly processing the information taken in when a borrow occurs, selecting the number of terminals, and counting down the number of terminals within the maximum number of slots set below. This is achieved by providing a receiving device for time-division synchronous communication characterized by having a configuration for performing time-division synchronous communication in units. A 20-bit packet structure consisting of 1 bit data byte, 2 control bits, 8 bits of data or address information, and 1 stop bit, and the number of established terminals is either 30, 60, 120, or 240. This is achieved by

(5) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a schematic block diagram of the main part of the receiving device according to the present invention, in which block 31 is a flip-flop circuit, D is an input, CP is a clock pulse, and Q is a flip-flop circuit.
is the output, R is the reset input, and block 32
33 is a register that takes in the contents of the counter 32, 34 is a scanner, 35 is a subtraction counter, and 36 is a counter that counts the number of slots in one frame. A matching circuit that determines whether the number of slots is equal to the number of slots set by the maximum slot number setting circuit, 38 a counter that counts the time interval obtained by equally dividing the slot width by the number of bits composing a packet, 39 a shift clock, and 40 data A shift register 42 performs serial-to-parallel conversion of data, and 42 represents a comparator that checks address data in the captured data.

The receiving method in the apparatus having the above-mentioned configuration will be explained using the 20-bit packet information shown in FIG. 3 as an example.

First, when a vertical synchronization signal VSYNC for frame synchronization is generated among the NTSC synchronization signals, this signal is applied to the reset input of the flip-flop circuit 31, initial settings such as clearing the counter 32 are performed, and the following first horizontal synchronization signal HSYNC updates the contents of the counter 32 by one and clears the contents of the counter 38. and the next
Until HSYNC occurs, the counter 38 counts the time interval in which the slot width is divided into 20 by the clock pulses issued by the clock generator in the tap device 4 of FIG. A shift clock pulse is generated,
According to this pulse, the shift register 25 in FIG.
The serial packet information output from Ps in Figure 3
When detected, each bit is taken into the shift register 40 and the parallel data is converted.
HSYNC and VSYNC are separated in the tap device 4 of FIG. 1 and used as described above.

The converted data is taken into the 18-bit register 41 as 18-bit data excluding the first start bit and the last stop bit. At this time, the last bit is given the role of a communication flag; for example, when this flag is 1, it is communication information, and when it is 0, it is not. This communication flag is used by the micro CPU in the tap device 4 in Figure 1.
It becomes input. and control bit 14 shown in FIG.
When indicates that the 8-bit contents indicated by reference numeral 16 are the address of the connected station (for example, when control bit 14 is 01), the comparator 42 operates to compare the receiving device's own address and the above 8-bit contents. are compared, and if they match, the contents of the counter 32 (calling side address) are taken into the register 33 by a match signal, and at the same time, the number N of terminals is sent to the scanner 34.
is selected and loaded into the subtraction counter 35. Note that if the addresses do not match, the above calling party address and number of terminals N will not be loaded, and the next
The contents of the counter 32 are incremented by one by HSYNC, and data fetching, conversion, and address checking are performed again.

When the number N of terminals is loaded into the subtraction counter 35, 1 is subtracted from the number N of terminals each time HSYNC occurs, and at the timing when a borrow occurs, the received data is received as its own data and the scanner 34 The number N of terminals is selected and loaded into the subtraction counter 35. and again
It counts down each time an HSYNC occurs, and processes the data captured at the timing of a borrow as information sent to its own terminal device. Thereafter, loading of the number of terminals N, countdown, data processing when a borrow occurs, and reloading of the number of terminals N are repeated within the range of the set maximum number of slots to receive information. Note that slots exceeding the set number of slots are ignored by the matching circuit 36.
The selection of the above-mentioned initial setting information is repeated by the occurrence of the next VSYNC. Also, the number of terminals N
and the self-address are respectively set by the setting circuit (switch) in the tap device 4 shown in FIG.
The borrow signal output from the subtraction counter 35 of FIG. 5 is input to the micro CPU in the tap device 4 of FIG.

With the receiving device and its operation explained above, it is possible to select and process only the information sent to the number of own terminals among the received information assigned to each slot S shown in FIG. Even if the value changes, this can be handled by simply changing the set value N accordingly. For example, for 20-bit packet information, the communication speed
The number of terminals is 30, 60, within the range of 9600bps to 1200bps.
Can be 120 or 240.

Also, in the above explanation, the information is a 20-bit packet, but the information is not limited to this, and in that case, the shift clock pulse interval,
The capacity of the register 41 is appropriately selected.

(6) Effects of the invention As explained in detail above, according to the present invention,
It is possible to easily configure information transmission using a time division multiplexing method that allocates time slots using NTSC synchronization signals, and to configure an interconnection system between terminals and processing equipment using the above information transmission method. It is highly effective in providing work systems.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of an interconnection system between a terminal and a processing device according to the present invention, Fig. 2 is a waveform diagram of a frame synchronization signal and a slot synchronization signal, Fig. 3 is a diagram of the bit configuration of a packet, and Fig. 4 5 is a block diagram of a transmitting device, and FIG. 5 is a block diagram of a receiving device of the present invention. 1... Coaxial cable 1, 2... Synchronous generator, 3
... Terminator, 4 ... Tap device, 5 ... Data line, 6 ... Inserter, 7 ... Terminal,
8...Processing device, 11...Packet, 12...Start bit, 13...Stop bit, 14...
...Control bit, 15...Data byte, 16...
Data or address information byte, 21... Self-address setting circuit, 22... Terminal setting circuit, 2
3, 34... Scanner, 24, 35... Subtraction counter, 25, 40... Shift register, 26... Output data set register, 27, 32, 38...
Counter, 28, 42... Comparator, 29, 37...
... Maximum slot setting circuit, 30, 31... Flip-flop circuit, 36... Matching circuit, 39... Shift clock.

Claims (1)

[Claims] 1. Initial setting of time division used in time division synchronous communication using an NTSC synchronization signal, performing frame synchronization with the vertical synchronization signal (VSYNC) of the signal, and performing slot synchronization with the horizontal synchronization signal (HSYNC). A device combined with a transmitting device comprising a circuit including a scanner 23 for operation and a maximum slot number determining circuit 29, which transmits serial packet information one time per time when the time width of the slot is divided by the number of packet bits. A circuit that includes a counter 38, a shift clock 39, and a shift register 40 that capture bits bit by bit and convert them into parallel information; a circuit that includes a comparator 42 that determines a self-address with respect to address information in the captured information; and a circuit that selects a terminal number and performs subtraction. subtraction counter 35
It is equipped with a circuit including a flip-flop circuit 31 and a counter 32, and the initial setting of time division is performed by a vertical synchronization signal (VSYNC).
Then, every time a horizontal periodic signal (HSYNC) occurs, the comparator 42 captures serial packet information, converts it to parallel information, and determines its own address, and in the case of a match of its own address, processes the captured information and The number of terminals is selected using the register 33, and then the number of terminals is counted down using the subtraction counter 35 every time a horizontal synchronization signal is generated, and at the timing of a borrow, the acquired information is processed and the number of terminals is counted using the scanner 34. After making a selection, the number of terminals is counted down again using the horizontal synchronization signal (HSYNC), and within the maximum number of slots set below, processing of the information to be taken in when a borrow occurs, selection of the number of terminals, and number of terminals are performed. 1. A receiving device for time-division synchronous communication, characterized in that it is configured to perform time-division synchronous communication on a frame-by-frame basis by repeatedly performing a countdown. 2. A patent characterized in that serial packet information has a 20-bit packet structure consisting of a 1-bit start bit, 8-bit data byte, 2-bit control bits, 8-bit data or address information, and 1-bit stop bit. A receiving device for time division synchronous communication according to claim 1. 3. A receiving device for time division synchronous communication according to claim 1 or 2, characterized in that the number of terminals to be set is 30, 60, 120, or 240.