JPH0226920B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a buffer memory used in a method for packetizing and transmitting data from a plurality of terminal devices.

Packet transmission is a method of dividing information into appropriate units and transmitting the packets.The information divided into appropriate units is added with the addresses of the receiving side and the sending side, control commands, etc., and a single packet is formed. .

In this packet transmission, the buffer memory forms packets on the transmitting side and temporarily stores the packets until an empty time slot is found, and on the receiving side suppresses time jitter in received data.

Conventionally, a plurality of terminal devices have been provided with independent buffer memories, and the buffer memories have been controlled by a plurality of address counters corresponding to the respective buffer memories. FIG. 1 is a conceptual diagram of a conventional buffer memory control system. In this figure, 1 is a transmission path, 2 is a packet insertion circuit, 3 is a packet extraction circuit, 4-1 to 4-N are buffer memories, 5-1 to 5-N, 8-1 to 8-N are write address counters, 6-1~6-N, 7-1~7-
N is a read address counter, 9-1 to 9-N,
10-1 to 10-N are terminal devices, and 11 and 12 are selection circuits.

As shown in this figure, conventionally, each terminal device has an independent buffer memory 4-1 to 4-N and an address counter, and on the transmitting side, a selection circuit 11 switches between the buffer memories 4-1 to 4-N to transmit a packet. On the receiving side, the selection circuit 12 transfers the packets to the buffer memories 4-1 to 4-1 corresponding to each terminal device.
4-Distribute to N. In this way, in the past, independent buffer memories 4-1 to 4-N were provided for each terminal device, which required multiple address counters, resulting in a large circuit scale, and also required a small capacity memory for each terminal device. Therefore, the disadvantage is that the cost is high.

The present invention eliminates the above-mentioned drawbacks, allows multiple terminal devices to share one buffer memory and one set of address counters, reduces the scale of the buffer memory control circuit, and facilitates address specification from the address counter. It is intended to be.

In the present invention, in a control method for a buffer memory used in packet transmission in which data from a plurality of terminal devices is converted into packets and transmitted, one buffer memory is provided for each of the plurality of terminal devices, and a writing,
A set of address counters for specifying the read address is provided, and areas of the buffer memory are allocated equally to each terminal device, and the upper bits of the address specify the area divided for each terminal device, and the lower bits are used to allocate the data. Specify the packet area to store the packet and the data storage area within the packet area, and store the data every time the address counter indicating the data writing and reading position for each terminal counts up due to data writing and reading. The contents of the circuit are rewritten to the counted up value, and when the designation of the area divided by terminal device changes, the contents of the area of the memory circuit corresponding to the area is set to the address count, and counting is started from that value. The feature is that the address can be specified by uploading the address.

The present invention will be explained in detail below using the figures. FIG. 2 shows an embodiment of the present invention. In this figure, 1
3 is a buffer memory, 14 is a memory circuit, 15,1
6 is an address counter, 17 is a first-in first-out memory circuit (hereinafter referred to as FIFO)
18 and 19 are selection circuits, 20 is a packet insertion control circuit, 21 is a packet extraction control circuit, 22, 23
is a terminal address generation circuit, 24 and 25 are terminal selection circuits, WA is a write address, and RA is a read address. Note that in this figure, the same numbers as in FIG. 1 indicate the same parts.

Here, for the following explanation, the configurations of the buffer memory 13 and storage circuit 14 shown in FIG. 2 will be explained. FIG. 3a shows the structure of the buffer memory 13, and b shows the structure of the storage circuit 14. In this embodiment, it is assumed that one packet is formed from l pieces of data. Furthermore, one data consists of a specified number of bits, and in reality it is necessary to specify an address in units of bits, but since the explanation will be complicated, the minimum address specification will be made in units of data. The buffer memory 13 has an area for storing n packets for each terminal device, and the storage area for each terminal device is determined in advance. The reason why the storage areas in the buffer memory are divided in advance for each terminal device in this way is that when data from each terminal device is stored sequentially from the lower address of the buffer memory,
This is because for terminal devices that do not output data, the buffer memory capacity is reduced and address specification becomes complicated. In this embodiment, the upper bits of the address specify the area divided for each terminal device, and the lower bits specify the area of the packet in which data is to be stored and the area in which the data is stored within the packet area.

FIG. 3b shows the configuration of a memory circuit 14 having a capacity to store the contents of address counters 15 and 16 for each terminal device. Addressing of the memory circuit 14 is specified using the above-mentioned upper bits.

The operation of one embodiment of the present invention will be described below.

In this explanation, terminal devices 9-1 to 9-N to 10-
Consider the case where packets are sent to nodes 1 to 10-N.

Switching of the write address WA and read address RA of the buffer memory 13 and the storage circuit 14 is performed by selection circuits 18 and 19.
9 is controlled by a signal from the packet insertion control circuit 20. First, each terminal device 9-1 to 9-N
The case of writing data into the buffer memory 13 will be explained. The terminal device is switched in the terminal selection circuit 24 by a signal from the terminal address generation circuit 22. Further, the output of the terminal address generation circuit 22 is equivalent to the upper bits of the address of the buffer memory 13, thereby specifying an area divided for each terminal device, and the lower bits are specified by the address counter 15. Each time the address counter 15 counts up, it rewrites the contents of the area of the storage circuit 14 corresponding to the terminal device with the counted up value. In addition, the address counter 15 stores the current terminal address every time l pieces of data are stored in the buffer memory.
Store it in FIFO17. When the selected terminal device changes, the contents of the area of the memory circuit 14 corresponding to the selected terminal device are set in the address counter 15, and the address is specified by counting up from that value.

When reading the contents of the buffer memory 13,
Reading is performed in the order stored in FIFO17, and FIFO
The output of address counter 17 becomes the upper bit of the address, and the contents of address counter 16 are stored in memory circuit 14 every time the address counter 16 counts up, as in the case of writing.
When the terminal address output by the FIFO changes, the contents of the area of the storage circuit 14 corresponding to the terminal address are set in the address counter 16. The above is the buffer memory control performed on the transmitting side.

The above control is similarly performed on the receiving side. Note that on the receiving side, the FIFO 17 is not necessary because the packet extraction circuit 3 can sequentially extract the terminal addresses.

By controlling the buffer memory 13 as described above, even though only one buffer memory 13 is provided, when viewed from the terminal device side, it becomes as if it had an independent buffer memory.

As described above, according to the present invention, one buffer memory 13 and one set of address counters can be shared by a plurality of terminal devices, so the scale of the buffer memory control circuit can be reduced. Furthermore, since it is sufficient to prepare only one large-capacity memory, costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of a conventional buffer memory control system, FIG. 2 is an embodiment of the present invention, FIG. 3a is a diagram showing the area configuration of the buffer memory according to the invention, and FIG. be. 1...Transmission line, 2...Packet insertion circuit, 3...
...Packet extraction circuit, 9-1 to 9-N, 10-1
~10-N... terminal device, 13... buffer memory, 14... storage circuit, 15, 16... address counter, 17... FIFO, 18, 19... selection circuit, 20... packet insertion control circuit, 21 ……
Packet extraction control circuit, 22, 23...Terminal address generation circuit, 24, 25...Terminal selection circuit.

Claims (1)

[Scope of Claims] 1. In a buffer memory control method used in packet transmission in which data from a plurality of terminal devices is converted into packets and transmitted, one buffer memory and write and read addresses are specified for the plurality of terminal devices. A set of address counters is provided to allocate an area of the buffer memory equally to each terminal device, and the upper bits of the address specify an area divided for each terminal device, and the lower bits specify a packet in which data is stored. The contents of the memory circuit are specified every time an address counter indicating the data writing and reading position for each terminal counts up due to data writing and reading. It is rewritten to the counted up value, and when the designation of the area divided by the terminal device changes, the contents of the area of the storage circuit corresponding to the area is set to the address count, and the address is counted up from that value. A buffer memory control method in packet transmission, characterized in that a buffer memory is specified.