JPH0228948B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a clamp circuit in a video circuit for a television, display, etc., and particularly to a clamp circuit suitable for a large-amplitude, wide-band video circuit.

[Background of the invention]

A general configuration of a video signal pedestal clamp circuit is shown in Japanese Patent Publication No. 59-35542.
This configuration assumes that a circuit with low output impedance is connected before the clamp circuit and a circuit with high input impedance is connected after the clamp circuit. No consideration was given to the case where the

An example of improving the clamping characteristics by lowering the output impedance of the amplifier that sends the signal to the clamp circuit is the circuit shown in Figures 5 and 6, published in "Television Technology, December 1981 issue." TRs 703 and 704 in FIG. 5 form a complementary emitter follower circuit in order to lower the output impedance of the amplifier. In the circuit shown in FIG. 5, the TRs 703 and 704 contribute to lowering the output impedance as impedance conversion amplifiers, but no consideration was given to the increase in loss in the high frequency range where impedance conversion is incomplete.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a clamp circuit that is capable of stable DC regeneration and has little loss in a circuit configuration in which the output impedance of the preceding stage is not sufficiently low.

[Summary of the invention]

A typical clamp circuit is designed to lower the charging/discharging time constant of the DC blocking capacitor by placing a low output impedance circuit in the front stage, so that charging/discharging is completed in a short clamping period. However, it is not easy to lower the output impedance in a high-output broadband circuit because it increases power consumption. On the other hand, if the output impedance of the previous stage is not low enough, the charge accumulated in the DC blocking capacitor during the non-clamping period will be released during the clamping period, and the current flowing at that time will pass through the previous stage, causing a voltage drop at the output impedance of the previous stage. is added to the output signal of The voltage drop decreases as the charge accumulated in the DC blocking capacitor is released, but because the charging/discharging time constant is large, the voltage drop remains large even near the end of the clamp period. The signal to which the voltage drop just before the end of the clamp period is added is clamped to a constant potential, and since the voltage drop changes depending on the content of the signal, the original signal itself is not clamped to a constant potential.

Therefore, the present invention provides a current bypass path in parallel with the DC blocking capacitor to reduce as much as possible the charge accumulated in the DC blocking capacitor during the non-clamping period, thereby suppressing the current flowing through the front stage circuit during clamping, thereby achieving stable clamping operation. It is characterized by causing the person to do the following.

[Embodiments of the invention]

FIG. 1 is a diagram showing the principle of the present invention. 1 is a circuit before the clamp circuit, and is a voltage source with an output impedance r. 2 is the next stage circuit, through which a load current _i1 flows according to the input voltage. 3 is a current bypass circuit,
4 is a DC blocking capacitor, 5 is a clamp voltage source,
6 is a switch. Depending on the configuration of the switch 6, there are two types of clamps: a synchronous clamp that opens and closes periodically from the outside, and an asynchronous clamp that opens and closes depending on the signal content.The present invention is applicable to both of these methods. Since there is no major difference in principle, the explanation will be given below using a synchronous clamp as an example.

When a signal is output from the preceding stage circuit 1, only its AC component is transmitted to the next stage circuit 2 via the DC blocking capacitor 4. In the next stage circuit 2, when the switch 6 is closed, a DC potential is applied to the signal by the clamp voltage source 5. While the switch 6 is open, current flows from the next stage circuit 2 to the DC blocking capacitor 4 or from the DC blocking capacitor 4 to the next stage circuit 2. Since the principles are the same, only the case where current flows from the next stage circuit 2 to the DC blocking capacitor 4 will be described below. Further, as a condition in this case, the clamp potential is higher than the DC output potential of the front stage circuit 1. When current flows into the DC blocking capacitor 4 from the next stage circuit 2, the current bypass circuit 3 extracts the current from the next stage circuit 2 to the previous stage circuit 1 according to the amount. It is assumed that the current i ₂ drawn by the current bypass circuit 3 to the previous stage circuit is set to be approximately equal to the current i ₁ flowing in from the next stage circuit 2 (it must never exceed i ₁ ). At this time, almost no charge is accumulated in the DC blocking capacitor 4. Next, when the synchronization switch 6 is closed, while the synchronization switch 6 is open,
That is, the charge accumulated in the DC blocking capacitor 4 during the non-clamping period is extracted, and DC regeneration is performed by the clamp voltage source 5. However, since almost no charge is stored in the DC blocking capacitor 4, even if the discharge time constant is large, no problematic voltage drop occurs and stable DC regeneration is possible.

FIG. 2a is a diagram showing an example of the waveform of a clamped signal, and FIG. 2b is a diagram showing the waveform of a clamp pulse. When the clamp pulse is input, the synchronous switch 6 is closed and the clamp voltage source 5 performs DC regeneration. The depression h in the signal waveform during the clamp period in FIG. 2a is due to the voltage drop caused by the output impedance of the preceding circuit 1.

An embodiment of the present invention in the output stage of a video circuit of a CRT display is shown in FIG. resistance 7,
The transistor 8 and the resistor 9 constitute a common emitter amplifier, which corresponds to the front stage circuit 1 in FIG. 10 is
This is the cathode of the CRT and corresponds to the next stage circuit 2 in FIG. Further, 11 is a bypass transistor, and 12 is a clamp transistor, which correspond to the current bypass circuit 3 and the synchronous switch 6 in FIG. 1, respectively. Other signals are the same as in FIG. A video signal input from a terminal A is amplified by a grounded emitter amplifier 1, and only its alternating current component is transmitted to a cathode 10 via a direct current blocking capacitor 4. Therefore, this circuit regenerates the DC component using a synchronous clamp and drives the cathode 10. The operation will be explained in detail below. First, when no clamp pulse is input to terminal B, that is,
During the display period of the CRT display, a cathode current flows through the bypass transistor 11 and charges are accumulated in the DC blocking capacitor 4. However, since it is charged by the base current of the bypass transistor 11, the current amplification factor of the bypass transistor 11 is
If hfe, the charging current of the DC blocking capacitor 4 is 1/(1+hfe) times the cathode current, and the remainder is bypassed to the grounded emitter amplifier 1 at the previous stage. Therefore, if hfe is large enough, the DC blocking capacitor 4 will hardly be charged during the non-clamping period. Next, when a clamp pulse is input to terminal B, the clamp transistor 12 becomes conductive.
The charge accumulated during the non-clamp period is extracted from the DC blocking capacitor 4, and the potential on the cathode side of the DC blocking capacitor 4 becomes approximately equal to the potential of the clamp voltage source 5. Here, the clamp current that flows when the charge is extracted from the DC blocking capacitor 4 by the clamp transistor 12 is supplied through the load resistor 9 of the front-stage circuit 1, so that a voltage drop occurs there. Furthermore, since the charging/discharging time constant of the DC blocking capacitor is large, charging/discharging is not completed even just before the end of the clamping period, and the clamping potential varies by the voltage drop across the load resistor 9. However, as mentioned above, in the circuit of FIG. 3, almost no charge is accumulated in the DC blocking capacitor 4 during the non-clamping period, so the clamp current drawn out during the clamping period is also small. Therefore, there is little voltage drop due to the output impedance of the previous stage, and stable clamping operation can be performed. Furthermore, according to the circuit shown in Figure 3,
During the non-clamping period, the accumulated charge in the DC blocking capacitor 4 hardly changes, so the sub is reduced, so by lowering the capacitance of the DC blocking capacitor 4 and lowering the charging/discharging time constant during the clamping period, more stable clamping operation can be achieved. It becomes possible to do this. That is, the bypass transistor 11 operates as a variable current source that generates a current that is a current amplification factor Hfe times the current flowing through the capacitor 4, and bypasses most of the cathode current from the capacitor 4. In the circuit of Fig. 3, the clamp voltage source 5
It is assumed that the potential of the transistor 8 is higher than the collector potential of the transistor 8 when there is no signal.

FIG. 4 shows an improved embodiment of the circuit shown in FIG. The first difference is that the bypass transistor 11
A capacitor 14 is inserted in parallel between the base and emitter of the oscillator, thereby preventing deterioration of frequency characteristics. In the circuit shown in FIG. 3, when the cathode current is small, the base-emitter resistance of the bypass transistor 11 is extremely large, and together with the capacitance of the cathode terminal 10, it forms a low-pass filter, resulting in deterioration of high frequency characteristics. Therefore, as shown in FIG.
By inserting a capacitor 14 between the emitters, high frequency components are bypassed and high frequency characteristics are improved. The second difference is that the cathode is connected to a sufficiently high voltage source via a resistor 15 so that the cathode potential is determined even when no cathode current flows. The diode 13 is inserted to prevent backflow and to reduce the capacitance connected in parallel with the cathode terminal 10. Since the other operations are the same as the circuit shown in FIG. 3, their explanation will be omitted here.

FIG. 5 similarly shows the final stage of the video circuit of a CRT display, and is a diagram showing an embodiment in which a current mirror is used as the current bypass circuit 3. Since the bypass transistor 11 and the diode 16 constitute a current mirror, the cathode current is divided into a current flowing into the DC blocking capacitor 4 and a current flowing into the pre-stage circuit 1 via the bypass transistor 11. The division ratio is inversely proportional to the values of the resistors 17 and 18. Therefore, if the value of the resistor 18 is set sufficiently small, most of the cathode current will be bypassed to the front stage circuit 1 via the resistor 18 and the transistor 11, and the DC blocking capacitor 4 will hardly be charged. Here, the diode 16 compensates for the characteristics by diode-connecting a transistor with substantially the same characteristics as the bypass transistor 11. Further, the capacitor 14 is the fourth
As shown in the figure, this is to prevent deterioration of high frequency characteristics, and the same effect can be obtained by inserting it between the base and emitter of the bypass transistor 11 or between the base and cathode 10 of the bypass transistor 11.

FIG. 6 is a diagram showing an embodiment in which the current mirror is configured in two stages in the circuit of FIG. 5, and almost all of the cathode current is bypassed to the preceding stage circuit 1. Bypass transistor 11, diode 1
6, resistor 17 and resistor 18 constitute a first current mirror, transistor 21, diode 19,
The resistor 20 and the resistor 22 constitute a second current mirror. For the bypass transistor 11 and the diode 16, and for the transistor 21 and the diode 19, transistors having substantially the same characteristics are used to compensate for the characteristics. Also, resistor 17, resistor 18, resistor 20
and resistor 21 have the same resistance value. The cathode current is connected to resistor 17 and resistor 1 by the first current mirror.
Divided by an inverse ratio of 8. Since the resistance values of the resistor 17 and the resistor 18 are equal, the cathode current is divided into two parts: one goes to the DC blocking capacitor 4, and the other goes to the front stage circuit 1 via the second current mirror diode 19.
In the second current mirror circuit flowing into the current mirror circuit, since the resistance values of the resistors 20 and 22 are equal, a current equal to the current flowing through the diode 19 is extracted from the current blocking capacitor 4. In other words, a current equal to the current injected by the first current mirror is drawn from the DC blocking capacitor 4 by the second current mirror, and the DC blocking capacitor 4 is not charged. Note that the circuit shown in FIG. 6 must be designed so that the sum of the currents drawn by the current mirror does not exceed the cathode current. This is because, if it were to be exceeded, the cathode potential would automatically continue to fall due to a vicious cycle in which the cathode potential falls, the cathode current increases, and the cathode potential further falls.

Since the charge accumulated in the DC blocking capacitor 4 is almost 0, there is no voltage drop due to the output impedance of the grounded emitter amplifier 1 in the preceding stage, and stable clamping operation is exhibited.

FIG. 7 is a diagram showing an embodiment of a clamp circuit in which emitter followers are arranged at the front stage and the rear stage. The transistor 24 and the resistor 23, and the transistor 26 and the resistor 25 each constitute an emitter follower.
They correspond to the previous stage circuit 1 and the next stage circuit 2 in FIG. 1, respectively. The operation will be briefly explained below. Figures 3 to 6
Contrary to the circuit shown in the figure, during the non-clamp period, the input current of the emitter follower circuit 2 consisting of the transistor 26 and the resistor 25 is extracted from the clamp circuit.
Most of the current is directly supplied from the preceding stage circuit 1 by the bypass transistor 11, and only a small amount is supplied from the DC blocking capacitor 4. Therefore, even if charge is injected from the clamp voltage source 5 through the clamp transistor 12 and diode 13 during the clamp period, the amount of clamp current flowing at that time is small, and the influence of voltage drop due to the output impedance of the preceding stage circuit 1 is small. Normally, in the configuration shown in FIG. 7, the input impedance of the next-stage circuit 2 is large and the output impedance of the previous-stage circuit 1 is small, so there is no need to use the present invention. When used in
The circuit of the present invention is effective because it is difficult to sufficiently lower the output impedance of the front-stage circuit 1, which leads to an increase in power consumption. In the circuit shown in FIG. 7, the potential of the clamp voltage source 5 is assumed to be smaller than the DC potential of the previous stage output.

FIG. 8 is a diagram showing an actual example of a clamp waveform of a conventional clamp circuit. A voltage drop of 20V can be confirmed when clamping.

FIG. 9 is a diagram showing a clamp waveform obtained by using the same circuit as FIG. 8 but improved by the method of FIG. 4. In Figure 8, it can be seen that the voltage drop during clamping, which was about 20V, has been reduced to about 3 to 5V.

Although the above explanation is about a synchronous clamp, it is also possible to construct an asynchronous clamp circuit by replacing the clamp transistor 12 with a diode in each of the embodiments shown in FIGS. 3, 4, 5, 6, and 7. be. Since the operations are the same, repeated explanation will be omitted.

〔Effect of the invention〕

According to the present invention, by adding at least one transistor and one capacitor to the conventional clamp circuit, charging to the DC blocking capacitor can be suppressed.
Not only can voltage level fluctuations during clamping be suppressed, but also sag characteristics can be improved, making stable DC regeneration possible. Furthermore, power consumption can be reduced compared to the case where a low output impedance circuit is inserted before the clamp circuit.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a waveform diagram showing a clamped signal waveform and clamp pulse, Fig. 3 is a circuit diagram showing the most basic embodiment of the invention, and Fig. 4 is a diagram showing the clamped signal waveform and clamp pulse. FIG. 3 is a circuit diagram showing an embodiment with improved high frequency characteristics; FIG. 5 is a circuit diagram showing an embodiment using a current mirror; FIG. 6 is a circuit diagram showing an embodiment using two stages of current mirrors; Figure 7 shows
A circuit diagram showing an embodiment using a PNP type clamp transistor, FIG. 8 is a waveform diagram showing a clamp waveform of a conventional circuit, and FIG. 9 is a waveform diagram showing a clamp waveform by the circuit of the present invention shown in FIG. 4. . 1... Pre-stage circuit, 2... Next-stage circuit, 3... Current bypass circuit, 4... DC blocking capacitor, 5...
...Clamp voltage source, 6...Synchronization switch.

Claims (1)

[Claims] 1. A pre-stage circuit having high output impedance;
A current bypass consisting of a DC blocking capacitor inserted between the load and the output terminal of the capacitor, a switching means that periodically connects and connects a low impedance voltage source, and a variable current source connected in parallel with the capacitor. A clamp circuit comprising a circuit, wherein the current flowing from the variable current source changes according to the current flowing through the load and is a predetermined times the current flowing through the capacitor. 2 The variable current source is composed of a transistor, the base-collector path of this transistor is connected in parallel with the capacitor, the emitter is connected to the load, and the current flowing through the capacitor is multiplied by the current amplification factor of this transistor. 2. The clamp circuit according to claim 1, wherein the clamp circuit is bypassed by a current bypass circuit.