JPH0312508B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a clamp circuit in a video circuit for a television or display, and particularly to a clamp circuit suitable for the final stage of a large amplitude, wide band video circuit.

[Background of the invention]

A general configuration of a video signal pedestal clamp circuit is shown in Japanese Patent Laid-Open No. 53-63807.
This configuration assumes that a low output impedance circuit is connected to the front stage of the clamp circuit and a high input impedance circuit to the rear stage, and does not take into account the case where the output impedance of the front stage is not low enough. .

As an example of improving the clamping characteristics by lowering the output impedance of the amplifier that sends the signal to the clamp circuit, there are the circuits shown in Figures 5 and 6 described in "Television Technology, December 1981 issue." Figure 5
TRs 703 and 704 form a complementary emitter follower circuit in order to lower the output impedance of the amplifier. In the circuit shown in Figure 5,
Although the TRs 702 and 704 contribute to lower output impedance as impedance conversion amplifiers, no consideration has been given to the increase in loss in the high frequency range where impedance conversion is incomplete.

[Purpose of the invention]

An object of the present invention is to provide a clamp circuit capable of stable DC reproduction in a circuit configuration in which the output impedance of the preceding stage is not sufficiently low compared to the input impedance of the succeeding stage.

[Summary of the invention]

A typical clamp circuit is designed to lower the charging/discharging time constant of the DC blocking capacitor by placing a low output impedance circuit in the front stage, so that charging/discharging is completed in a short clamping period. However, it is not easy to lower the output impedance in a high-output wideband circuit because it increases power consumption. On the other hand, if the output impedance of the previous stage is not low enough, the charge accumulated in the DC blocking capacitor during the non-clamping period will be released during the clamping period.
Since the current flowing at that time passes through the previous stage, a voltage drop occurs at its output impedance and is added to the output signal of the previous stage. The voltage drop decreases as the charge accumulated in the DC blocking capacitor is released, but because the charging/discharging time constant is large, the voltage drop remains large even near the end of the clamp period. The signal to which the voltage drop just before the end of the clamp period is added is clamped to a constant potential, and since the voltage drop changes depending on the content of the signal, the original signal itself is not clamped to a constant potential.

Therefore, the present invention provides a current source that complementarily injects into or draws from the input side of the DC blocking capacitor a current equal to the current drawn or injected from the output side of the DC blocking capacitor during the clamp period. , it is characterized by preventing current from flowing through the output impedance of the previous stage, and by significantly lowering the charging and discharging time constant of the DC blocking capacitor, and by completing charging and discharging within the clamping period, stable clamping operation is performed. shall be.

[Embodiments of the invention]

FIG. 1 is a diagram showing the principle of the present invention. 1 is a circuit before the clamp circuit and is a voltage source with an output impedance r. 2 is the load of the clamp circuit, that is, the latter stage circuit, and current _i1 is input/output according to the input voltage.
3 is a clamp current complementary circuit, 4 is a DC blocking capacitor, 5 is a clamp voltage source, and 6 is a switch. Depending on the form of this switch 6, there are two types: a synchronous clamp that periodically controls opening and closing from the outside, and an asynchronous clamp that opens and closes depending on the signal content. Since there is not much difference in terms of performance, we will explain the synchronous method below as an example. Clamp current complementary circuit 3
is a circuit that extracts a current _i 3 from the input side of the DC blocking capacitor 4 or injects it into the input side, which is equal to the clamp current i ₂ that is injected into or extracted from the output side of the DC blocking capacitor 4 during clamping. The operation will be briefly explained below. During the non-clamping period, the switch 6 is open, and a charge is accumulated in the DC blocking capacitor 4 by the current i ₁ flowing from the subsequent circuit 2. DC blocking capacitor 4
Although current may flow from the circuit to the subsequent circuit 2,
Since the principles are the same, only the case where current flows from the subsequent stage circuit 2 will be described below. The charge accumulated in the DC blocking capacitor 4 is drawn out to the clamp voltage source 5 through the switch 6 during the clamp period, and the potential of the downstream terminal of the DC blocking capacitor 4 is fixed to the potential of the clamp voltage source 5. At this time, if the charging/discharging time constant of the DC blocking capacitor 4 is large, a large clamp current _i2 flows through the output impedance of the front stage circuit 1 even just before the end of clamping, causing a voltage drop, and this voltage drop is added to the original signal. be clamped. Furthermore, since the voltage drop changes depending on the content of the signal, the DC potential of the clamped signal is not stable as a result. Therefore, when the clamp current i ₂ flows, by injecting a current i ₃ equal to it into the front stage side of the DC blocking capacitor 4, the clamp current i ₂ is supplied as i ₃ from the clamp current complementary circuit 3. Since it does not flow through the pre-stage circuit 1, the voltage drop described above does not occur. Furthermore, the charging/discharging time constant of the DC blocking capacitor 4 during the clamping period is significantly reduced, and a sufficient clamping operation can be performed with a short clamping period.

FIG. 2 shows, as a specific embodiment of the present invention,
FIG. 3 is a diagram showing an example of clamping at the final stage of a video circuit of a CRT display. Resistor 7, transistor 8, and resistor 9 constitute a common emitter amplifier,
This corresponds to the front-stage circuit 1 in FIG. 10 is the cathode of the CRT, which corresponds to the latter stage circuit 2 in FIG. 11
1 is a complementary transistor for injecting a clamp current into the pre-stage circuit 1, and 12 is a clamp transistor, each of which corresponds to the clamp current phase circuit 3 switch 6 in FIG. 4 indicates a DC blocking capacitor, and 5 indicates a clamp voltage source. Resistor 13 is a protection resistor that fixes the cathode potential when no clamp pulse is applied. When a clamp pulse is input from the B terminal, the clamp transistor 12 becomes conductive, and the charge accumulated during the non-clamp period is extracted from the DC blocking capacitor 4. The clamp current flowing at this time is divided by the complementary transistor 11, and only the base current flows to the clamp voltage source 5, and most of the other part is injected into the front stage of the DC blocking capacitor 4. The subsequent potential of the DC blocking capacitor 4 is fixed to the potential of the clamp voltage source 5. At this time, the DC blocking capacitor 4 is temporarily short-circuited by the complementary transistor 11, and almost no clamp current is supplied from the previous stage. Furthermore, since the charging/discharging time constant of the DC blocking capacitor becomes extremely small, stable clamping operation is possible within a short clamping period. The circuit shown in FIG. 2 is effective only when a current is injected from the subsequent circuit 2 and the clamp potential is higher than the DC potential of the output of the preceding circuit 1.

FIG. 3 is a diagram showing an embodiment of the present invention that operates regardless of the magnitude of the clamp potential and the DC potential of the output of the front stage circuit 1 when charge is injected from the rear stage circuit 2. Transistors 16, 17, resistor 1
4. The resistor 15 constitutes a first current mirror circuit, and the transistors 20 and 21 and resistors 18 and 19 constitute a second current mirror circuit. When a clamp pulse is input to the B terminal, the clamp transistor 12 becomes conductive, and the charge accumulated in the DC blocking capacitor 4 during the non-clamp period is transferred to the transistor 1.
6. It is pulled out through the resistor 14. Let the current flowing at this time be _i2 . If the resistors 14 and 15 are chosen equal here, the current i ₂₃ flowing through the transistor 17 due to the first current mirror circuit is equal to i ₂ .
Current i ₂₃ is drawn from a sufficiently high voltage source (not shown) connected to terminal 22 through transistor 20 and resistor 18 . If the resistors 18 and 19 are chosen equally, the second current mirror circuit produces a current equal to the current i ₂₃ , that is, a current equal to the clamp current i ₂ .
i ₃ is injected into the front stage of the DC blocking capacitor 4 via the resistor 19 and the transistor 21 . Since the current i ₃ is injected from a sufficiently high voltage source connected to the terminal 22, it is not affected by the magnitude relationship between the clamp potential and the DC potential of the output of the front-stage circuit 1. however,
The circuit configuration is somewhat more complicated than the circuit shown in FIG.

FIG. 4 is a diagram showing an embodiment in which charges are extracted to the subsequent circuit 2 and the clamp potential is lower than the DC potential of the output of the preceding circuit 1. The principle is almost the same as the circuit shown in Figure 2, and the differences are as follows.
This is because a current i ₃ equal to the current i ₂ injected into the next stage side of the capacitor 46 during clamping is drawn out from the circuit at the previous stage of the capacitor 4, so a detailed explanation will be omitted.

FIG. 5 is a diagram showing an embodiment of the present invention that operates regardless of the magnitude of the clamp potential and the output DC potential of the preceding stage circuit 1 when charges are extracted to the subsequent stage circuit 2. The principle is almost the same as the circuit shown in FIG. A current equal to the current i ₂ injected into the latter stage of capacitor 4 when clamping is applied to capacitor 4.
It is pulled out from the front side.

As described above, according to the present invention, by injecting a current i ₃ equal to the clamp current i ₂ into the front stage side of the DC blocking capacitor 4, an AC closed loop is formed and voltage drop caused by the output impedance of the front stage circuit is prevented. be able to.

The specific effects will be explained using figures.

Figures 6 and 7 show a conventional clamp circuit in the final stage of the video circuit of a CRT display, and a second clamp circuit of the present invention.
An example of a cathode voltage waveform when each of the clamp circuits shown in the figure is used is shown. The period indicated by _tC in the figure is the clamp period, and compared to the waveform of the conventional circuit shown in Fig. 6, the waveform of the present invention shown in Fig. 7 has a considerably improved voltage effect during the clamp period _tC . can be confirmed. To give a specific numerical value as an example of a case where the input impedance of the subsequent stage circuit 2 is considerably reduced, conventionally there was a voltage drop of about 20V during the _tC period, but with the present invention, it has been reduced to about 1 to 2V. Significantly improved.

Although the above explanation is about a synchronous clamp, it is also possible to construct an asynchronous clamp circuit by replacing the clamp transistor 12 with a diode in the embodiments shown in FIGS. 2, 3, 4, and 5. Since the operations are the same, repeated explanation will be omitted.

〔Effect of the invention〕

According to the present invention, by adding a small number of circuits, it is possible to prevent a voltage drop due to the output impedance of the preceding stage circuit during clamping, and stable DC reproduction is possible. Furthermore, compared to the case where a circuit with low output impedance is provided in the preceding stage, power consumption is reduced.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a circuit diagram showing an example in which charges are injected from the next stage and the clamp potential is larger than the DC potential of the output of the previous stage circuit, and Fig. 3 is a circuit diagram of the next stage. Figure 4 is a circuit diagram showing an embodiment that operates regardless of the magnitude relationship between the clamp potential and the DC potential of the output of the previous stage when charge is injected from the output. FIG. 5 is a circuit diagram showing an example of a case where the DC potential is smaller than the DC potential of the output stage, and FIG. 6 is a clamp waveform diagram of a conventional clamp circuit, and FIG. 7 is a waveform diagram of a clamp circuit of the present invention. 1... Pre-stage circuit (voltage source), 2... Post-stage circuit (current source), 4... DC blocking capacitor, 5... Clamp voltage source, 6... Synchronous switch, 3... Clamp current complementary circuit.

Claims (1)

[Scope of Claims] 1. A DC blocking capacitor inserted in a signal transmission path between a front-stage circuit and a rear-stage circuit, and a low-impedance DC blocking capacitor inserted in a signal transmission path between a front-stage circuit and a rear-stage circuit, and a switch means that conducts intermittently to a terminal on the rear-stage circuit side of the capacitor. A clamp circuit connected to a voltage source and configured to discharge the capacitor charged during the non-conducting period of the switching means during the conducting period of the switching means, further comprising: a current control circuit for controlling discharge of the capacitor; The current control circuit moderates the discharge current of the capacitor flowing through the output impedance of the preceding stage circuit during the conduction period of the switch means,
A clamp circuit characterized by suppressing a voltage drop caused by the discharge current flowing through the output impedance. 2. A low-impedance voltage source is connected to a DC blocking capacitor inserted in the signal transmission path between the front-stage circuit and the rear-stage circuit, and a terminal on the rear-stage circuit side of the capacitor via a switch means that conducts intermittently,
In the clamp circuit for charging the capacitor discharged during the non-conducting period of the switching means during the conducting period of the switching means, a current control circuit for controlling charging of the capacitor is provided, and the current control circuit is configured to control the charging of the capacitor. A clamp circuit characterized in that the charging current of the capacitor flowing through the output impedance of the preceding stage circuit is relaxed during the conduction period of the switching means, and the voltage drop caused by the charging current flowing through the output impedance is suppressed.