JPH0230573B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bipolar semiconductor device with improved emitter-related parts and a method for manufacturing the same.

Conventionally, a bipolar semiconductor device having the structure shown in FIG. 1 has been known.

The figure is a side cross-sectional view of the main parts, 1 is a p ^- type silicon semiconductor substrate, 2 is an n ⁺ type buried layer, 3 is an epitaxially grown n ^- type silicon semiconductor layer, 4 is a silicon dioxide insulating film, and 5 is a p ⁺ type element isolation region,
6 is a p-type base region, 7 is an n ⁺ type emitter region,
Reference numeral 8 indicates an n ⁺ type collector contact region, 9E an emitter electrode, 9B a base electrode, and 9C a collector electrode.

In general, when manufacturing a semiconductor device, alignment is always a problem. In particular, in the above-mentioned bipolar semiconductor device, the emitter region 7 is formed inside the base region 6, and the electrode contact window of the emitter electrode 9E is The emitter area 7
Since the mask must be made inside the mask, precise mask alignment is required. If,
If the formation of the electrode contact window is misaligned, the emitter electrode 9E may overlap the base region 6 in some cases, resulting in an emitter-base short circuit. Moreover, even if this state does not occur, the insulating film 4
If the emitter electrode 9E and base electrode 9B are close to each other, migration may occur during actual operation, resulting in a short circuit.

In order to avoid such an accident, it is sufficient to provide sufficient margin for mask alignment, but this does not allow for an improvement in the degree of integration.

The present invention reduces the number of mask alignment steps by diffusing impurities from electrodes to form at least an emitter region, and prevents short circuits from occurring even if there is not much allowance in various dimensions. ,
As a result, the device can be highly integrated, and even if such an electrode is formed, there is no risk that the electrode formation surface of the semiconductor substrate will be eroded by the electrode, and
This is intended to reduce the number of heat treatment steps and prevent unnecessary impurity re-diffusion in the impurity diffusion region, and this will be explained in detail below.

2 to 5 are sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

Refer to FIG. 2 (1) Form up to the base region using a conventionally known technique.

That is, n ⁺ type impurities are selectively deposited on p ^- type silicon semiconductor substrate 11, and then n ^- type silicon semiconductor layer 13 is epitaxially grown. As a result, an n ⁺ type buried layer 12 is also formed.

For example, silicon dioxide insulating film 1 is formed by thermal oxidation method.
Grow 4.

For example, the silicon dioxide insulating film 14 is patterned using a photolithography technique to selectively form openings, and then a p type impurity such as boron is introduced to form a p ⁺ type element isolation region 15.

The silicon dioxide insulating film 14 is patterned again to selectively form openings, and then, for example, boron is introduced to form the p-type base region 16.

See Figure 3 (2) Remove the silicon dioxide insulating film 14.

(3) Sputtering is applied to form a phosphorus (or arsenic)-containing molybdenum silicide film to a thickness of, for example, 3000 mm.
Form to about [Å]. To carry out this sputtering method, molybdenum and silicon are placed as sputter targets in an arbitrary ratio, and phosphine (PH ₃ )/argon (Ar) is used as the sputtering gas atmosphere.

(4) The phosphorus-containing molybdenum silicide film is patterned using photolithography to form an emitter electrode 17E and a collector electrode 17C.

Refer to FIG. 4 (5) Perform high temperature heat treatment in an oxidizing atmosphere to form the silicon dioxide insulating film 18 to a thickness of, for example, 3000~.
Formed to about 5000 [Å]. As the high temperature oxidizing atmosphere in this case, a dry oxidizing gas atmosphere at a temperature of 1000 [° C.] may be used. Under this condition, the insulating film formed on the emitter electrode 17E and the collector electrode 17C is formed several times thicker than that on the silicon semiconductor layer 13.

By this heat treatment, the silicon semiconductor layer 13 is removed from the emitter electrode 17E and the collector electrode 17C.
Phosphorus is diffused into the n ⁺ type emitter region 19 and
An n ⁺ type collector contact region 20 is formed. Therefore, these regions 19 and 20 are formed in self-alignment with the respective electrodes 17E and 17C.

Refer to Fig. 5 (6) After patterning the silicon dioxide insulating film 18 using the usual photolithography technique to form a base electrode contact window, a boron-containing molybdenum silicide film is formed to a thickness of, for example, 3000 mm.
Form to about [Å]. This is done by applying the sputtering method as in step (3) above.

(7) The boron-containing molybdenum silicide film is patterned to form a base electrode 21 using a conventional photolithography technique.

(8) Thereafter, a conventional technique is applied to form a protective film, wiring, etc., and the device is completed.

In this embodiment, the emitter electrode 17E and the collector electrode 17C are formed at the same time, and then the base electrode 21 is formed, but it is also possible to form these at the same time and then heat-treat them at the same time. good. In that case, since a large amount of boron is diffused from the base electrode 21, the p ⁺ type base contact region is formed deeply, and the ohmic contact becomes even better. In addition, the emitter electrode 17
E, base electrode 21 with respect to collector electrode 17C
To form these at the same time, in the state shown in Figure 3, a photoresist film pattern having an opening in the area where the base electrode is to be formed is formed, and then a boron-containing molybdenum silicide film is formed. The patterning may be performed by dissolving the photoresist film and lifting off the boron-containing molybdenum silicide film. Furthermore, if necessary, the base electrode 21 may be formed first, and the emitter electrode 17E and collector electrode 17C may be formed later.

By the way, in the present invention, since the formation of an impurity-containing high melting point metal silicide film is important, next,
This point will be explained.

The impurities can be selected as appropriate depending on the required conductivity type and characteristics, such as the above-mentioned phosphorus and boron (the sputtering gas atmosphere is diborane (B ₂ H ₆ )/argon (Ar)). Or change the arsenic (spatter gas atmosphere to arsine (AsH ₃ )/
Argon (Ar) may be used. Further, as the high melting point metal, in addition to the above-mentioned molybdenum, tungsten (W), platinum (Pt), tantalum (Ta), etc. can be used. Note that the high melting point metal silicide mentioned here may have a different stoichiometric composition as long as it can maintain a stable state during heat treatment in the manufacturing process of a semiconductor device.

The sputtering method was carried out using the apparatus shown in FIG.

In the figure, 31 is a chamber, 32 is a gas supply pipe, 33 is an exhaust pipe, 34 is a holder, 35 is a sample such as a silicon wafer, 36 is a shutter, and 37 is a target such as molybdenum silicide. There is.

The specific conditions are as follows.

Molybdenum silicide: 5 to 50 [wt%] silicon
Mainly contains 36.9 [wt%] Sputter gas: (PH ₃ + Ar) Gas pressure: 5 to 10×10 ^-2 [Torr] Sputter power supply: DC (voltage 450 [V], current 400 to
800 [mA] Target-sample distance: about 40 [mm] Impurity distribution when the phosphorus-containing molybdenum silicide film formed in this way is heat-treated at a temperature of 1000 [℃] and phosphorus is diffused into the silicon substrate. is shown in FIG.

The specific resistance of the phosphorus-containing molybdenum silicide film is 5×10 ^-5
It is on the order of [Ω·cm], which is significantly lower than that of polycrystalline silicon.

As is clear from the above description, the main effects of the present invention are listed as follows.

(1) At least, since the emitter region can be formed in a self-aligned manner by impurity diffusion from the emitter electrode, the mask alignment process is reduced, and emitter-base short circuits do not occur even if there is not much dimensional margin. .

(2) The electrode, which is also a source of impurities, has low resistance unlike polycrystalline silicon.

(3) The device can be highly integrated.

(4) Since the electrode is formed from the beginning as a refractory metal silicide film containing impurities of one conductivity type, the substrate The electrode forming surface will not be eroded.

(5) From what is described in (4) above, the number of times the device generates specific heat will naturally decrease, and at that point, unnecessary impurity re-diffusion will be less likely to occur in the impurity diffusion region that has already been created. .

[Brief explanation of drawings]

FIG. 1 is an explanatory side cross-sectional view of the main part of a conventional example, FIGS.
The figure is an explanatory diagram of the sputtering apparatus, and FIG. 7 is a diagram showing impurity distribution. In the figure, 11 is the substrate, 12 is the buried layer, 13
15 is a semiconductor layer, 15 is an isolation region, 16 is a base region, 17E, 17C are electrodes, 18 is an insulating film, 19
20 is an emitter region, 20 is a collector contact region, and 21 is a base electrode.

Claims (1)

[Claims] 1. A step of introducing an opposite conductivity type impurity into a semiconductor substrate of one conductivity type to form a base region, and then applying a sputtering method to a surface of the semiconductor substrate of one conductivity type to form a base region. forming a first high melting point metal silicide film containing impurities, and then patterning the first high melting point metal silicide film to form an emitter electrode on the surface of the opposite conductivity type base region; a step of forming a collector electrode on the surface of a semiconductor substrate of one conductivity type, and then forming an insulating film covering the surface of the semiconductor substrate of one conductivity type and diffusing impurities from the emitter electrode and the collector electrode to form a semiconductor substrate of one conductivity type. a step of forming an emitter region and a collector contact region of one conductivity type; a step of selectively etching the insulating film to form a base electrode contact window; forming a melting point metal silicide film; and then patterning the second high melting point metal silicide film to form a base electrode on the surface of the opposite conductivity type base region. A method for manufacturing a featured semiconductor device.