JPH0230700B2 - PACHINKOKI - Google Patents

Description

[Detailed description of the invention] The present invention secures the right to win by the pachinko ball flying into a predetermined winning hole, and the pachinko ball flying into a winning hole different from the predetermined winning hole. This invention relates to a pachinko machine in which the right to win a prize is exercised by the player.

In pachinko machines, one of the requirements for increasing the player's desire to play is that the winning conditions during the game change depending on the player's skill.

The present invention was made from this point of view, and the configuration of the present invention is to set a solenoid in a driving state that is turned on when a pachinko ball flies into a predetermined winning hole to increase the winning probability, thereby increasing the winning probability. A right securing circuit that secures increasing rights is turned on when a pachinko ball flies into a winning hole different from a predetermined winning hole and the right securing circuit is in an on state, and the solenoid is turned on. This pachinko machine has a right exercise circuit that drives the pachinko machine for a predetermined period of time to exercise the secured right.

Embodiments of the present invention will be described below based on the drawings.

In FIG. 1, reference numeral 1 is an accessory used in the pachinko machine according to the present invention, and the upper part of this accessory 1 is provided with a top prize opening 2, left and right top prize winning holes 3, 4, Side wall prize openings 5 and 6 are provided on both side walls of the object 1. This accessory 1 has a sorting opening 7, and a sorting plate 8 is provided at the bottom thereof. This sorting board 8 is inclined from the back to the front, and the pachinko balls 9 and 10 that fly into the sorting hole 7 from each winning hole 2, 3, 4, 5, and 6 are It is adapted to roll forward of the inclined plate 8 while its course is changed by the installation part 11. Partition plates 12 and 13 are erected in front of the distribution plate 8, and these partition plates 12 and 1
The area between 2 and 2 is a rights securing winning opening 14, and this rights securing winning opening 14 is provided with a rights securing switch 15 having a shape shown in FIG. The function of this rights securing switch 15 will be described later. On both sides of the rights securing winning hole 14, normal winning holes 16 and 17 from which a predetermined number of winning balls are paid out are provided.

Below the accessory 1, there is an attacker prize opening 18,1
9 is provided, and the space between this attacker prize 18 and the attacker prize opening 19 is an attacker 20 that picks up falling pachinko balls. As shown in FIG. 3, this attacker 20 is controlled to open and close by a solenoid 21, and in FIG. 3, 22 is an attacker control lever mechanism. Atatsukar prize opening 18, 19
At the upper part of the player, rights exercise winning holes 23 and 24 are provided facing the attacker winning holes 18 and 19, respectively. The right exercise prize openings 23 and 24 are provided with right exercise switches 25 and 26, respectively.

As shown in FIG. 4, the rights securing switch 15 is connected to a Schmitt waveform shaping circuit 27, and the rights securing switches 25 and 26 are connected to a Schmitt waveform shaping circuit 28. The Schmitt waveform shaping circuits 27 and 28 are connected to each switch 15 and 2.
When 5 and 26 are closed, they each output a high signal. The output signal of the Schmitt waveform shaping circuit 27 is input to a T flip-flop 29.
The output signal of the Schmitt waveform shaping circuit 28 is input to an AND circuit 30. When the T flip-flop is set, that is, in the high state, when a high signal is input from the Schmitt waveform shaping circuit 27, the T flip-flop becomes low. The output signal of the T flip-flop circuit 29 is input to an AND circuit 30 and a 4-bit binary counter circuit 31. The 4-bit binary counter circuit 31 is reset to output a low signal to the NAND circuit 32 when the T flip-flop circuit 29 is in the high state.

33 is a clock circuit, and 34 is a power reset circuit. When the power is turned on, the clock circuit 33 outputs the clock signal A shown in FIG. The signal is output to a circuit 36. The OR circuit 35 combines the reset signal output from the power reset circuit 34 and the NOT circuit 3.
The reset signal inputted from the NAND circuit 32 via the T flip-flop circuit 29 is outputted to the T flip-flop circuit 29.
is reset to a low state when at least one of the power reset circuit 34 and the not circuit 37 is in a high state.

Clock signal A from clock circuit 38 is input to 4-bit binary counter circuit 38. The 4-bit binary counter circuit has four output lines, the output line is connected to the AND circuit 39, the output line is connected to the pilot lamp drive circuit 40, and the output line is connected to the 4-bit binary counter circuit. 41. A rectangular signal shown in FIG. 6 flows through each output line. Reference numeral 42 denotes a pilot lamp, and when the power is turned on, the pilot lamp driver circuit 40 is intermittently turned on and off by the output signal from the 4-bit binary counter circuit 38, so that it is in a blinking state.

The right securing switch 15, the Schmitt waveform shaping circuit 27, and the T flip-flop circuit 29 are turned on when a pachinko ball flies into a predetermined winning opening, and set the solenoid 21, which increases the winning probability, into a drive ready state. , roughly constitutes a right securing circuit that secures the right to increase the winning probability, and the right exercise switches 25 and 26 and the AND circuit 30 are used when a pachinko ball flies into a winning hole different from the predetermined winning hole. Moreover, when the right securing circuit is in the on state, it is turned on and drives the solenoid 21 for a predetermined period of time, forming part of a rights exercising circuit that exercises the secured rights.

AND circuit 30 is T flip-flop circuit 2
9 is in a high state and at least one of the rights exercise switches 25 and 26 is closed, outputs a set signal to the flip-flop circuit 43;
The flip-flop circuit 43 is brought into a high state. The output signal of the flip-flop circuit 43 is input to a not circuit 44 and a differentiation circuit 45. The NOT circuit 44 has a function of canceling the reset of the 4-bit binary counter circuit 41, and when the flip-flop circuit 43 is in the low state, the 4-bit binary counter circuit is reset by the high signal output from the NOT circuit 44. 41 is reset so that the 4-bit binary counter circuit 41 outputs a low signal, and when the flip-flop circuit 43 is in the high state, this reset is released and the clock signal shown in FIG. 7 is output. It is like that. The differentiation circuit 45 is the flip-flop circuit 4
A differential signal is output at the rising edge when 3 changes from low to high, and this differential signal is input to the 4-bit binary counter circuit 38, and the 4-bit binary counter circuit 38 is reset by this differential signal. It is becoming more and more common. The relationship between the clock signal output from the 4-bit binary counter circuit 38 and the clock signal A output from the clock circuit 33 will be explained based on FIGS. 5 and 6. A clock signal with 4 times the period is output from the output line, a clock signal with 8 times the period is output from the output line, and a clock signal with 16 times the period is output from the output line. Each time the 4-bit binary counter circuit 38 is reset, the number is newly counted from the clock signal A immediately after the reset, and the 4-bit binary counter circuit 38 repeatedly outputs the clock signal shown in FIG.

The relationship between the 4-bit binary counter circuit 41 and the clock signal output from the 4-bit binary counter circuit 38 will be explained next.The 4-bit binary counter circuit 41 has three output lines ', ', '. , the clock signal output from the output line' has twice the period of the clock signal output from the output line, and the clock signal output from the output line' has a period twice that of the clock signal output from the output line. The clock signal outputted from the output line' has a period 16 times that of the clock signal outputted from the output line. The clock signals output from each output line ',',' are input to an AND circuit 46. The AND circuit 46 connects each of these output lines',
When ' and ' are each high, a reset signal B shown in FIG. The flip-flop circuit 47 is set by the clock signal output from the output line ' of the 4-bit binary counter circuit 41, and remains in a high state until the reset signal B is input, and the flip-flop circuit 47 remains in the high state until the reset signal B is input. The output signal 47 is input to a solenoid drive circuit 48, a 4-bit binary counter circuit 31, and a 4-bit binary counter circuit 49. This 4
The bit binary counter circuit 49 is set when the flip-flop circuit 47 is high, and outputs the clock signal inputted from the AND circuit 39 to the resistance waveform synthesis circuit 50. The synthesized waveform signal output from the resistance dollar waveform synthesis circuit 50 is input to the voltage variable oscillation circuit 51, and is input to the audio amplification circuit 52.
The sound is converted into sound from the speaker 53. 54 is an AND circuit, and the output signal of the T flip-flop circuit 29, the clock signal from the output line of the 4-bit binary counter circuit 38, and the output signal from the NAND circuit 32 are input to the AND circuit 54. When the T flip-flop circuit 29 and the NAND circuit 32 are at high level, the clock signal from the output line of the 4-bit binary counter circuit is outputted to the pilot lamp drive circuit 55. The light turns on and off repeatedly.

Next, the effect will be explained.

(b) Turn on the power.

When the power is turned on, a reset signal is output to OR circuit 35 and OR circuit 36, and this reset signal is input to T flip-flop circuit 29, flip-flop circuit 43, and flip-flop circuit 47. Then, the T flip-flop circuit 29, the flip-flop circuit 4
3. The flip-flop circuit 47 becomes low. Since the flip-flop circuit 43 is in a low state, the note circuit 44 is in a high state.
The 4-bit binary counter circuit 41 is reset and the output of its clock signal is prohibited.

When the power is turned on, the clock circuit 33 outputs a clock signal A.
The signal is input to a bit binary counter circuit 38. Since the clock signal outputted from the output line of the 4-bit binary counter circuit 38 is input to the pilot lamp drive circuit 40, the pilot lamp 42 blinks when the power is turned on.

AND circuit 54 indicates that NAND circuit 32 is high;
T flip-flop 2 regardless of low state
9 is in the low state, the clock signal output from the output line of the 4-bit binary counter circuit 38 is not output to the pilot lamp 55. Therefore, the pilot lamp 56 is in an extinguished state.

The solenoid 21 is connected to the flip-flop circuit 4.
Since 7 is in the low state, it is not driven and the attacker car 2
0 is in the closed state, and since the flip-flop circuit 47 is in the low state, the 4-bit binary counter circuit 49 is not set, and no sound effect is generated from the speaker 53.

(b) During the game, the pachinko ball enters the winning hole 2 of the accessory 1,
3, 4, 5, or 6, the flying ball enters the right securing prize opening 14, and the right securing switch is instantaneously closed.

When the rights securing switch 15 is closed, the output signal from the Schmitt waveform shaping circuit 27 causes the T flip-flop 29 to go from low to high. This signal is input to an AND circuit 30 and a 4-bit binary counter circuit 31. Since the 4-bit binary counter circuit 31 is reset when the T flip-flop 29 is high, the output signals output from its two output lines are both low, and the NAND circuit 32 outputs a high signal. Therefore, the AND circuit 54 satisfies the conditions that the T flip-flop circuit 29 is high and the NAND circuit 32 is high,
In order to output the clock signal of the output line of the 4-bit binary counter circuit 38,
The pilot lamp 56 flashes to indicate that the rights have been generated and secured. This state of securing rights will be extinguished under the following three conditions.

When the rights reservation switch 15 is closed while the T flip-flop 29 is in the high state.

When the power is turned off.

When the right is exercised a specified number of times.

The extinguishment of the right after exercising the right a predetermined number of times will be described later.

(c) When the right is secured and a pachinko ball flies into either the right prize opening 23 or 24.

The AND circuit 30 outputs a high signal, and the flip-flop circuit 43 changes from low to high.

Since the differentiating circuit 45 outputs a differential signal at the rising edge when the flip-flop circuit 43 changes from low to high, the 4-bit binary counter circuit 38 is reset once and newly receives the clock signal A from the clock circuit 33.
The clock signal shown in FIG. 6 is output.

The 4-bit binary counter circuit 41 is
When the flip-flop circuit 43 is high, the NOT circuit 44 is low, so the reset is canceled and the clock signal shown in FIG. 7 is output. As shown in FIGS. 7 and 8, between the reset signal B output from the AND circuit 46 and the clock signal output from the output line', the rising edge of the clock signal output from the output line' is more temporal. Since it is fast, the flip-flop circuit 47
is set and becomes high when the clock signal from this output line is high. When the flip-flop circuit 47 goes high, the solenoid drive circuit 48 is activated, so that the solenoid 21 is activated and the attacker 20 is opened. At the same time, this high signal is input to the 4-bit binary counter circuit 31, and one exercise of the right is counted.

The 4-bit binary counter circuit 49 is
Since it is set when the flip-flop circuit 47 is high, the clock signal from the AND circuit 39 is output to the resistance dollar waveform synthesis circuit 50, and a sound effect is generated when the solenoid 21 is activated.

The flip-flop circuit 47 is an AND circuit 4
It is reset by the reset signal B output from 6, and changes from high to low after a predetermined time has elapsed, as shown in FIG. As a result, the operation of the solenoid 21 is stopped, the generation of sound effects is stopped, and the flip-flop circuit 43 is also reset by the reset signal B.
The flip-flop circuit 43 goes from high to low, the NOT circuit 44 goes high, the 4-bit binary counter circuit 41 is reset, the output of the clock signal is prohibited, and the first exercise of rights is completed. In this way, the exercise of the right is repeated, and the number of times the right is exercised is counted by the 4-bit binary counter circuit 31. When the number of times the right is exercised reaches 10, the two outputs of the 4-bit binary counter circuit 31 are A state in which both high signals are output from the lines is realized, and the NAND circuit 32 becomes low, so the NOT circuit 37 becomes high, and this is input to the T flip-flop 29 via the OR circuit 35, so the T flip-flop 29 is reset. The value goes from high to low, and the right is extinguished.

As explained above, the present invention has the effect of increasing the player's desire to play because the generated right is secured and the right is then exercised.

Note that the embodiment shows one example of the structure of the present invention, and it is possible to change this as appropriate within the scope of the objective of the present invention.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of the front main part of the pachinko machine according to the present invention, viewed from an oblique side. FIG. 2 is a perspective view of a pachinko machine rights securing switch according to the present invention. FIG. 3 is a perspective view showing the connection relationship between the attacker and the solenoid used in the pachinko machine according to the present invention. FIG. 4 is a block diagram of a circuit used in a pachinko machine according to the present invention. FIG. 5 is a clock signal diagram of a clock circuit applied to the present invention. 6 and 7 show the binary counter circuit 3, respectively.
8 and 41. FIG. FIG. 8 is a signal waveform diagram of the reset signal output from the AND circuit 46. FIG. 9 is a waveform diagram of the output signal output from the flip-flop circuit 47. 14... Rights securing prize opening, 15... Rights securing switch, 23, 24... Rights exercise winning opening, 25,
26... Right exercise switch, 27, 28... Schmitt waveform shaping circuit, 29... T flip-flop, 30... AND circuit, 43... flip-flop circuit, 48... solenoid drive circuit.

Claims (1)

[Scope of Claims] 1. A right-ensuring system that sets a solenoid, which is turned on when a pachinko ball flies into a right-securing winning opening and increases the probability of winning a prize, into a drive ready state to secure the right that increases the probability of winning a prize. When a pachinko ball flies into a winning opening for rights line use that is different from the winning opening for securing rights, and the circuit is turned on when the rights securing circuit is in an on state,
A pachinko machine comprising: a right exercise circuit that drives the solenoid for a predetermined period of time to exercise the secured right.