JPH0640909B2 - Pachinko machine - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention secures a winning right by a pachinko ball jumping into a predetermined prize hole, and a pachinko ball jumps into a prize hole different from the predetermined prize hole. It concerns a pachinko machine that exercises its winning right.

[0002]

2. Description of the Related Art In a pachinko machine, winning conditions during a game change depending on the skill of the player, and the generation of a right advantageous to the player (hereinafter referred to as a right) is one of increasing the player's willingness to play. Has become a requirement.

[0003]

However, when the above right is generated and the player cannot clearly recognize the fact, the right cannot be effectively exercised depending on the contents of the game,
In some cases, this causes a problem of extinguishing the right without the player's knowledge.

Therefore, the present invention has an object to provide a pachinko machine that clearly displays a right when a winning condition is changed during a game and a right advantageous to a player is generated.

[0005]

In order to achieve the above object, the present invention enters an operating state in which the right to increase the winning probability is secured on the basis of the detection of the hitting of a hit ball into the right winning port. A right securing circuit that is in an inoperative state in which the secured state of the right is extinguished based on the detection of a ball hitting the winning slot for securing the right in the operating state, and the right securing circuit in the operating state of the right securing circuit Use of a rights row different from the winning opening The right exercising circuit that activates an electric drive source to open a specific winning opening for a predetermined time based on the detection of a ball hitting the winning opening And a notification unit that operates when in the state.

[0006]

With the above configuration, when the right securing circuit shifts from the inoperative state to the operating state on the basis of the detection of the hitting of the hit ball for the right securing winning hole, the notification means is operated, so that the winning probability increases. It is possible to inform the secured state of the right. Further, when a ball hits the right securing winning opening while the right securing circuit is in the operating state, the right securing circuit shifts from the operating state to the inactive state, so that the informing means in operation stops the operation.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes an accessory used in a pachinko machine according to the present invention.
The winning entrance 2 and the right and left shoulder opening 3, 4 are provided, and the accessory 1
Side wall winning openings 5, 6 are provided on both side walls. The accessory 1 has a distribution port 7, and a distribution plate 8 is provided at the bottom thereof. This distribution plate 8 is inclined from the rear to the front, and each winning opening 2, 3, 4, 5, 6
The pachinko balls 9 and 10 jumping into the distribution port 7 roll in front of the inclined plate 8 while changing their course by a projecting portion 11 projecting from the distribution plate 8.

Partition plates 12, 13 are provided at the front of the distribution plate 8.
Is installed upright, and the space between the partition plates 12 and 12 is a winning hole for securing rights.
The right securing winning opening 14 is provided with a right securing switch 15 having the shape shown in FIG. The function of the right securing switch 15 will be described later. Ordinary winning holes 16 and 17 through which a predetermined number of winning balls are paid out are provided on both sides of the right securing winning hole 14.

Below the accessory 1, an attacker winning hole 18,
19 is provided, and between the attacker winning opening 18 and the attacker winning opening 19 is an attacker 20 as a specific winning opening for picking up a falling pachinko ball. The attacker 20 drives a solenoid 21 as an electric drive source by a solenoid drive circuit 48, which will be described later, to open the attacker 20 and create a state in which a pachinko ball with an increased winning probability easily wins.

As shown in FIG. 3, the attacker 20 is controlled to be opened and closed by a solenoid 21. In FIG. 3, 22 is an attacker control lever mechanism.
At the upper part of the attacker prize holes 18 and 19, the right exercise prize hole 2
3 and 24 are provided facing the attacker winning openings 18 and 19, respectively. The right exercising award winning openings 23 and 24 are provided with right exercising switches 25 and 26, respectively.

As shown in FIG. 4, the right securing switch 15 is connected to a Schmitt waveform shaping circuit 27, and the right exercising switches 25 and 26 are connected to a Schmitt waveform shaping circuit 28. The Schmitt waveform shaping circuits 27 and 28 output high signals when the switches 15, 25 and 26 are closed.

The output signal of the Schmitt waveform shaping circuit 27 is
The signal is input to the T flip-flop circuit 29, and the output signal of the Schmitt waveform shaping circuit 28 is input to the AND circuit 30. When the T flip-flop circuit 29 is set, that is, in the high state,
When a high signal is input from the Schmitt waveform shaping circuit 27, it goes into a low state. The output signal of the T flip-flop circuit 29 is an AND circuit 30 and a 4-bit binary counter circuit 31.
Has been entered in and.

The 4-bit binary counter circuit 31 is
When the T flip-flop circuit 29 is in the high state, it is reset to output a low signal to the NAND circuit 32.

Reference numeral 33 is a clock circuit, and 34 is a power reset circuit. The power reset circuit 34 outputs the clock signal A shown in FIG. Circuit 35 and OR circuit 36
It is designed to output to. The OR circuit 35 includes a reset signal output from the power reset circuit 34 and a knot circuit 37.
The reset signal input from the NAND circuit 32 via
It is designed to output to the flip-flop circuit 29,
The T flip-flop circuit 29 is reset to a low state when at least one of the power reset circuit 34 and the knot circuit 37 is in a high state.

The clock signal A of the clock circuit 33 is input to the 4-bit binary counter circuit 38. Four
The bit binary counter circuit 38 has four output lines, the output lines “A” and “A” are connected to the AND circuit 39, and the output line “C” is connected to the pilot lamp drive circuit 40. The output line “D” is connected to the 4-bit binary counter circuit 41. Each output line "A"
The rectangular signal shown in FIG.

Reference numeral 42 denotes a pilot lamp which is turned on and off, and the pilot lamp driver circuit 40 is intermittently turned on and off by an output signal from the 4-bit binary counter circuit 38, so that it is in a blinking state.

The right securing switch 15, the Schmitt waveform shaping circuit 27, and the T flip-flop circuit 29 are turned on when a pachinko ball hits a predetermined winning opening, and a solenoid 21 for increasing the winning probability is prepared for driving. Set to the state,
The right securing circuit that secures the right to increase the winning probability is roughly composed of the right exercising switches 25 and 26 and the AND circuit 30.
Is when the pachinko ball jumps into a winning opening different from the predetermined winning opening, and when the right securing circuit is in the on state, the solenoid 21 is driven for a predetermined time to secure the secured right. It forms part of the exercise circuit for exercising rights.

The AND circuit 30 is a T flip-flop circuit.
29 is in the high state, and the right exercise switches 25, 26
When at least one of the two is closed, the set signal is output to the flip-flop circuit 43, and the flip-flop circuit 43 is set to the high state. The output signal of the flip-flop circuit 43 is input to the knot circuit 44 and the differentiating circuit 45.

The knot circuit 44 has a function of releasing the reset of the 4-bit binary counter circuit 41,
When the flip-flop circuit 43 is in the low state, the high signal output from the knot circuit 44 resets the 4-bit binary counter circuit 41 so that the 4-bit binary counter circuit 41 outputs the low signal. When the reset circuit 43 is in the high state, this reset is released and the clock signal shown in FIG. 7 is output.

The differentiating circuit 45 is adapted to output a differentiating signal at the rising edge of the flip-flop circuit 43 from low to high. This differentiating signal is input to the 4-bit binary counter circuit 38, and the differentiating signal is inputted. The 4-bit binary counter circuit 38 is reset by.

This 4-bit binary counter circuit 38
The relationship between the clock signal output from the clock signal A and the clock signal A output from the clock circuit 33 will be described with reference to FIGS. 5 and 6. A clock signal having a cycle twice that of the clock signal A is output line "A". From the output line “a”, a clock signal with an 8 times period is output from the output line “c”, and a clock signal with a 16 times period is output from the output line “a”. 4 bit binary counter circuit 38, each time it is reset, the clock signal A immediately after the reset is newly counted again and the clock signal shown in FIG. 6 is repeatedly output.

4-bit binary counter circuits 41 and 4
The relationship with the clock signal output from the bit binary counter circuit 38 will be described below. The 4-bit binary counter circuit 41 has three output lines “o”, “ka”,
The clock signal output from the output line "O" has a double cycle, and the clock signal output from the output line "O" has a double cycle. The clock signal output has a cycle four times as long as the clock signal output from the output line “D”, and the clock signal output from the output line “K” is the clock output from the output line “D”. It has 16 times the period of the signal.

The clock signals output from the output lines “O”, “F”, and “K” are input to the AND circuit 46.
The AND circuit 46 uses the output lines "O", "K", and "K".
When each is high, the reset signal B shown in FIG. 8 is output to the OR circuit 36, and the reset signal B is input to the flip-flop circuit 47 and the flip-flop circuit 43.

The flip-flop circuit 47 is set by the clock signal output from the output line "ki" of the 4-bit binary counter circuit 41, and maintains the high state until the reset signal B is input. The output signal of the flip-flop circuit 47 is input to the solenoid drive circuit 48, the 4-bit binary counter circuit 31 and the 4-bit binary counter circuit 49.

This 4-bit binary counter circuit 49
Is set when the flip-flop circuit 47 is high, and outputs the clock signal input from the AND circuit 39 to the resistance dollar waveform synthesizing circuit 50. The synthesized waveform signal output from the resistor dollar waveform synthesis circuit 50 is input to the voltage variable oscillation circuit 51, and the audio amplification circuit
It is input to 52 and is converted to sound from speaker 53.

Reference numeral 54 denotes an AND circuit. This AND circuit 54
Together with the pilot lamp drive circuit 55 and the pilot lamp 56 constitute an informing means. AND circuit 54
The output signal of the T flip-flop circuit 29, the clock signal from the output line "C" of the 4-bit binary counter circuit 38, and the output signal from the NAND circuit 32 are input to the T flip-flop circuit 29 and the NAND circuit. When circuit 32 is high, in other words, when the right is reserved, 4
The clock signal from the output line “C” of the bit binary counter circuit is output to the pilot lamp drive circuit 55. As a result, the pilot lamp drive circuit 55 repeats the extinguishing of the lighting, so that the pilot lamp 56 is notified of the secured state of the right to increase the winning probability.

Next, the operation will be described.

(B) Turn on the power supply.

When the power is turned on, a reset signal is output to the OR circuit 35 and the OR circuit 36, and this reset signal is output to the T flip-flop circuit 29 and the flip-flop circuit 43.
Is input to the flip-flop circuit 47. Then,
T flip-flop circuit 29, flip-flop circuit 43,
The flip-flop circuit 47 becomes low. Since the flip-flop circuit 43 is in the low state, the knot circuit 44 is in the high state, and the 4-bit binary counter circuit 41
Is reset and the output of the clock signal is prohibited.

When the power is turned on, the clock circuit 33 outputs the clock signal A, which is input to the 4-bit binary counter circuit 38. The clock signal output from the output line "C" of the 4-bit binary counter circuit 38 is the pilot lamp drive circuit 40.
The pilot lamp 42 blinks when the power is turned on.

The AND circuit 54 has the 4-bit binary counter circuit 38 because the T flip-flop circuit 29 is in the low state regardless of whether the NAND circuit 32 is in the high or low state.
Do not output the clock signal output from the output line “C” to the pilot lamp drive circuit 55. Therefore, the pilot lamp 56 is off.

The solenoid 21 includes a flip-flop circuit 47.
Is not driven because it is in the low state, the attacker 20 is in the closed state, and the 4-bit binary counter circuit 49 is
Since the flip-flop circuit 47 is in the low state,
It is not set and no sound effect is produced from the speaker 53.

(B) A pachinko ball jumps into one of the winning holes 2, 3, 4, 5, 6 of the accessory 1 during the game, and the jumping ball enters the right securing winning hole 14 When the securing switch is momentarily closed.

When the right securing switch 15 is closed, the Schmitt waveform shaping circuit 27 based on the closing of the right securing switch 15
The output signal from the T flip-flop circuit 29 changes from low to high. This signal is input to the AND circuit 30 and the 4-bit binary counter circuit 31.

The 4-bit binary counter circuit 31 is
Since the T flip-flop circuit 29 is reset when it is high, the output signals output from the two output lines thereof are both low, and the NAND circuit 32 outputs a high signal. , The T flip-flop circuit 29 is high and the NAND circuit 32 satisfies the high condition, the clock signal of the output line "C" of the 4-bit binary counter circuit 38 is output, and the pilot lamp 56 blinks. Then, it is displayed that the right has been generated and secured.

The state of securing the right disappears under the following three conditions.

When the right securing switch 15 is closed while the aT flip-flop circuit 29 is in the high state.

When the right to increase the winning probability is secured, the T flip-flop circuit 29 is in the high state and is in the operating state. At this time, if a hit ball jumps into the right securing winning opening 14 and the right securing switch 15 is closed, the T flip-flop circuit 29 is reset based on the closing of the right securing switch 15, and the high state is changed to the low state. , The right secured state disappears by shifting from the operating state to the inactive state.
As described above, the T flip-flop circuit 29 alternately repeats setting and resetting each time one ball is hit,
Securing and extinguishing rights are reversed. Therefore, when the player exercises the right, the right exercising winning holes 23 and 24 are aimed and hit so as not to jump into the right ensuring winning opening 14. Therefore, it is possible to enhance the interest of the player in two stages of securing the right and exercising the secured right without extinguishing it, and to impart the game change to the player.

B When the power is turned off.

C When the right is exercised a predetermined number of times.
The extinction of the right when the right is exercised a predetermined number of times will be described later.

(C) When the right is secured and the pachinko ball has jumped into either one of the right exercising winning holes 23 and 24.

The AND circuit 30 outputs a high signal, and the flip-flop circuit 43 changes from low to high.

The differentiating circuit 45 is a flip-flop circuit.
Since the differential signal is output at the rising edge of 43 when it goes from low to high, the 4-bit binary counter circuit 38
Is reset once, the clock signal A from the clock circuit 33 is newly counted, and the clock signal shown in FIG. 6 is output.

The 4-bit binary counter circuit 41 is
Since the knot circuit 44 becomes low when the flip-flop circuit 43 is high, the reset is released and the clock signal shown in FIG. 7 is output. AND circuit as shown in FIG. 7 and FIG.
Since the rising edge of the clock signal output from the output line "ki" is earlier in time between the reset signal B output from 46 and the clock signal output from the output line "ki", the flip-flop circuit 47 , It is set and becomes high when the clock signal from this output line "ki" is high.

When the flip-flop circuit 47 becomes high,
Since the solenoid drive circuit 48 is driven, the solenoid
21 is activated, the attacker 20 is opened, the high signal is input to the 4-bit binary counter circuit 31, and it is counted that the exercise of right has been performed once.

The 4-bit binary counter circuit 49 is
Since the flip-flop circuit 47 is set when it is high, the clock signal from the AND circuit 39 is output to the resistance dollar waveform synthesizing circuit 50, and the sound effect is generated together with the operation of the solenoid 21.

The flip-flop circuit 47 is an AND circuit 46.
Is reset by the reset signal B output from
As shown in FIG. 9, it goes from high to low after a lapse of a predetermined time. As a result, the operation of the solenoid 21 is stopped, the generation of the sound effect is stopped, and the flip-flop circuit is stopped.
Since 43 is also reset by the reset signal B, the flip-flop circuit 43 changes from high to low and the knot circuit
44 becomes high and 4-bit binary counter circuit 41
Is reset, the output of the clock signal is prohibited, and the first exercise of the right ends.

In this way, the exercise of the right is repeated, the number of times of the exercise of the right is counted by the 4-bit binary counter circuit 31, and when the number of times reaches 10, the two bits of the 4-bit binary counter circuit 31 are counted. Since the high signal is output together from the output line and the NAND circuit 32 becomes low, the knot circuit 37 becomes high, which is the T flip-flop circuit via the OR circuit 35.
Entered in 29. As a result, the T flip-flop circuit 29
Is reset and the right disappears from high to low, while the AND circuit 54 outputs a low level regardless of the clock signal of the output line "C" of the 4-bit binary counter circuit 38. Therefore, the pilot lamp 56 is turned off, and the disappearance of the right that is generated and secured is displayed.

The embodiment shows one structural example of the present invention, and can be appropriately modified within the scope of the object of the present invention.

[0051]

As described above, according to the present invention, since the notification means informs that the right securing circuit is in the operating state, it is possible to notify the right secured state in which the winning probability increases.
As a result, not only can the player feel a sense of accomplishment of the game when the right is secured, but the player can clearly recognize the right secured state and the disappearance of the right secured state. It can be used effectively.

[Brief description of drawings]

FIG. 1 is a perspective view of an accessory used in a pachinko machine according to the present invention.

FIG. 2 is a perspective view of a right securing switch of a pachinko machine according to the present invention.

FIG. 3 is a perspective view showing a connection relationship between an attacker and a solenoid used in the pachinko machine according to the present invention.

FIG. 4 is a block diagram of a circuit used in the pachinko machine according to the present invention.

5 is a clock signal diagram of the clock circuit shown in FIG.

6 is a signal waveform diagram of a clock signal output from the binary counter circuit shown in FIG.

7 is a signal waveform diagram of a clock signal output from the binary counter circuit to which the clock signal shown in FIG. 6 is input.

8 is a signal waveform diagram of a reset signal output from the AND circuit to which the clock signal shown in FIG. 7 is input.

9 is a waveform diagram of an output signal output from the flip-flop circuit set by the clock signal shown in FIG. 14 Right guarantee winning hole 15 Right securing switch 23, 24 Right exercising winning hole 25, 26 Right exercising switch 27, 28 Schmitt waveform shaping circuit 29 T flip-flop circuit 30 AND circuit 43 Flip-flop circuit 48 Solenoid drive circuit 54 AND circuit Means) 55 Pilot lamp drive circuit (informing means) 56 Pilot lamp (informing means)

Front page continuation (72) Inventor Misao Hojima 2-8-5 Nishiki-cho, Kiryu-shi, Gunma Prefecture (72) Inventor Toshio Oda 3-30-12 Nakano Nakano-ku, Tokyo Condominium Soleuyu Room 509 (72) Inventor Kanda Masao 1-9-13 Hamamatsu-cho, Kiryu-shi, Gunma Prefecture (72) Inventor Hitoshi Morita Ohma-machi, Yamada-gun, Gunma Prefecture 45-3 Oma (72) Sadayuki Takahashi 1-487-4 Aioi-cho, Kiryu-shi Gunma Prefecture (72) ) Inventor Momojiro Kanai 5-21 Orihime-cho, Kiryu-shi Gunma (72) Inventor Reiji Fujita 6-8-6 Higashi Kiryu-shi, Gunma (72) Inventor Tadashi Roppongi 1241-5 Kurokawa Hiromachi, Kiryu-shi Gunma ) Inventor Kiyoshi Otani 762-Kirihara, Omama-cho, Yamada-gun, Gunma Prefecture (72) Inventor, Jiro Hayashi, 713-1 Aramaki-machi, Maebashi, Gunma Prefecture

Claims (1)

[Claims] 1. An operating state for securing the right to increase the winning probability based on the detection of the entry of a hit ball into the right securing winning opening, and the operating state is brought into the operating state where the hitting ball enters the right securing winning opening. Based on the detection of the right, the right securing circuit that goes into an inoperable state for extinguishing the secured state of the right, and the hitting ball to the winning row for use of the right row different from the right securing winning opening in the operating state of the right securing circuit. It has a right exercising circuit that operates an electric drive source for opening a specific winning opening for a predetermined time based on the detection of a winning, and an informing means that operates when the right securing circuit is in an operating state. Pachinko machine to be.