JPH0234490B2 - - Google Patents

Description

Detailed Description of the Invention The present invention is mainly used in an A/D converter etc. realized on a semiconductor integrated circuit with a complementary insulated gate configuration, and compares two voltages with a small difference and calculates the voltage according to the magnitude of the difference. The present invention relates to a voltage comparison circuit suitable for outputting a logic voltage.

Conventional voltage comparator circuits used in semiconductor integrated circuits with complementary insulated gate configurations are configured with M1 as a constant current source, M2 and M3 as input transistors, and M4 and M5 as current mirror loads, as shown in Figure 1. The terminals 2 and 3 are
A two-stage amplifier circuit was used in which an output voltage proportional to the difference between the voltages applied to the terminal 6 was taken out from the terminal 6, and this was further amplified by an inverting amplifier 11 with M6 as a constant current load.

Symbols used in this application, including FIG. 1, define an n-channel transistor as shown in FIG. 2a, and a p-channel transistor as shown in FIG. 2b. The gate is denoted by G, the source is denoted by S, and the drain is denoted by D. This 2
A stage-structured amplifier circuit usually provides a gain of 2,000 to 5,000 times, but in order to obtain a gain margin, one stage of inverting amplifier 12 consisting of transistors M8 and M9 is usually added. 13 is the above M1 and M
This is a bias voltage supply circuit for operating 6 in a constant current region.

In such a voltage comparator circuit, when the input voltage decreases, the number of amplification stages must be increased accordingly, resulting in an increase in the area occupied in the integrated circuit and an increase in power consumption. Furthermore, the common-mode voltage rejection of the first-stage differential amplifier is not perfect, and when the common-mode component of the input voltage changes, the output voltage at node 6 changes, and this voltage is amplified by the inverting amplifier, so the input voltage is
In the case of a voltage difference of less than mV, depending on the common mode voltage, the final stage output may be in a logic “1” state or a logic “0” state.
The state of may change. The same phenomenon also occurs when the power supply voltage fluctuates. Therefore, in such a voltage comparison circuit, it is difficult to compare voltages of 1 mV or less when the common mode voltage of the input voltage changes significantly or when there is a lot of noise in the power supply. More importantly, the differential amplifier 10
It is very difficult to match the operating center voltage of the inverting amplifier 11 with the operating center voltage of the inverting amplifier 11, and with current technology, it is normal for them to deviate by several hundred mV;
This is the internal and external input offset voltage. This cannot be controlled with current technology. Therefore, when comparing voltages, it is necessary to compare voltages that include offsets.
This method has the disadvantage that it is not possible to compare true voltage differences.

As another voltage comparison method, for example, there is a circuit as shown in Fig. 3, which was presented at the ISSCC by Deingwall in 1979. ('79 ISSCC Digest of
Technical papers pp 126) The details of the operation of this circuit are described in the above-mentioned document and will be omitted here. In this circuit, the input voltage from terminals 102 and 103 in the figure is applied to transistors M10, M11 or M1.
2 and M13, which conduct alternately, to one electrode of the accumulator C1, the other electrode of the accumulator being connected to the input terminal of an inverting amplifier constituted by the transistors M14 and M15. The input terminal and output terminal of this inverting amplifier are made conductive and non-conductive in synchronization with the switch. In the figure, φ and are mutually complementary clocks. For example, when the switch connected to the input terminal 103 is conductive, the switch consisting of transistors M116 and M17 connected between the input terminal 105 and the output terminal 106 of the inverting amplifier is also conductive, and the potential of the terminals 105 and 106 is changed. Equal potential. Next, when the switch connected to the input terminal 102 side is made conductive and the other two switches are made non-conductive, the potential at the terminal 104 changes by the difference between the voltage at the terminal 102 and the voltage at the terminal 103. This change is C1
to the inverting amplifier through the output 106.
This change is multiplied several dozen times and output. The voltage difference between terminals 102 and 103 is therefore amplified. Although this circuit seems simple,
The size of the capacitor C1 needs to be several times larger than the size of the inverting amplifier. Further, the gain of the inverting amplifier is several tens of times at most, and if the input voltage difference is less than 1 mV, the output voltage is not sufficient to operate the logic circuit, so the latch 107 also requires a considerable amount of amplification. Furthermore, since the time at which the voltage at the terminal 103 is sampled and the time at which the voltage at the terminal 102 is sampled are different, if the power supply voltage fluctuates at both times, that voltage is treated equally as the signal input voltage. Therefore, it has the disadvantage of being extremely susceptible to power supply noise.

The present invention aims to eliminate such drawbacks and realize a voltage comparator circuit with very high sensitivity using a small number of elements.

The present invention provides a first flip-flop constituted by a pair of cross-coupled first and second field effect transistors of one conductivity type, and a first flip-flop having a common source and drain with the transistors constituting this flip-flop. The third and fourth field effect transistors have the same polarity as the flip-flop, and the first field effect transistor has a different polarity from the first flip-flop.
a second flip-flop constituted by a pair of cross-coupled fifth and sixth field effect transistors; and a second flip-flop having a common source and drain with the fifth and sixth transistors constituting the second flip-flop. comprising ninth and tenth field effect transistors having the same polarity as and means for generating a pulse, the gate electrodes of the seventh, eighth, ninth and tenth transistors being connected to the means for generating the pulse; The voltage comparison circuit is characterized in that the gate electrodes of the third and fourth transistors are used as signal input terminals, and the drain electrodes of the ninth and tenth transistors are used as output terminals.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments. FIG. 4 is a circuit diagram showing one embodiment of the present invention. This circuit consists of a flip-flop composed of n-channel MOS transistors T1 and T2, and an n-channel MOS transistor T3, which is connected in parallel to each transistor.
T4, p-channel MOS transistor T5,
A flip-flop composed of T6 and T
p-channel MOS transistors T7 and T8 connected in parallel to 5 and T6, respectively, and T1 and T2.
This is achieved by connecting the drain electrodes of T5 and T6 with n-channel transistors T9 and T10. The gate electrodes of T7, T8, T9, and T10 are connected to a pulse generation source as a terminal 208. The voltages to be compared are applied to the gate electrodes 202 and 203 of T3 and T4. Also, in this circuit, terminal 2
01 is connected to the positive power supply VDD, and the terminal 209 is grounded.

This circuit initially starts with a pulse voltage of zero. When the power supply voltage is 5V and the threshold voltage of the n-channel transistor is 0.8V, the input voltage is preferably 1V below the threshold voltage of T3 and T4.
The higher the degree, the faster the circuit can operate. This condition will be explained below. T3, T4
are conductive, so the voltage at nodes 204 and 205 is zero, T9 and T10 are non-conductive, and T7 and T8 are conductive, so the potential at terminals 206 and 207 is equal to the voltage V _DD at power supply terminal 201. Next, when a positive pulse is applied to the terminal 208, T9 and T10 become conductive.
T7 and T8 become non-conductive, and current flows into the flip-flops T1 and T2 through T9 and T10. If the potential of terminal 202 is higher than 203 at this time, the current flowing through transistor T3 is greater than the current flowing through transistor T4. No current flows through T1 and T2 until the potential at node 205 or 204 exceeds the threshold voltage, respectively. T9, T1
At the initial stage when 0 becomes conductive, nodes 204 and 205 are charged in the same way, but since node 204 has a larger amount of discharge, node 205 exceeds the threshold voltage first. Then, T1 also starts discharging, and node 204
The potential of does not rise. Therefore, the potential at node 205 continues to rise. Therefore, the current flowing through T9 is greater than the current flowing through T10. Then, since the potential of the terminal 206 becomes lower than the potential of the terminal 207, the flip-flop formed by T5 and T6 also operates, and the potential of the terminal 206 rapidly decreases. In this way, the state of the output voltage is determined according to the input voltage. Since its operation consists of a double flip-flop, the time required for the state to be determined has a channel length of about 6 microns.
Even if MOS transistors are used, the speed can be increased to 20 ns or less. Furthermore, since the arrangement is completely symmetrical from input to output, the cause of offset voltage, which is a drawback in conventional circuits, can be eliminated. Furthermore, since power supply noise is applied equally to both input voltages, it is canceled and there is no risk of malfunction due to noise. Further, since positive feedback is provided by the flip-flop, the gain is infinite, and even if the input voltage is 1 mV or less, a voltage output sufficient for the logic amplitude can be obtained as an output.

Returning to the initial state returns the pulse to zero. Then, T9 and T10 become non-conductive, and T7,
T8 is conductive. The charges at nodes 204 and 205 are then rapidly discharged through T3 and T4, respectively, while nodes 206 and 207 are rapidly charged through T7 and T8, respectively, to the supply voltage V _DD
Return to With the circuit configuration of the present invention, this recovery time can easily be reduced to 10 ns or less.

This circuit does not consume current in its initial state. Further, even during the comparison operation, only a very small amount of current is consumed, and the power consumption is advantageously less than 1/10 of that of the conventional circuit.

In the case described above, the input voltage according to the present invention is preferably lower than the threshold voltages of T3 and T4.
Performance is best when the voltage is around 1V. A normal differential amplifier circuit is sufficient as a circuit that can meet this condition over a wide input range. An example is shown in FIG. FIG. 5 shows a circuit B according to the present invention in which a conventional differential amplifier circuit A is added.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a comparator circuit that combines a differential amplifier 10 and inverting amplifiers 11 and 12 according to the prior art. FIG. 2a shows an n-channel transistor, and FIG. 2b shows a p-channel transistor. FIG. 3 is a diagram showing another prior art comparator using an inverting amplifier and a transfer gate as a switch. FIG. 4 is a diagram showing a basic circuit of an embodiment of the present invention. FIG. 5 is a diagram showing an example of a circuit in which a differential amplifier is combined with the present invention to expand the input voltage range. M1 to M17, T1 to T10...MOS transistors.

Claims (1)

[Claims] 1. A first flip-flop composed of a pair of cross-coupled first and second field effect transistors of one conductivity type, and a source and a drain common to the first and second transistors constituting this flip-flop. A third and fourth field effect transistor having the same polarity as the first flip-flop, and a pair of cross-coupled fifth and sixth field effect transistors having a different polarity from the first flip-flop. a second flip-flop, and seventh and eighth field effect transistors having a common source and drain with the fifth and sixth transistors constituting the second flip-flop and having the same polarity as the second flip-flop;
A pair of drain electrodes of the first flip-flop and a pair of drain electrodes of the second flip-flop.
Ninth and tenth field effect transistors having the same polarity as the first flip-flop, each of which uses the pair of drain electrodes of the flip-flop as a source electrode and a drain electrode, respectively, and means for generating a pulse; The gate electrodes of the ninth and tenth transistors are connected to the pulse generating means, the gate electrodes of the third and fourth transistors are used as signal input terminals, and the drain electrodes of the ninth and tenth transistors are connected to the means for generating the pulse. A voltage comparison circuit characterized by having an output terminal.