JPH0234551B2 - - Google Patents

Abstract

PURPOSE:To decrease distortion received from a transmission line by decreasing the amplitude ratio of a modulated carrier band signal. CONSTITUTION:A transmission differential logical circuit 11 applies a 4-phase transmission differential conversion to input signals S11,S12 to output a (p) signal D1 and a (q) signal D2, and a transmission logic converting section 12 converts a (p) signal (S21,S31,S41).(q) signal (S22,S32,S42) into a TCONT.(p) signal (S'21,S'31,S'41).(q) signal (S'22,S'32,S'42).(p) signal H1.(q) signal H2l. Then a trans mission path selection section 13 outputs (p-) signal (S21-).(q) signal (S22-) or (p) signal (S'21-).(q) signal (S'22-) for selection, and a code conversion section 14 outputs (p) signal E1.(q) signal E2. Then a code conversion section 15 outputs a (p) signal (D1-D3D'3E4) or a (q) signal (D1-D3D'3E4) and a D-A converting section 16 converts them into a multi-value signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modulation/demodulation device, and particularly to a modulation/demodulation device using a multilevel orthogonal amplitude modulation method.

[Conventional technology]

The multilevel orthogonal amplitude modulation method is used for large-capacity digital wireless communication because the amount of information transmitted per unit frequency of the exclusive frequency width of the carrier band is large and radio waves can be used effectively in wireless transmission.

A conventional multilevel orthogonal amplitude modulation method will be explained with reference to the drawings.

FIG. 3 is an explanatory diagram showing the arrangement of signal points in the multilevel orthogonal amplitude modulation method, and shows signal points in the first quadrant on the signal plane in the case of 256 values.

In the conventional 256-value orthogonal amplitude modulation method, the input p signal and the input q signal, each of which is a ⁴ -digit binary code, are divided into 24 signals from -15k to 15k with an interval of 2k (k is a positive constant). (=16) p coordinates and q
correspond to each one of the coordinates. A total of 64 signal points marked with black circles and white circles in FIG. 3 indicate 1/4 of the 22 ^×4 (=256) signal points created in this way. Since the outermost point of the signal point group is a square, the conventional multi-level orthogonal amplitude modulation method will be referred to as a square multi-value orthogonal amplitude modulation method.

Since the amplitude of the modulated carrier band signal is proportional to the distance from the origin of the signal plane to the signal point, it is
In the 256-value orthogonal amplitude modulation method, the ratio R between the maximum value and the minimum value of the amplitude is √2×15 ² /√2×1 ² =15. Generally, R in the square 2 ²ⁿ value orthogonal amplitude modulation system is (2 ⁿ -1), which is a large value.

The transmission path from the modulator to the demodulator has transmission distortion that depends on the amplitude, and the larger the value of R, the greater this distortion.

As explained above, the conventional square multi-value orthogonal amplitude modulation method has the drawback that distortion is large in the transmission path.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention, or in other words, the purpose of the present invention is to solve the above-mentioned drawbacks and to provide a modulation/demodulation device using a multilevel orthogonal amplitude modulation method in which R is small and distortion caused in a transmission path is small. be.

[Means for solving problems]

The modem and modem of the present invention each have n (n is 3
The first input p is a binary code of (natural number) digits
Some of the signal points of a square multilevel orthogonal amplitude modulation system in which the signal and the input q signal each correspond to one of ²ⁿ coordinates equally spaced in the p-axis and q-axis directions that are orthogonal to each other on the signal plane A modulator and a demodulator that use a circular multilevel orthogonal amplitude modulation method in which the distance between two adjacent signal points is always constant by changing the position of the signal point group, and the outermost point of the signal point group is arranged close to a circle. In the modulation/demodulation device comprising: the modulator, the position of the signal point of the square multi-value quadrature amplitude modulation method corresponding to the first input p signal and q signal is set to the position of the signal point of the square multi-value quadrature amplitude modulation method, Determine whether or not a change is required and output the first determination result, and if the change is required, the first input p of the digit whose sign is changed in accordance with any of the changes.
A second input p signal and an input q signal consisting of the signs of the signal and the input q signal are logically converted to obtain a third input signal, each of which is a binary code having the same number of digits as the second input p signal and input q signal. When outputting an input p signal and an input q signal and a fourth input p signal and input q signal, each of which is a binary code of at least one digit, and when the above change is not required, the sign of all digits of each is a value " Said fourth input p which takes 0''
a transmission logic converter that outputs a signal and an input q signal; and a transmission logic converter that outputs the second input p signal and input q signal or the third input p signal and input q based on the first determination result of the transmission logic converter. a transmission route selection unit that selects and outputs one of the signals;
a fifth input p signal or input q signal consisting of the sign of the first input p signal or input q signal whose sign is not changed by any of the changes; The second or third input p signal or input q signal and the fourth input p signal or input q signal are input, and the sign of all digits of the fourth input p signal or input q signal is a value "0", one of ²ⁿ values are equally spaced from each other, and when the sign of any digit of the fourth input p signal or input q signal takes the value "1", the values are equally spaced from each other. Two ^{D-A converters output a multi-value signal P or a multi-value signal Q that takes one of the values exceeding 2 n} , and the multi-value signal P and the multi-value signal Q are inputted and the orthogonal amplitude is calculated. an orthogonal modulation circuit that outputs a modulated wave; A first output p signal or output q signal corresponding to the fifth input p signal or input q signal, and a second output signal Q corresponding to the second or third input p signal or input q signal. two A-D converters that output an output p signal or an output q signal and a third output p signal or output q signal corresponding to the fourth input p signal or input q signal; and the third output p signal and output q signal are input, and the sign of all digits of each of the third output p signal and output q signal is the value "0". If not, logically converts the second output p signal and output q signal and the third output p signal and output q signal to output the second determination result. a reception logic conversion section that outputs a fourth output p signal and an output q signal, each of which is a binary code having the same number of digits as the output p signal and output q signal; and the second determination of the reception logic conversion section. Based on the result, the second output p signal and the output q
and a receiving path selection section that selects and outputs either the signal or the fourth output p signal and the fourth output q signal.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

_{FIGS .} 1 _and 2 are block diagrams showing a modulator _/ demodulator constituting an embodiment of _the modulation/demodulation device of the present _{invention .} S ₄₂ ) represents a four-digit binary code, and represents an exclusive OR circuit (hereinafter referred to as an EX-OR circuit).

The modulator shown in FIG. 1 has a p signal S ₁₁ and a q signal S ₁₂
a transmission differential logic circuit 11 that inputs a signal, performs four-phase transmission differential conversion, and outputs a p signal D ₁ and a q signal D ₁ (the upper of the two signals D ₁ is defined as the p signal D ₁ ); P signal (S ₂₁ S ₃₁ S ₄₁ )/Q signal (S ₂₂ S ₃₂ S ₄₂ ) input signal
A transmission logic converter 12 that outputs TCONT, p signal (S ₂₁ ′S ₃₁ ′S ₄₁ ′), q signal (S ₂₂ ′S ₃₂ ′S ₄₂ ′), p signal H ₁ , and q signal H ₂ ; Signal (S ₂₁ S ₃₁ S ₄₁ )・q
Input the signal (S ₂₂ S ₃₂ S ₄₂ ), p signal (S ₂₁ ′S ₃₁ ′S ₄₁ ′), q signal (S ₂₂ ′S ₃₂ ′S ₄₂ ′), and signal TCONT, and input the p signal (S ₂₁ S ₃₁ S ₄₁ )/q signal (S ₂₂ S ₃₂ S ₄₂ ) or p signal (S ₂₁ ′S ₃₁ ′S ₄₁ )/q signal (S ₂₂ ′S ₃₂ ′S ₄₂ ′) A selection section 13;
It is composed of 13 EO circuits and 4 AND circuits, and inputs the p signal _D1 , q signal _D1 , the output of the transmission path selection section 13, and the p signal _H1 , q signal _H2, and generates the p signal _D1.・
q signal D ₁ and p each being a 3-digit binary code
A code converter 14 outputting the signal/q signal and the p signal _E4 /q signal _E4 , and each of the three EX-
The p signal D ₁ or q signal D ₁ is composed of an OR circuit, the p signal or q signal which is the output of the code converter 14 and is a 3-digit binary code, and the p signal E ₄ or the q signal
Two code converters 15 input the signal _E4 and output the p signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ) or the q signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ), and the NOT Circuit 161 and EX-OR circuit 162
and a D-A conversion circuit 163, and outputs a p signal (D ₁ D ₂ D ₃ D ₃ 'E ₄ ) or a q signal (D ₁ D ₂ D ₃ D ₃ 'E ₄ ).
It is configured to include two DA converters 16 that input a signal P or a signal Q that is a multilevel signal, and an orthogonal modulation circuit (not shown).

The demodulator shown in FIG. 2 includes a quadrature detection circuit (not shown) that outputs a signal P and a signal Q, and a p signal (D ₁ D ₂ D ₃ D ₃ 'E ₄ )
Alternatively, two A-D converter circuits 26 outputting the q signal (D ₁ D ₂ D ₃ D ₃ 'E ₄ ) and three EX-
It is composed of an OR circuit, and inputs the p signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ) or the q signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ), and generates the p signal or the 5-digit binary code. The two code conversion units 25 that output the q signal and the p signal and q signal output from the two code conversion units 25 are input, and the p signal D ₁ and the q signal are input.
a code conversion unit 24 that outputs D ₁ , p signal (S ₂₁ ″S ₃₁ ″S ₄₁ ″), q signal (S ₂₂ ″S ₃₂ ″S ₄₂ ″), and p signal H ₁ and q signal H ₂ ; p signal (S ₂₁ ″S ₃₂ ″S ₄₂ ″)・
Reception that inputs the q signal (S ₂₂ ″S ₃₂ ″S ₄₂ ″) and the p signal H ₁ and q signal H ₂ and outputs the signal RCONT and the p signal and q signal, each of which is a 3-digit binary code. The logic converter 22, the p signal (S ₂₁ ″S ₃₁ ″S ₄₁ ″), the q signal (S ₂₂ ″S ₃₂ ″S ₄₂ ″), the p signal, the q signal that is the output of the reception logic converter 22, and the signal RCONT and outputs the p signal (S ₂₁ ″S ₃₁ ″S ₄₁ ) and q signal (S ₂₂ ″S ₃₂ ″SD ₄₂ ″), or the p signal and q signal that are the output of the reception logic converter 22. A transmission route selection unit 23 that outputs
and a reception differential logic circuit 21 which inputs the p signal _D1 and the q signal _D1 , performs four-phase reception differential conversion, and outputs the resultant signal.

The embodiment shown in FIGS. 1 and 2 uses a circular 256-value orthogonal amplitude modulation method.

To explain the arrangement of signal points in this method with reference to FIG. 3, in the first quadrant of the signal plane, there are signal points a, b, and c, which are part of the signal points of the square 256-value orthogonal amplitude modulation method.・d・e・f as signal points a′・b′・
Convert to c′, d′, e′, f′ and make the same changes in the second, third, and fourth quadrants to make the outermost point of the signal point group circular. That is, the 64 signal points marked with black circles and triangles represent the first quadrant of the signal point arrangement of this method. In this signal point arrangement, the ratio R between the maximum value and the minimum value of the carrier band signal amplitude is √157, which is approximately R in the square 256-value orthogonal amplitude modulation method.
It has become 0.84 times.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained.

At the beginning of the explanation of the operation of the modulator shown in FIG.
The operation of the converter 16 will be explained.

_The D _- A conversion circuit 163 converts the value k [ _{( -1} ) _D1 ^・2 ³ +
(-1) ^D2・2 ² +(-1) ^D3・2 ¹ +(-1) ^D3 '・2 ¹ +
(−
1) Since it is configured to output signal P or signal Q, which is a multilevel signal having ^D4・²⁰ ],
The D-A converter 16 converts the input signal (D ₁ D ₂ D ₃ D ₃ 'E ₄ ) into a value k [(-1) ^D1 2 ³ + (-1) ^D2 2 ² + (-1
)
^D3・2 ¹ + (−1) ^D3 ′・2 ¹ + (−1) ^(D3 ′ ^E4)・2 ⁰ ] ( ₃ ′ is the polarity inversion value of D ₃ ′) , represents an exclusive OR operation).
Therefore, when E ₄ = 0, the input signal (D ₁ D ₂ D ₃ D ₃ ′) has a magnitude relationship that is opposite to that of the binary number (D ₁ D ₂ D ₃ D ₃ ′). Outputs one of 16 values with an interval of “2k”. When the input signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ) is (00000), the output is “15k”, and when it is (11110), the output is “−15k”.
It is. (00001), the output is “17k”,
(11111), it becomes “-17”.

Now, the input signal p of the modulator shown in FIG.
The signal point corresponding to the signal (S ₁₁ S ₂₁ S ₃₁ S ₄₁ ) and the q signal (S ₁₂ S ₂₂ S ₃₃ S ₄₄ ) is one of the black circles in Figure 3 (the second
), the transmission logic converter 12 detects this and converts the signal TCONT to a logic value of "0". , p whose value is “0”
Outputs signal _H1 and q signal _H2 . The transmission path selection unit 13 selects and outputs the p signal (S ₂₁ S ₃₁ S ₄₁ ) and the q signal (S ₂₂ S ₃₂ S ₄₂ ) when the value of the signal TCONT is a logical value “0”. The code converter 14 and the two code converters 15 work together to rotationally symmetrically transform the p signal (S ₂₁ S ₃₁ S ₄₁ S ₄₁ H ₁ ) and the q signal (S ₂₂ S ₃₂ S ₄₂ H ₂ ). One code converter 15 outputs the p signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ), and the other code converter 15
outputs a q signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ) (E ₄ =0 in this case). The outputs of the two code converters 15 are subjected to D/A conversion by the two D/A converters 16 to become the signal P and the signal Q, as described above. The orthogonal modulation circuit amplitude-modulates two carrier waves having the same frequency and being orthogonal to each other, one with a signal P and the other with a signal Q, and synthesizes them into a carrier band signal (this part is not shown). p signal (S ₂₁ S ₃₁ S ₄₁ H ₁ )・q
Since the signal (S ₂₂ S ₃₂ S ₄₂ H ₂ ) has been rotationally symmetrically transformed by the code converter 14 and the two code converters 15, the p Signal (S ₂₁ S ₃₁ S ₄₁ H ₁ ), q signal (S ₂₂ S ₃₂ S ₄₂ H ₂ ) and the position of this signal point rotated by π/2, π or 3π/2 around the origin of the signal plane. p signal corresponding to the signal point (S ₂₁ S ₃₁ S ₄₁ H ₁・
It matches the q signal (S ₂₂ S ₃₂ S ₄₂ H ₂ ). Therefore, the codes of the second and subsequent digits of each of the p signal (S ₁₁ S ₂₁ S ₃₁ S ₄₁ ) and q signal (S ₁₂ S ₂₂ S ₃₂ S ₄₂ ) are affected by the four-phase phase uncertainty during reception demodulation. The signal points are arranged so that they are not affected by the signal. S ₁₁ and S ₁₂ are not affected by the four-phase phase uncertainty due to the action of the transmission differential logic circuit 11.

When the signal point corresponding to the p signal (S ₁₁ S ₂₁ S ₃₁ S ₄₁ )/q signal (S ₁₂ S ₂₂ S ₃₂ S ₄₂ ) is one of the triangle marks in FIG. detects this and outputs a signal that takes a logical value of “1”.
Outputs TCONT and also p signal (S ₂₁ S ₃₁ S ₄₁ )・q
The signal (S ₂₂ S ₃₂ S ₄₂ ) is logically converted and the p signal (S ₂₁ ′S ₃₁ ′S ₄₁ ′), q signal (S ₂₂ ′S ₃₂ ′S ₄₂ ′) and p
signal
Outputs H ₁ and q signal H ₂ . FIG. 4 shows the truth table of this logic conversion at signal point a and shown in FIG.
b, c, d, e, f as signal points a', b', c', d',
This example shows the case of changing to e′ and f′. One of the p signal _H1 and the q signal _H2 becomes "0" and the other becomes "1". The transmission path selection unit 13 selects p when the value of the signal TCONT is a logical value “1”.
Signal (S ₂₁ ′S ₃₁ ′S ₄₁ ′)・q signal (S ₂₂ ′S ₃₂ ′S ₄₂ ′)
Select and output. The code converter 14, the two code converters 15, and the two DA converters 16 operate in the same manner as already described. In this case, the codes of the second and subsequent digits of each of the p signal (S ₁₁ S ₂₁ S ₃₁ S ₄₁ ) and q signal (S ₁₂ S ₂₂ S ₃₂ S ₄₂ ) are affected by the four-phase phase uncertainty during reception demodulation. The signal point arrangement is such that it is not affected by

Next, the operation of the demodulator shown in FIG. 2 will be explained.

The carrier band signal is subjected to orthogonal synchronous detection by an orthogonal detection circuit and becomes a signal P and a signal Q (this part is not shown). The A-D conversion circuit 26 inputs the signal P or the signal Q and outputs the p signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ) or the q signal (D ₁ D ₂ D ₃ D ₃ ′E ₄ ). . The A/D conversion circuit 26 that operates in this manner can be easily constructed with 17 comparators. The two code converters 25 and 24 are integrated,
The code converter 14 and the two code converters 15 work together to perform inverse rotational symmetric conversion. When both the p signal H ₁ and the q signal H ₂ are “0”, the p signal (S ₂₁ ″S ₃₁ ″S ₄₁ ) and the q signal (S ₂₂ ″S ₃₂ ″S ₄₂ ″) are p
Equal to signal (S ₂₁ S ₃₁ S ₄₁ ) and q signal (S ₂₂ S ₃₂ S ₄₁ ).
When either the p signal H ₁ or the q signal H ₂ is “1”, the p signal (S ₂₁ ″S ₃₁ ″S ₄₁ ″) or the q signal (S ₂₂ ″S ₃₂ ″S ₄₂ ″) is p. Signal (S ₂₁ ′S ₃₁ ′S ₄₁ ′)・q
equal to the signal (S ₂₂ ′S ₃₂ ′S ₄₂ ′). When both the p signal H ₁ and the q signal H ₂ are “0”, the reception logic converter 22 outputs the signal RCONT which takes the logical value “0”, and the reception path selection unit 23 outputs the signal RCONT which takes the logical value “0”. “0”
When , p signal (S ₂₁ ″S ₃₁ ″S ₄₁ ″)・q signal (S ₂₂ ″S ₃₂ ″S ₄₂ ″), that is, p signal (S ₂₁ S ₃₁ S ₄₁ )・q
Select and output the signal (S ₂₂ S ₃₂ S ₄₂ ). p signal
When either H ₁ or q signal H ₂ is “1”,
The reception logic converter 22 converts the signal to have a logic value of “1”.
Outputs RCONT and also outputs p signal (S ₂₁ ″S ₃₁ ″S ₄₁ )・
q signal (S ₂₂ ″S ₃₂ ″S ₄₂ ), i.e. p signal (S ₂₁ ′S ₃₁ ′S ₄₁ ), q signal (S ₂₂ ′S ₃₂ ′S ₄₂ ′) and p signal
Logically converts H ₁ and q signal H ₂ . This logic conversion is the inverse of the logic conversion performed by the transmission logic conversion unit 12, and the outputs of the reception logic conversion unit 22 are the p signal (S ₂₁ S ₃₁ S ₄₁ ) and the q signal (S ₂₂ S ₃₂ S ₄₂ ). . The reception path selection unit 23 selects p which is the output of the reception logic conversion unit 22 when the value of the signal RCONT is a logical value “1”.
Select and output the signal (S ₂₁ S ₃₁ S ₄₁ ) and q signal (S ₂₂ S ₃₂ S ₄₂ ). The receiving differential logic circuit 21 receives p signal S ₁₁ and q signal in response to input p signal D ₁ and q signal D _1.
Output S ₂₁ .

This completes the explanation of the embodiment shown in FIGS. 1 and 2.

Using the signal point arrangement used in the embodiment shown in Figures 1 and 2, a communication system without four-phase phase uncertainty during reception demodulation (for example, a communication system in which a reference phase signal is superimposed on a carrier band signal) is developed. When using, the first
Transmission differential logic circuit 11, reception differential logic circuit 21, and code conversion unit 1 in the embodiment shown in FIG.
4. Code conversion unit 15, code conversion unit 24, and code conversion unit 25 are not required. In this case, the position of the signal point of the square multi-level orthogonal amplitude modulation method corresponding to the p signal (S ₁₁ S ₂₁ S ₃₁ S ₄₁ ) and q signal (S ₁₂ S ₂₂ S ₃₂ S ₄₂ ) is circular. In order to determine whether a change is required in the multilevel quadrature amplitude modulation method, the transmission logic converter uses signals (S ₁₁ S ₂₁ S ₃₁ S ₄₁ ) and signals (S ₁₂ S ₂₂ S ₃₂ S ₄₂ ). must be entered.

Although the embodiment has been described above for the case of 256 (=2 ^{2 × 4} ) values, the present invention is applicable to 2 ²ⁿ values (n is a natural number of 3 or more).
It can be used for all of the following.

When the number of values for signal P and signal Q is (2 ⁿ +2), the transmitting differential logic circuit 11 and the receiving differential logic circuit 21 of the respective components of the embodiment shown in FIGS. It is only necessary to increase or decrease the number of stages in the portion other than , according to the increase or decrease in n.

The number of values that signal P and signal Q take is (2 ⁿ + 2m)
(m is a natural number of 3 or more), p signal
The H ₁ and q signals H ₂ must have two or more digits and a binary code. p signal if m=2 or 3
The H ₁ and q signals H ₂ are two-digit binary codes and are related to the p signal H ₁ or the q signal H ₂ . The D-A conversion section adds an input terminal for the third digit from the bottom to an n-digit A-D conversion circuit corresponding to the four-digit D-A conversion circuit 163 shown in FIG. EX-
One set of circuits having the same configuration as that of the OR circuit 162 is added and connected to the added input terminal of the DA conversion circuit and the input terminal of the second digit from the bottom. The sign of each digit of p signal _H1 or q signal _H2 is added to the original EX-OR circuit 162.
Connect to EO circuit. Increase the number of digits of p signal H ₁ and q signal H ₂ to 3 or more digits and use p signal H ₁ or q signal H ₂
It is clear that the case where m is 4 or more can also be accommodated by increasing the number of stages of the portions related to each in the same manner as in the above case.

〔Effect of the invention〕

As explained in detail above, by using the present invention, it is possible to provide a modulation/demodulation device using a circular multilevel orthogonal amplitude modulation method that uses radio waves effectively and suffers less distortion in a transmission path. .

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are block diagrams showing a modulator/demodulator constituting an embodiment of the modulation/demodulation device of the present invention;
FIG. 3 is an explanatory diagram showing the arrangement of signal points of the multilevel orthogonal amplitude modulation method, and FIG. 4 is a diagram showing the truth table of logic conversion by the transmission logic conversion section. 12... Transmission logic converter, 16... DA converter.

Claims (1)

[Claims] 1 2 each having n digits (n is a natural number of 3 or more)
A square multi-level orthogonal amplitude modulation method in which a first input p signal and an input q signal, which are binary codes, are respectively made to correspond to one of ²ⁿ coordinates in the p-axis and q-axis directions that are orthogonal to each other on the signal plane. In a modulation/demodulation device comprising a modulator and a demodulator using a circular multilevel cross-amplitude modulation method in which the positions of some of the signal points are changed and the outermost points of the signal point group are arranged close to a circle, The modulator is configured to receive the first input p signal and the q
determining whether the position of the signal point of the square multi-value quadrature amplitude modulation method corresponding to the signal requires the change in the circular multi-value quadrature amplitude modulation method and outputting a first determination result; When a change is required, the second input p signal and input q signal consisting of the signs of the first input p signal and input q signal of the digit whose sign is changed are logically converted to the second input p signal and the input q signal. outputting a third input p signal and an input q signal, each of which is a binary code of the same number of digits as the input q signal, and a fourth input p signal and an input q signal, each of which is a binary code of at least one digit; a transmission logic conversion unit that selects either the second input p signal and input q signal or the third input p signal and input q signal based on the first determination result of the transmission logic conversion unit; a fifth input p signal consisting of the sign of the first input p signal or input q signal whose sign is not changed by any of the changes; and the transmission path selection section. A multi-value signal inputting the second or third input p signal or input ^q signal which is the output of The demodulator includes two D-A converters that output a signal P or a multi-value signal Q, and an orthogonal modulation circuit that receives the multi-value signal P and the multi-value signal Q and outputs a quadrature amplitude modulated wave. , a quadrature detection circuit which inputs the orthogonal amplitude modulated wave and outputs the multi-value signal P and the multi-value signal Q; and a quadrature detection circuit which inputs the multi-value signal P or the multi-value signal Q and outputs the fifth input p signal or the input q signal. a first output p signal or output q signal corresponding to the first output p signal or output q signal; a second output p signal or output q signal corresponding to the second or third input p signal or input q signal; and the fourth input p signal. or two A-D converters that output a third output p signal or an output q signal corresponding to the input q signal, and the second output p signal and the output q signal, and the third output p signal. and an output q signal, outputs a second discrimination result according to these signals, and logically converts the second output p signal and output q signal and the third output p signal and output q signal. a reception logic converter for outputting a fourth output p signal and an output q signal, each of which is a binary code having the same number of digits as the second output p signal and output q signal; and a reception path selection section that selects and outputs either the second output p signal and output q signal or the fourth output p signal and output q signal based on the second determination result. modem and modem.