JPH0352700B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modulation/demodulation device, and particularly to a modulation/demodulation device using a multilevel orthogonal amplitude modulation method.

[Conventional technology]

The multilevel orthogonal amplitude modulation method can transmit a large amount of information per unit frequency of the exclusive frequency width of the carrier band, and can effectively use radio waves in wireless transmission, so it is extremely effective when used in large-capacity digital wireless communications.

In a conventional modulation/demodulation device that uses a multilevel orthogonal amplitude modulation method, the signals to be transmitted are expressed as a p signal (S ₁₁ S ₂₁ ...S _o1 ) and a q signal (S ₁₂ S ₂₂ ...S _o2 ), which are binary codes. , P=k [(-1) ^S11・2 ^n-1 +(-1) ^S21・2 ^n-2
+...+(-1) ^Sn1・2 ⁰ ], Q=k[(-1) ^S12・2 ^n-1
+
(-1) ^S22・2 ^n-2 +...+(-1) ^Sn2・2 ⁰ ], the p signal (S ₁₁ S ₂₁ ...S _o1 ) and the q signal (S ₁₂ S ₂₂ ...S _{o2 )} are orthogonal to each other. It corresponds to a signal point (PQ) on a signal plane (pq) having a p-axis and a q-axis, where k is a positive constant.

Now, since the multilevel quadrature amplitude modulation method has the well-known four-phase phase uncertainty, except for special cases where the receiver can know the absolute phase of the transmitter,
Transmit signal point (PQ) and receive signal point (-Q P) (-P -Q) or (Q -P)
In this case, the above-mentioned correspondence between the p signal (S ₁₁ S ₂₁ ...S _o1 ), q signal (S ₁₂ S ₂₂ ...S _o2 ) and the signal point (PQ) indicates that correct signal transmission is not possible. Can not.

As explained above, the conventional modulation/demodulation device using the multilevel quadrature amplitude modulation method has the drawback of being affected by four-phase phase uncertainty.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention, or in other words, the purpose of the present invention is to solve the above-mentioned drawbacks and provide a modulation/demodulation device that uses a multilevel quadrature amplitude modulation method and is not affected by four-phase phase uncertainty. be.

[Means for solving problems]

The modem and modem of the present invention each have n (n is 3
The input p signal and the input q signal, which are binary codes of (natural number) digits, are
In the modulation and demodulation device, the modulator includes a modulator and a demodulator that use a multilevel orthogonal amplitude modulation method, each of which corresponds to one of ²ⁿ coordinates equally spaced in the directions of the axis and the q-axis. Input the sign of the first digit of each of the p signal and the input q signal.
a transmission differential logic circuit that performs phase transmission differential conversion and outputs; a first exclusive OR circuit that outputs an exclusive OR of outputs of the transmission differential logic circuit; and the input p signal and the input each of the q signals i
(i is a natural number from 2 to n) When the logical product of the exclusive OR of the codes of the th digit and the output of the first exclusive OR circuit has a logical value "1", the input p signal and the (n-1) first code conversion circuits that invert the polarity of the sign of each i-th digit of the input q signal; an alternating binary encoding modulation circuit that inputs the code conversion circuit and the output of the alternating binary encoded orthogonal amplitude modulated wave and outputs the alternating binary encoded orthogonal amplitude modulated wave; an alternating binary encoding demodulation circuit which inputs an amplitude modulated wave and outputs an output p signal and an output q signal, each of which is an alternating binary code of n digits; a reception differential logic circuit that inputs a code, performs four-phase reception differential conversion, and outputs the signal; a second exclusive OR circuit that outputs an exclusive OR of inputs of the reception differential logic circuit; and the output. When the logical product of the exclusive OR of the codes of the i-th digit of the p signal and the output q signal and the output of the second exclusive OR circuit has a logic value "1", the output p signal and [Embodiment] The circuit includes (n-1) second code conversion circuits that invert the polarity of the sign of each i-th digit of the output q signal. The present invention will now be described in detail.

FIGS. 1 and 2 are block diagrams showing a modulator/demodulator constituting a first embodiment of the modulation/demodulation apparatus of the present invention.

The modulator shown in FIG. 1 has a p signal S ₁₁ and a q signal S ₁₂
A transmission differential logic circuit 11 which inputs a p signal D ₁₁ and a q signal D ₁₂ through 4-phase transmission differential conversion and outputs a p signal D ₁₁ and a q signal D 12, and which inputs a p signal D 11 and a q signal D ₁₂ and performs a 4-phase transmission differential logic Exclusive OR circuit that outputs the sum (hereinafter referred to as EX
-OR circuit) 12 and EX-OR circuit 13
1, 133, 134 and an AND circuit 132, p signal S ₂₁ / q signal S ₂₂ or P signal S ₃₁ / q signal
Input S ₃₂ and input p signal S ₂₁ ′, q signal S ₂₂ ′ or p signal
Two code converters 1 that output S ₃₁ ′ and q signals S ₃₂ ′
3, and two DA converters 14 which input the p signal (D ₁₁ S ₂₁ ′S ₃₁ ′) or the q signal (D ₁₂ S ₂₂ ′S ₃₂ ′) and output the signal P or the signal Q, It is constituted by an orthogonal modulation circuit (not shown) that amplitude modulates one of two carrier waves having the same frequency but orthogonal to each other with a signal P and the other with a signal Q, and outputs the resultant signal as a carrier band signal. There is. The DA converter 14 has two EX-OR circuits, inputs the p signal (D ₁₁ S ₂₂ ′S ₃₁ ′) or the q signal (D ₁₂ S ₂₂ ′S ₃₂ ′), and converts the p signal (D ₁₁ D ₂₁ D ₃₁ ) Q signal (D ₁₂ D ₂₂ D ₃₂ )
a code conversion circuit 141 that outputs a signal P or a signal Q, and a D-A conversion circuit 1 that receives a p signal (D ₁₁ D ₂₁ D ₃₁ ) or a q signal (D ₁₂ D ₂₂ D ₃₂ ) and outputs a signal P or signal Q.
42.

The demodulator shown in FIG. 2 includes a quadrature detection circuit (not shown) that orthogonally detects a carrier band signal and outputs a signal P and a signal Q, and a quadrature detection circuit (not shown) that outputs a signal P or a signal Q by quadrature detection, and a p signal (D ₁₁ S ₂₁ ′S ₃₁ ′) or q signal (D ₁₂ S ₂₂ ′S ₃₂ ′)
4 and EX-OR circuits 231, 233, 234
AND circuit 232, p signal S ₂₁ ', q signal
S ₂₂ ′ or p signal S ₃₁ ′/q signal S ₃₂ ′ is input and p signal
Two code converters 23 that output S ₂₁ and q signals S ₂₂ or p signals S ₃₁ and q signals S ₃₂ , and p signals D ₁₁ and q
EX-OR circuit 22 which inputs signal D ₁₂ and outputs the exclusive OR of two input signals, p signal D ₁₁ and q signal
Input D ₁₂ , perform 4-phase reception differential conversion, and generate p signal S ₁₁・q
The receiving differential logic circuit 21 outputs the signal _S12 . The A-D converter 24 inputs the signal P or the signal Q and outputs the p signal (D ₁₁ D ₂₁ D ₃₁ ) or the q signal (D ₁₂ D ₂₂ D ₃₂ ).
42 and two EX-OR circuits, input the p signal (D ₁₁ D ₂₁ D ₃₁ ) or the q signal (D ₁₂ D ₂₂ D ₃₂ ), and input the p signal (D ₁₁ S ₂₁ ′S ₃₁ ′) or The code conversion circuit 241 outputs a q signal (D ₁₂ S ₂₂ ′S ₃₂ ′).

Next, the operation of the modulation/demodulation apparatus shown in FIGS. 1 and 2 will be explained.

The DA conversion circuit 142 converts the p signal (D ₁₁ D ₂₁ D ₃₁ ) or the q signal (D ₁₂ D ₂₂ D ₃₂ ) into P
=k [(-1) ^D11・2 ² +(-1) ^D21・2'+(-1) ^D
31・
2 ⁰ ], Q=k [(-1) ^D12・2 ² +(-1) ^D22・2'+
(−
1) D-A to signal P or signal Q as ^D32・²⁰ ]
Convert. The A-D converter circuit 242 performs inverse conversion of the D-A converter circuit 142, and converts the signal P or signal Q.
Signal (D ₁₁ D ₂₁ D ₃₁ ) or Signal (D ₁₂ D ₂₂ D ₃₂ )
A-D conversion is performed.

As already explained, due to the four-phase phase uncertainty, the signal P and signal Q at the modulator may not match the signal P and signal Q at the demodulator.
Therefore, the p signal (D ₁₁ D ₂₁ D ₃₁ ) and q signal (D ₁₂ D ₂₂ D ₃₂ ) in the modulator and the p signal (D ₁₁ D ₂₁ D ₃₁ ) and q signal (D ₁₂ D ₂₂ D ₃₂ ) may not match.

However, the p signal D ₁₁ and the q signal D ₁₂ are not affected by the four-phase phase uncertainty due to the well-known effects of the transmitting differential logic circuit 11 and the receiving differential logic circuit 21.

EX-OR circuit 12, two code converters 13,
The two code conversion units 141 work together to rotationally symmetrically transform the p signal (S ₂₁ S ₃₁ ) and the q signal (S ₂₂ S ₃₂ ) into the p signal (D ₂₁ D ₃₁ ) and the q signal (S ₂₂ S ₃₂ ), so
The p signal (S ₂₁ S ₃₁ ) and q signal (S ₂₂ S ₃₂ ) corresponding to an arbitrary signal point, and the position at which this signal point is rotated by π/2・π or 3π/2 around the origin of the signal plane. It does not match the p signal (S ₂₁ S ₃₁ ) and q signal (S ₂₂ S ₃₂ ) corresponding to the signal point. That is, the p signal (S ₂₁ S ₃₁ ) and the q signal (S ₂₂ S ₃₂ ) are also not affected by the four-phase phase uncertainty.

The code conversion circuit 242 performs the inverse conversion of the code conversion performed by the code conversion circuit 142, and the code conversion unit 23 performs the inverse conversion of the code conversion performed by the code conversion unit 13. Therefore, the two code conversion circuits 241 and two The code converter 23 and the EX-OR circuit 22 work together to convert the p signal (S ₂₁ S ₃₁ ) and q signal (S ₂₂ S ₃₂ ) into p signal (S ₂₁ S ₃₁ ) and q signal (S ₂₂ S ₃₂ ). Convert the sign to .

The code conversion circuit 141 is a well-known circuit that converts an alternating binary code into a natural binary code.
As described above, the conversion circuit 142 is a natural binary encoding D-A conversion circuit, so two D-A conversion circuits are used.
The converter 14 and the above-mentioned orthogonal modulation circuit constitute an alternating binary encoding orthogonal modulation circuit. Further, the code conversion circuit 242 is a well-known circuit that converts a natural binary code into an alternating binary code, and the A-D conversion circuit 242 is a natural binary encoding D-A conversion circuit. The circuit and the two DA converters 24 constitute an alternating binary encoding demodulation circuit.

Next, the rotationally symmetric transformation described above will be explained in more detail.

Figures 3a and 3b are drawings showing tables for explaining the operation of rotationally symmetric transformation, and Figure 3a shows the case where the signal point is in the first or third quadrant of the signal plane. b is a table for cases in the second or fourth quadrant. In FIGS. 3a and 3b, the first and second columns from the left of the table show the code conversion operation performed by the EX-OR circuit 12 and the code conversion unit 13 together, and the third to sixth columns The operation performed by the code conversion circuit 141 is shown.

Considering the way the D-A conversion circuit 142 operates,
The p signal (D ₁₁ D ₁₂ ) is (00), (10), (11), (01)
In this case, the signal points corresponding to the p signal (D ₁₁ D ₂₁ D ₃₁ ) and the q signal (D ₁₂ D ₂₂ D ₃₂ ) are located in the first, second, third, and fourth quadrants of the signal plane.

If the signal point is in the first or third quadrant,
The output of the EO circuit 12 is “0” and the output of the AND circuit 13
Since the output of 2 is also "0", the code converter 13 outputs the input as is. When the signal point is in the second or fourth quadrant, the output of the EX-OR circuit 12 is "1", so the code converter 13 outputs the two inputs as they are when their values are equal; When the values differ, the polarity is inverted and output.
The first and second columns from the left in Figures 3a and 3b summarize the above information in a table.

In the code conversion circuit 141, D _2j (j is “1”
or “2”) or D _3j is D _1j・S _2j
Or it depends on D _2j and S _3j . The third to sixth columns from the left in Figure 3 a and b are done like this.
D _2j or D _3j is expressed in a matrix in the form of (D ₂₁ D ₂₂ ) or (D ₃₁ D ₃₂ ).

First, consider the relationship between the position of the signal point and the signal (D ₂₁ D ₂₂ ).

When the signal point is in the first quadrant, in Figure 3a, if i = 1 and the signal (D ₁₁ 2 ₁₂ ) is (00), looking at the third column, the signal (D ₂₁ D ₂₂ ) is (00).・
When (10), (11), and (01), the signal (D ₂₁ D ₂₂ ) becomes (00), (10), (11), and (01), and the p signal (0S ₂₁ S ₃₁ ) and q signal The signal points corresponding to (0S ₂₂ S ₃₂ ) are the four signal points that are in the upper right, upper left, lower left, and lower right quarters of the 16 signal points arranged in the square of the first quadrant. Either. When the signal point is in the second quadrant, if i=1 in Figure 3b and the signal (D ₁₁ D ₁₂ ) is (10), looking at the fourth column, the signal (S ₂₁ S ₃₂ ) becomes ( 00)・(10)・
When (11)・(01), the signal (D ₂₁ D ₂₂ ) is (10)・
(11)・(01)(00), p signal (1S ₂₁ S ₃₁ )・q
The signal point corresponding to the signal (0S ₂₂ S ₃₂ ) is the upper left corner of the 16 signal points arranged in a square shape in the second quadrant.
This is one of four signal points that correspond to 1/4 of each of the lower left, lower right, and upper right. From the above considerations when the signal points are in the first or second quadrant, four signals corresponding to 1/4 each of the upper right, upper left, lower left, and lower right of the 16 signal points in the first quadrant. The signal corresponding to the point (S ₂₁ S ₂₂ ) and the signal for the four signal points corresponding to the upper left, lower left, lower right, and 1/4 of the upper right of the 16 signal points in the second quadrant (S ₂₁ S ₂₂ ) is found to be equal. This means that the signal (S ₂₁ S ₂₂ ) corresponding to an arbitrary signal point in the first quadrant corresponds to the signal point located at a position rotated by π/2 counterclockwise around the origin of the signal plane. Signal ( _{S21 S22} )
This shows that they match.

By performing the same consideration when the signal point is in the third or fourth quadrant, we can calculate the signal corresponding to any signal point (S ₂₁ S ₂₂ ) and the signal point counterclockwise around the origin of the signal plane. π/2・π・in the direction
It can be seen that the signal (S ₂₁ S ₂₂ ) corresponding to the signal point located at the position rotated by 3π/2 matches.

Next, the relationship between the position of the signal point and the signal (S ₃₁ S ₃₂ ) will be considered.

If the signal point is in the first quadrant and the signal (D ₂₁ D ₂₂ ) is (00), if i = 2 in Figure 3a and look at the third column, the signal (S ₃₁ S ₃₂ ) will be (00). (Ten)·
When (11) and (01), the signal (D ₃₁ D ₃₂ ) is (00) and
(10)・(11)・(01), p signal (00S ₃₁ )・q
The signal points corresponding to the signal (00S ₃₂ ) are signals S ₃₁ and S ₃₂
These are the upper right, upper left, lower left, and lower right signal points among the four signal points corresponding to all combinations of . Also, the signal (D ₂₁ D ₂₂ ) corresponding to the signal point located in the first quadrant and located at a position rotated by π/2 counterclockwise from the signal point where the signal (D ₂₁ D ₂₂ ) is (00) is (10). Therefore, the signal point is in the second quadrant and the signal (D ₂₁ D ₂₂ )
Considering the case where is (10), in Figure 3b, if i = 2 and look at the fourth column, the signal (D ₃₁ D ₃₂ ) is (00), (10), (11), (01). When the signal (D ₃₁ D ₃₂ ) becomes (00), (10), (11), (01),
The signal points corresponding to the p signal (11S ₃₁ ) and q signal (00S ₃₂ ) are the upper left, lower left, lower right, and upper right signal points among the four signal points corresponding to all combinations of signals S ₃₁ and S ₃₂ . It is. From the above considerations, p signal (00S ₃₁ )
The signal point corresponding to the q signal (00S ₃₂ ) is the signal S ₃₁ .
When the signal points are the upper right, upper left, lower left, and lower right of the four signal points corresponding to all combinations of S ₃₂ , the signal points corresponding to the p signal (11S ₃₁ ) and the q signal (00S ₃₂ ) are It can be seen that among the four signal points corresponding to all combinations of signals _S31 and _S32 , these are the upper left, lower left, lower right, and upper right signal points. This means that the signal points corresponding to the p signal (00S ₃₁ ) and q signal (00S ₃₂ ) are moved counterclockwise by π/2 around the origin of the signal plane.
The signal point at the rotated position is the p signal (11S ₃₁ ).
This corresponds to the q signal (00S ₃₂ ), indicating that the values of S ₃₁ and S ₃₂ do not change.

By performing similar considerations for all combinations of signals D ₂₁ D ₂₂ , we can calculate the signal (S ₂₁ S ₂₂ ) corresponding to any signal point in the first quadrant and the signal point rotated counterclockwise by π/2. It can be seen that the signal (S ₂₁ S ₂₂ ) corresponding to the signal point at the position matches. Furthermore, by performing the same consideration when the signal point is in the third or fourth quadrant, we can calculate the signal corresponding to any signal point (S ₃₁ S ₃₂ ) and its signal point with the origin of the signal plane as the center. π/2・clockwise
It can be seen that the signal (S 31 S 32 ) corresponding to the signal point located at the position rotated by π·3π/2 coincides with the signal (S ₃₁ S ₃₂ ).

Signal (S ₂₁ S ₂₂ ) and signal (S ₃₁ S ₃₂ ) corresponding to any signal point and the position of the signal point rotated counterclockwise by π/2, π, 3π/2 around the origin of the signal plane Since the signal (S ₂₁ S ₂₂ ) and the signal (S ₃₁ S ₃₂ ) corresponding to the signal point located in coincide with each other, the p signal (S ₂₁ S ₃₁ ) and the q signal (S ₂₂ S ₃₂ ) also have a similar matching relationship. have.

Although the first embodiment has been described above for the case of 64 (=2 ^{2 × 3} ) values, the present invention can be used for all cases of 2 ²ⁿ (n is a natural number of 3 or more) values.

In the modulator shown in FIG.
By adding one digit, the second and third digit code conversion unit 13
The 3-digit code conversion circuit 141 and the DA conversion circuit 142 are converted into a 4-digit code conversion circuit and a DA conversion circuit using the same connection as the 3-digit code conversion circuit 141 and the DA conversion circuit 142. The A-D converter circuit 242 and the code converter circuit 241 are changed to a 4-digit D-A converter circuit and a code converter circuit, and the code converter 23 is replaced with a 4-digit D-A converter circuit and a code converter circuit.
A second embodiment of the present invention can be obtained by adding 2 digits and connecting them in the same way as the code conversion unit 23 for the second and third digits.
A modulation/demodulation device with 2 ^2×4 (=256) values is obtained. Fourth
FIG. 5 is a block diagram showing a modulator/demodulator constituting a second embodiment of the present invention obtained in this way. The fact that this embodiment is not affected by the four-phase phase uncertainty is explained by comparing the position of the signal point with the signal (S ₃₁ S ₃₂ ) in the explanation of the rotational object transformation of the embodiment shown in FIGS. 1 and 2. This can be seen by repeating the same considerations as those regarding relationships.

By repeating the same changes as the first embodiment of the present invention shown in FIGS. 1 and 2 to obtain the second embodiment of the present invention shown in FIGS. 4 and 5, These are third and fourth embodiments of the present invention. 2 ^2×5 value・2 ^2×6
A modem with the value... is obtained.

The invention described in Japanese Patent Application Laid-Open No. 59-112749 appears to be similar to the 64-value modulation/demodulation device of the present invention, but it is completely different. That is _, in the modulator constituting the 64-value modulation/demodulation apparatus of the present invention, taking the modulator shown in _FIG . One of the input terminals of the AND circuit 132 is connected to the output terminal of the EX-OR circuit 12.
However, in the invention described in Japanese Unexamined Patent Publication No. 59-112749 _, one of the input terminals of the AND circuit ₁₃₂ is an It is connected to the output terminal of circuit 131. The demodulator constituting the 64-value modem of the present invention also has similarities and differences with the above, and as explained above, the 64-value modem of the present invention is described in Japanese Patent Laid-Open No. 112749/1983. The structure and operation of this invention are completely different from those of the previous invention.

〔Effect of the invention〕

As explained in detail above, the modulation/demodulation device of the present invention uses a means of rotationally symmetrically converting the codes from the second digit onward of each of two series of binary codes, which are signals to be transmitted. By using the modulation and demodulation device, it is possible to obtain a modulation and demodulation device that uses a multilevel orthogonal amplitude modulation method and is not affected by four-phase phase uncertainty.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the modulator/demodulator constituting the first embodiment of the modulation/demodulation device of the present invention, and FIGS. 3a and 3b are tables for explaining the operation of rotationally symmetric conversion. Fig. 3a is a drawing showing a table when the signal point is in the first or third quadrant, and Fig. 3b is a drawing showing a table when the signal point is in the second or fourth quadrant. The drawings, FIGS. 4 and 5 show the modulator and demodulator constituting the second embodiment of the modulation and demodulation device of the present invention.
FIG. 2 is a block diagram showing a demodulator. 13... code converter, 14... DA converter.

Claims (1)

[Claims] 1 2 each having n digits (n is a natural number of 3 or more)
A multilevel orthogonal amplitude modulation method is used in which the input p signal and the input q signal, which are binary codes, are made to correspond to one of ²ⁿ coordinates equally spaced in the p-axis and q-axis directions that are perpendicular to each other on the signal plane. In a modulation and demodulation device comprising a modulator and a demodulator, the modulator inputs codes of the first digits of the input p signal and the input q signal, performs four-phase transmission differential conversion, and outputs a transmission differential signal. a logic circuit, a first exclusive OR circuit that outputs an exclusive OR of the outputs of the transmission differential logic circuit, and the input p
signal and the input q signal, respectively i (i is 2
When the logical product of the exclusive OR of the codes of the th digit (~n natural number) and the output of the first exclusive OR circuit has a logical value "1", the input p signal and the input q signal (n-1) first code conversion circuits each inverting the polarity of the sign of the i-th digit; the output of the transmission differential logic circuit;
1) an alternating binary encoding modulation circuit that inputs the output of the first code conversion circuit and outputs an alternating binary encoded orthogonal amplitude modulated wave; an alternating binary encoding demodulation circuit which inputs an alternating binary encoded orthogonal amplitude modulated wave and outputs an output p signal and an output q signal, each of which is an n-digit alternating binary code;
A reception differential logic circuit inputs the sign of the first digit of the signal and the output q signal, performs four-phase reception differential conversion, and outputs the signal, and outputs an exclusive OR of the inputs of the reception differential logic circuit. A second exclusive OR circuit, the exclusive OR of the i-th digit signs of each of the output p signal and the output q signal, and the output of the second exclusive OR circuit are ANDed. and (n-1) second code conversion circuits that invert the polarity of the sign of the i-th digit of each of the output p signal and the output q signal when the logical value is "1". modem.