JPH0243138B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multiplexer type ultrasonic flaw detector that uses a plurality of contacts by switching them, and more specifically relates to a multiplexer type ultrasonic flaw detector that can switch probes at high speed. Regarding sonic flaw detectors.

[Conventional technology]

A multiplexer-type ultrasonic flaw detector sequentially switches multiple probes in synchronization with the pulse repetition frequency (hereinafter referred to as PRF), and transmits ultrasonic waves at a predetermined frequency from the switched probes.
The reflected wave of this ultrasonic wave from a defect in the object to be tested is taken in as a defect signal representing defect information on the object to be tested, and the object to be tested for flaws is detected.

In a multiplexer type ultrasonic flaw detector, the defect signal output from each probe can be captured for a certain period of time based on a gate signal synchronized with the PRF. It is necessary to set the gate width appropriately according to each probe. Also, since the probes are switched in synchronization with the PRF, it is necessary to match the timing of outputting the gate signal. Furthermore, it is necessary to appropriately determine a level signal for each probe to determine whether the defect signal output by each probe is a true defect signal rather than noise.

For this reason, conventional multiplexer-type ultrasonic flaw detectors store in advance the data necessary for flaw detection of the object to be tested for each probe in the main memory circuit, and each time the probe is switched, The data stored in the main memory circuit was transmitted to each module making up the flaw detector.

[Problem that the invention seeks to solve]

By the way, in order to transmit the data stored in the main memory circuit to each module each time the probe is switched, a central processing unit (hereinafter referred to as CPU) is required.
must be done through. That is, the data in the main memory circuit is not directly transmitted to each module, but is transmitted once to the CPU, and then from this CPU to each module. For this reason,
If you increase the PRF and increase the transducer switching speed, the data will not be transmitted in time;
There was a problem that high-speed flaw detection was not possible.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a multiplexer-type ultrasonic flaw detector that can perform high-speed flaw detection even when the flaw detector is equipped with a plurality of probes. shall be.

[Means for solving problems]

Therefore, in the present invention, for each of the plurality of probes, a main memory circuit that stores data necessary for flaw detection of the object to be tested based on defect signals, and a main memory circuit that stores data necessary for flaw detection of the object to be flaw tested based on defect signals, and A memory circuit that stores data stored in the circuit via a central processing unit, and a memory circuit that stores data stored in the circuit via a central processing unit, and data corresponding to the switched probes each time multiple probes switch in synchronization with the pulse repetition frequency. A multiplexer-type ultrasonic flaw detector is constituted by a signal generating means that reads out the data and generates a signal necessary for flaw detection of the object to be flaw-detected based on the read data.

[Effect]

The multiplexer type ultrasonic flaw detector configured as described above causes the data stored in the main memory circuit to be stored in the memory circuit via the central processing unit when the flaw detector is activated. Next, each time the probe is switched in synchronization with the pulse repetition frequency, data corresponding to the switched probe is directly transmitted from the storage circuit to the signal generation means, and the signal generation means receives the transmitted data. A signal necessary for flaw detection of the object to be flawed is generated based on the flaw detection.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of the main parts of a multiplexer type ultrasonic flaw detector according to the present invention. 1st
In the figure, 1 is the main control circuit, B is the CPU, 3 is the main memory circuit, 4 is the gate module, 5 is the distance sensitivity correction module (hereinafter referred to as DAC module), and 6 is the automatic gain control module (hereinafter referred to as AGC module).
(called a module), 7 is a volatile memory circuit, 8,
9, 10 and 11 are gate circuits, 12 is an inverting circuit, 13 is an internal address generation circuit, 14 is a gate width signal generation counter (signal generation means), 15 is a starting point signal generation circuit (signal generation means), and 16 is a level Signal generation circuit (signal generation means) 17 is a control bus, 18 is a data bus for transmitting data,
19 is an address bus that transmits the address of data to read or write; 20 is a PRF line that transmits a PRF signal; and 21 is a channel that is output in synchronization with the PRF signal and sequentially switches four probes (not shown). This is a channel selection signal line that transmits a selection signal. In addition, DAC5 and
It is assumed that the AGC 6 also has a volatile memory circuit 7 similarly to the gate module 4. Also, PRF
The channel selection signal synchronized with the signal is a signal indicating which of the first probe, second probe, third probe, and fourth probe is operable.

The main memory circuit 3 is a non-volatile memory device that retains its memory contents even when the power is turned off, and as described above, the main memory circuit 3 is a non-volatile memory device that retains its memory contents even when the power is turned off. It stores the data necessary for flaw detection. The data stored in the main memory circuit 3 is transmitted to the gate module 4, DAC 5, and AGC 6 via the CPU 2 when the flaw detector is activated, and is stored in the memory circuit of each module. Here, a case will be described in which data stored in the main memory circuit 3 is transmitted to the memory circuit 7 of the gate module 4.

First, the CPU 2 reads the data of the first probe to be written into the memory circuit 7 from the main memory circuit 3 and outputs it to the data bus 18, and also sends the address of the memory circuit 7 to which this data is to be written to the address bus 19. Send. Next, the gate circuit 8 is activated by the PRF signal output to the PRF signal line 20.
and 9 open, a write signal is output to the control bus 17 to write the data in the main memory circuit 3 to the memory circuit 10. Similarly, the data of the second probe, the data of the third probe, and the data of the fourth probe are
output the data of the probe along with the address of the memory circuit 7 where these data should be written,
The information is sequentially written into the memory circuit 7 in synchronization with the PRF signal and stored. Note that data is stored in the DAC 5 and AGC 6 in the same manner, but the explanation thereof will be omitted.

When each module that makes up the flaw detector finishes storing data in each memory circuit, each time the probe is switched in synchronization with the PRF signal, data corresponding to the switched probe is transferred from each memory circuit. Read it out and transmit it to each part. Here, the operation of the gate module 4 will be explained with reference to the timing chart shown in FIG.

First, when the internal address generation circuit 13 switches the probe in accordance with the channel selection signal output in synchronization with the PRF signal, the address of the data corresponding to the first probe to be read from the memory circuit 7 is generated. The gate signal generation counter 14 outputs a load signal to the gate circuit 10 and instructs that the data read from the memory circuit 7 should be taken in.
Output to. Then, it is inverted via the inverter 12 and input to the gate circuits 10 and 11.
When the PRF signal becomes high level "H" (see FIG. 2a), the gate circuits 10 and 11 are opened, and the address output from the internal address generation circuit 13 is input to the memory circuit 7 via the gate circuit 10. , the data stored at this address is passed through the gate circuit 11 to the gate signal generation counter 1.
4 is output. Further, the gate generation counter 14 takes in the data output from the memory circuit 7, generates a gate width signal that keeps the gate signal at a high level "H" for a certain period of time based on the taken data, and outputs it. (See Figure 2 b). Similarly, when the internal address generation circuit 13 outputs an address signal and a load signal, and the data output from the storage circuit 7 is sequentially outputted to the gate signal starting point generation circuit 15 and the level signal generation circuit 16,
A gate signal starting point generating circuit 15 and a level signal generating circuit 16 generate and output a starting point signal and a level signal, respectively. Note that the above operation is performed after the probe is switched, and then the switched probe receives the ultrasonic wave T.
This is done before sending 1.

Next, when the PRF signal becomes low level "L", the ultrasonic wave T1 is transmitted from the probe, and after a predetermined period of time, a defect signal F1 corresponding to the reflected wave from the defect of the object to be tested is output from the probe. (See Figure 2c). This defect signal is taken into the flaw detector by opening a gate circuit (not shown) in response to the gate signal output from the gate signal generation counter 14. Further, the gate signal taken into the flaw detector is compared with the level signal output from the level signal generation circuit 16, and it is determined whether or not it is a true defect signal.

In the same way, the PRF signal goes to high level "H"
Each time, the second probe, the third probe, the fourth probe, the first probe, the second probe, etc. are repeated. The data corresponding to each probe is transferred from the memory circuit 7 to the gate generation counter 14 and the gate signal origin generation circuit 1.
5 and the level signal generating circuit 16, and the gate width signal, the starting point signal, and the level signal are generated and outputted by the gate generating counter 14, the gate signal starting point generating circuit 15, and the level signal generating circuit 16, respectively. (See Figure 2 b).

〔Effect of the invention〕

As explained above, according to the present invention, the main memory circuit stores data necessary for flaw detection of the object to be tested based on defect signals for each of the plurality of probes, and when the flaw detector is started, A probe in which the data stored in the memory circuit is stored in the memory circuit via a central processing unit, and the signal generation means is switched each time multiple probes are switched in synchronization with the pulse repetition frequency. The data corresponding to the child is read directly from the memory circuit, and the signal necessary for flaw detection of the object to be tested is generated based on the read data, so the pulse repetition frequency is increased.
The effect is that high-speed flaw detection can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiplexer type ultrasonic flaw detector according to the present invention, and FIG. 2 is a timing chart illustrating the operation of the multiplexer type ultrasonic flaw detector according to the present invention. 1... Main control circuit, 2... Central processing unit (CPU), 3... Main memory circuit, 4... Gate module, 5... Distance sensitivity compensation module (DAC), 6... Automatic gain control module ( AGC), 7...Memory circuit, 8, 9, 10, 11
... Gate circuit, 12 ... Inverting circuit, 13 ... Internal address generation circuit, 14 ... Gate generation counter, 15 ... Starting point signal generation circuit, 16 ... Level signal generation circuit, 17 ... Control bus, 1
8...Data bus, 19...Address bus, 20
...PRF line, 21...Channel selection signal line.

Claims (1)

[Scope of Claims] 1. A plurality of probes are sequentially switched in synchronization with a pulse repetition frequency, and ultrasonic waves of a predetermined frequency are transmitted from the switched probes, and an object to be inspected in response to the ultrasonic waves is detected. In a multiplexer-type ultrasonic flaw detector that receives a reflected wave, captures the reflected wave as a defect signal representing defect information of the object to be tested, and performs flaw detection on the object to be tested, for each of the plurality of probes, A main memory circuit that stores data necessary for flaw detection of the object to be tested based on the defect signal, and central processing of the data stored in the main memory circuit when the flaw detector is activated and when the data is changed. A storage circuit that stores data via the device, and each time the plurality of probes are switched in synchronization with the pulse repetition frequency, data corresponding to the switched probes is directly transmitted, and the transmission A multiplexer-type ultrasonic flaw detector, characterized in that the multiplexer-type ultrasonic flaw detector is equipped with a signal generating means for generating a signal necessary for flaw detection of the object to be flaw-detected based on the flaw-detecting data. 2. Claim 1 in which the main memory circuit is a nonvolatile memory device, and the memory circuit is a volatile memory device.
The multiplexer type ultrasonic flaw detector described in Section 1. 4 The signals necessary for flaw detection of the object to be flawed include a starting point signal that instructs the sending timing of a gate signal that is synchronized with the pulse repetition frequency and sets the timing at which the defect signal should be captured, and a period during which the defect signal should be captured. A patent that is a level signal for determining that the defect signal corresponds to the object to be inspected when the gate width signal to be set and the defect signal captured by the gate width signal are greater than a predetermined size. A multiplexer type ultrasonic flaw detector according to claim 1.