JPH0243139B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog signal output device for a multiplexer type ultrasonic flaw detector.

[Conventional technology]

A multiplexer-type ultrasonic flaw detector switches multiple probes sequentially in synchronization with a pulse repetition frequency (hereinafter referred to as PRF), and transmits ultrasonic waves at a predetermined frequency from the switched probes. The reflected wave of the ultrasonic wave from a defect in the object to be tested is taken in as a defect signal representing defect information on the object to be tested, and the object to be tested for flaws is detected. This defect signal contains noise in addition to signals corresponding to reflected waves obtained when the ultrasonic waves are reflected by real defects in the object to be inspected. Therefore, it is necessary to obtain only the defect signal corresponding to the reflected wave obtained by the ultrasonic wave being reflected by the real defect of the object to be inspected, that is, the true defect signal.

FIG. 2 is a configuration diagram of a conventional analog signal output device for an ultrasonic flaw detector that outputs the true defect signal as an analog signal. In FIG. 2, 20 is a defect signal that counts the number of times the defect signal exceeds a preset level, and when the counted value reaches the preset value, the defect signal is determined to be a true defect signal. A detection circuit 21 detects and holds the peak value of the defect signal taken in in synchronization with the PRF, and a peak value hold circuit 22 stores the highest peak value, which is the highest level among the peak values, and detects the peak value of the defect signal. This is a storage circuit that outputs the stored maximum peak value in analog form when the detection circuit 20 determines that it is a true defect signal.

[Problem that the invention seeks to solve]

By the way, when a multiplexer-type analog signal output device for an ultrasonic flaw detector is configured using a conventional analog signal output device for an ultrasonic flaw detector, the above-mentioned defect signal judgment circuit 20, peak value hold circuit 21, and storage circuit 22 The number of probes required corresponds to the number of probes, leading to an increase in the size and cost of the device.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a multiplexer-type analog signal output circuit for an ultrasonic flaw detector that can be made smaller and lower in cost.

[Means for solving problems]

Therefore, in the present invention, for each of a plurality of probes, the number of times the defect signal continuously exceeds a preset level is counted, and when the counted value reaches the preset value, the defect signal is determined to be a true defect. A defect signal detection means outputs a count-up signal which is considered to be a signal, and the count value of the defect signal detection means is stored for each of the plurality of probes, and the probe is activated in synchronization with the pulse repetition frequency. Each time it is switched, the stored count value corresponding to the probe that was outputting a defect signal immediately before switching is rewritten to the count value of the defect signal detection means, and
a first storage means that sets a stored count value corresponding to the switched probe as a count value of the defect signal detection means; , a peak value hold circuit that detects and holds the peak value of the defect signal, an analog-to-digital converter that converts the defect signal with the peak value held into a digital signal, and a peak value A second section for storing the defect signal having the maximum peak value among the defect signals held and converted into digital signals.
A multiplexer-type superconverter is provided from a memory means for a plurality of probes, and a digital-to-analog converter that is provided for each of the plurality of probes and converts the defect signal stored in the second memory means into an analog signal and outputs the analog signal. Constructs an analog signal output device for a sonic flaw detector.

[Effect]

In the multiplexer-type analog signal output device for an ultrasonic flaw detector configured as described above, the first storage means is defect signal detection means for detecting whether or not a defect signal is a true defect signal for each of a plurality of probes. The second storage means stores the detection result of the maximum defect signal for each of the plurality of probes, and the second storage means stores the detection result of the maximum defect signal for each of the plurality of probes. Each time the switching is performed, the stored content of the first storage means is replaced with the count value of the defect signal detection means, and the peak value of the detected defect signal is greater than the peak value of the defect signal stored in the second storage means. If it is larger, the peak value of the defect signal stored in the second storage means is updated, and the second storage means stores the digital-to-analog converter provided for each of the plurality of probes. Each defect signal is converted into an analog signal and output.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a multiplexer type analog signal output device for an ultrasonic flaw detector according to the present invention. In FIG. 1, 1 is a reference signal generation circuit in which a reference level is set for a defect signal F output by a probe (not shown), and outputs a reference signal S corresponding to the set reference level;
Comparing the defect signal F output from the probe switched in synchronization with the PRF signal with the reference signal S,
When the defect signal F is larger than the reference signal S, a comparison circuit outputs a comparison signal that takes a high level "1". 3 is a comparison circuit that outputs a comparison signal in synchronization with the PRF signal and is used to set the timing at which the defect signal F should be taken in. A gate circuit 4 that opens and closes according to a gate signal G counts the number of times that the defect signal F exceeds the reference signal S, and when the counted value reaches a preset value, it outputs a count-up signal "1". The output counter 5 is for each of multiple probes,
This is a first storage circuit that stores the count value of the counter 4.

The reference signal generation circuit 1, the comparator circuit 2, the gate circuit 3, and the counter 4 count the number of times that the defect signal continuously exceeds a preset level, and when the counted value reaches the preset value, the defect signal is This constitutes a defect signal detecting means that outputs a count-up signal indicating that the signal is a true defect signal. counter 4
The count-up signal output by the count-up signal indicates that the defect signal F after the output of the count-up signal is the true defect signal F. Furthermore, the count value of the counter 4 and the count value stored in the first storage circuit 5 are as follows.
When a channel selection signal CH that sequentially switches multiple probes in synchronization with the PRF signal is output, the probes can be switched. Each time the probe is switched by the channel selection signal CH,
The count value corresponding to the probe that was outputting the defect signal F immediately before switching, which is stored in the first memory circuit 5, is rewritten to the count value of the counter 4, and the count value of the first memory circuit 5 is rewritten to the count value of the counter 4. The memorized count value corresponding to the switched probe is set in the counter 4.

Next, 6 is a peak value hold circuit that detects and holds the peak value of the defect signal F every time the defect signal F is input in synchronization with the PRF signal, and 7 is the defect signal F whose peak value is held. 8 and 9 are buffers that temporarily store the defect signal F converted into a digital signal; 10 is a buffer that stores the defect signal F stored in the buffer 8 and the defect signal F stored in the buffer 9; A determination circuit 11 compares the magnitude with the defect signal F for each of the plurality of probes, and a determination circuit 11 stores the peak value for each of the plurality of probes, and selects the defect signal F having the maximum peak value among the defect signals F converted into digital signals. , a second memory circuit for storing data, respectively; 12, a condition determination circuit that outputs a write signal to the second memory circuit 11 when a condition described later is satisfied; 13, a stretch circuit;
14 is provided for each of the plurality of probes,
This is a digital-to-analog converter that converts each of the defect signals F having the maximum peak value stored in the second storage circuit into analog signals and outputs the analog signals.

Next, a series of operations of the peak value hold circuit 6, analog/digital converter 7, buffers 8 and 9, and second storage circuit 11 will be explained. When the probe is switched by the channel selection signal CH, the peak value hold circuit 6 holds the peak value of the defect signal F output from the switched probe,
The defect signal F holding the peak value is stored in the buffer 8 and output to the determination circuit 10. On the other hand, the second storage circuit 11 causes the buffer 9 to store the defect signal F holding the peak value corresponding to the switched probe. Next, the determination circuit 10 compares the defect signal F stored in the buffer 8 from the peak value hold circuit 6 with the defect signal F stored in the buffer 9, and determines that the defect signal F stored in the buffer 8 is When the defect signal is larger than the defect signal F stored in the buffer 9, a determination signal that takes a high level "1" is output. The condition determination circuit 12 indicates that the counter 4 has a count-up signal of "1" and the determination circuit 10
is the judgment signal “1”, and the comparison circuit 2 is the comparison signal “1”
While outputting , a write signal is output to the second memory circuit 11 to cause the second memory circuit 11 to store the defect signal F in which the peak value stored in the buffer 8 is held. Immediately after the device is started, the second storage circuit 11 does not store anything, so the determination signal "1" is output, and the peak value hold circuit 6 outputs the defect signal F which initially held the peak value.
will be stored in the second storage circuit 11.

When the condition determination circuit 12 outputs an output signal instructing that a defective signal should be output and also outputs a channel selection signal CH, the storage circuit 11 stores the stored contents corresponding to the channel selection signal CH into a corresponding digital format.・Analog converter 14
Convert it to an analog signal and output it.

〔Effect of the invention〕

As explained above, according to the present invention, the first memory stores the detection results of the defect signal detection means for detecting whether or not the defect signal is a true defect signal for each of the plurality of probes. For each of the means and the plurality of probes, a second storage means is provided for storing the maximum peak value of the defect signal, each time the probe is switched in synchronization with the pulse repetition frequency. The stored content of the first storage means is replaced with the counted value of the defect signal detection means, and if the peak value of the detected defect signal is larger than the peak value of the defect signal stored in the second storage means, the second storage means is replaced with the count value of the defect signal detection means. The peak value of the defect signal stored in the storage means is updated, and the digital-to-analog converter provided for each of the plurality of probes converts the defect signal stored in the second storage means into an analog signal. As the number of probes increases, all you need to do is increase the storage capacity of each storage means and add digital-to-analog converters. The slave analog signal output device does not need to be large-sized, and costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiplexer type analog signal output device for an ultrasonic flaw detector according to the present invention, and FIG. 2 is a block diagram of a conventional analog signal output device for an ultrasonic flaw detector. 1...Reference signal generation circuit, 2...Comparison circuit, 3
...Gate circuit, 4...Counter, 5...First memory circuit, 6...Peak value hold circuit, 7...
Analog/digital converter, 8, 9... Buffer, 10... Judgment circuit, 11... Second storage circuit, 12... Condition judgment circuit, 13... Stretch circuit, 14... Digital/analog converter.

Claims (1)

[Claims] 1.Sequentially switching multiple probes in synchronization with the pulse repetition frequency, transmitting ultrasonic waves of a predetermined frequency from the switched probes, and receiving reflected waves of the ultrasonic waves from defects in the object to be tested. In a multiplexer-type analog signal output device for an ultrasonic flaw detector that outputs a defect signal corresponding to the reflected wave as an analog signal, the defect signal continuously exceeds a preset level for each of the plurality of probes. defect signal detecting means for counting the number of times the defect signal has become a true defect signal, and outputting a count-up signal indicating that the defect signal is a true defect signal when the counted value reaches a preset value; The count value of the defect signal detection means is stored for each of the probes, and each time the probe is switched in synchronization with the pulse repetition frequency, the stored defect signal is detected immediately before the probe is switched. The count value corresponding to the probe that was outputting the signal is rewritten to the count value of the defect signal detection means, and the stored count value corresponding to the switched probe is rewritten as the count value of the defect signal detection means. a first storage means for setting the counted value of the detection means; and a peak value hold circuit for detecting and holding the peak value of the defect signal each time the defect signal is inputted in synchronization with the pulse repetition frequency. an analog-to-digital converter that converts the defect signal in which the peak value is maintained into a digital signal; and for each of the plurality of probes, the peak value is maintained;
a second storage means for storing the defect signal having the maximum peak value among the defect signals converted into digital signals; A multiplexer type analog signal output device for an ultrasonic flaw detector, characterized in that it is equipped with a digital-to-analog converter that converts each defect signal into an analog signal and outputs the same.