JPH0243157B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a time adjustment device suitable for application to a clock used in a vehicle that frequently passes through the international date line, such as a ship or an aircraft. .

"Prior Art" It is necessary to change the display on the clock when passing through the international date line. For this purpose, the special public
A time adjustment device is proposed in "Publication No. 33513".
The time adjustment device described in this publication has a structure in which, when a time value to be corrected is set, a correction pulse is given to the sub-clock for the set time to correct the display of the sub-clock.

"Problems to be Solved by the Invention" The time adjustment device described in this publication has a gate circuit 31 for time adjustment inserted in series in a regular pulse transmission path between a master clock and a slave clock, and this gate circuit 31 is connected to, for example, When adjusting in the direction of delay, the structure is such that the clock is closed and the time is adjusted. Therefore, if the correction circuit fails, there is a risk that the gate circuit 31 may be left closed. If the gate 31 is left closed, the regular pulses that should be transmitted from the master clock to the slave clock cannot be transmitted, resulting in a major inconvenience in that the clock function stops.

"Means for Solving the Problems" In the present invention, as shown in the functional diagram of FIG. For example, one regular pulse is sent to the slave clock 2 every 30 seconds as before.
The data is transmitted to the child clock 2 to intermittently advance the display every 30 seconds. Reference numeral 4 denotes a forward/reverse changeover switch which is switched when correcting the display of the slave clock 2 in the backward direction.

5 shows a time display device according to the present invention. The time display device 5 according to the present invention includes a correction pulse generator 6 that stops generating correction pulses while a normal pulse is present, and a correction time memory 7 that stores a correction time.
and a comparator 8 that compares the stored value stored in the correction time memory 7 with the amount of correction by the correction pulse and detects a match between the stored value and the amount of correction, and this comparator 8 outputs a mismatch. This configuration is composed of a state and a gate 9 which sends a corrected pulse to the normal pulse transmission line 3 in a state where no normal pulse exists. In this functional diagram, a counter 10 is provided, and the counter 10 counts the correction pulses to obtain the correction amount, and the comparator 8 compares this correction amount with the correction time stored in the correction time storage 7. The following shows the case where Reference numeral 11 indicates input means constituted by a digital switch for inputting the corrected time value into the memory 7.

According to this configuration, when the corrected time is input into the memory 7, the comparator 8 performs a comparison operation with the counted value of the counter 10. At this time, if the counter 10 is in the initial state, the comparator 8 detects a mismatch. When the comparator 8 detects a mismatch, it outputs an H logic signal in this example, and applies the H logic signal to one input terminal of the gate 9. Therefore, the gate 9 is controlled to be open, outputs the correction pulse output from the correction pulse generator 6, and provides the correction pulse to the slave clock 2 through the gate 9. On the other hand, a correction pulse is applied to a counter 10 to count the amount of correction. When this amount of correction matches the correction time stored in the correction time storage 7, the comparator 8 outputs an L logic and closes the gate 9 to complete the correction.
If the slave clock 2 is being corrected in the forward direction and a regular pulse is output from the master clock 1, the operation of the correction pulse generator 6 is stopped, the supply of correction pulses is cut off, and the regular pulse is output. The child clock 2 is given the regular time. When the regular pulse period has elapsed, the correction pulse generator 6 starts operating and performs correction again. In this way, even if a regular pulse is generated during correction, the regular pulse can be applied to the slave clock 2 so that the timing during correction can be executed correctly.

On the other hand, if the correction has been made in the retarded direction, the forward/reverse selector switch 4 is switched to drive the child clock 2 in the reverse direction and the switch 13 is turned on. switch 1
3 is a switch that provides a regular pulse to the counter 9; Therefore, when a regular pulse is generated during correction in the delay direction, the regular pulse is applied to the slave clock 2 and drives the slave clock 2 in the delay direction by one pulse, that is, 30 seconds. A normal pulse is applied to the two-pulse counting terminal 10A (a terminal that increments the count value by two when one pulse is applied) to increment the count value of the counter 9 by two. As a result, the amount of correction is reduced by two pulses, and the amount by which the child clock 2 is driven in the delay direction by one pulse due to the regular pulse is corrected, and the amount by which it should normally be stepped in the normal direction is corrected, and the amount of correction is reduced by two pulses. The structure is such that correct correction can be made even if a regular pulse is applied during correction.

"Embodiment" FIG. 2 shows an embodiment of the present invention. 1st in the diagram
Portions corresponding to those in the configuration diagram in the figure are designated by the same reference numerals. The master clock 1 has a 0 second signal terminal 1A and a 30 second signal terminal 1B, and the 0 second signal terminal 1A and the 30 second signal terminal 1B are connected to the regular pulse transmission line 3. In this example, the malfunction prevention circuit 1 is connected to the regular pulse transmission line 3.
An example in which 4 is provided is shown below. This malfunction prevention circuit 14 includes, for example, a J-K flip-flop 14A and a J-K flip-flop 14A.
Two AND gates 14B and 14C that are alternately controlled to open and close by the output of the flip-flop 14A.
Noah Gate 14D that takes out the 0 second signal and 30 second signal
And the 0 second signal extracted from this Noah Gate 14D.
The 30 second signal is connected to the clock terminal of the J-K flip-flop 14A and the two AND gates 14B and 14C.
The OR gate 14E is configured by the OR gate 14E. This malfunction prevention circuit 14 causes a 0 second signal or
Even if either one of the 30-second signals is output twice in a row, the second signal is blocked to prevent malfunction. This effectively operates when a regular pulse is output using a manual contact provided on the master clock 1, and this malfunction prevention circuit 14 simply transmits a regular pulse regardless of the operation of the time adjustment circuit 5, which will be described later. Do the following. Therefore, even if the time adjustment device 5 were to malfunction and become inoperable, normal pulses would not become incapable of being transmitted, and the reliability of the timekeeping operation is ensured.

In other words, as shown in FIGS. 3A and 3B, when the 0 second signal P a and the 30 second signal P _b are alternately input to the 0 second signal terminal _1A and the 30 second signal terminal 1B at 30 second intervals, the Noah gate 14D A pulse P _c shown in Figure C is output.

The pulse P _c is applied to the clock input terminal CK of the JK flip-flop 14A and one input terminal of each of the two AND gates 14B and 14C through the OR gate 14E.

By applying the pulse P _c to the clock input terminal CK of the J-K flip-flop 14A,
The -K flip-flop 14A inverts its state at each rising timing of the pulse P _c as shown in FIGS. 3D and 3E, and rectangular waves P _d and P _e are output from the output terminal Q.

These square waves P _d and P _e are connected to two AND gates 14
Since the pulse P c is applied to one input terminal of each of the two AND gates 14B and 14C, and the pulse P _c is applied from the OR gate 14E to the other input terminal of the two AND gates 14B and 14C, the AND gates 14B and 14C have a 0 second signal.
Outputs a signal for 30 seconds. In the illustrated example, the AND gate 14C outputs the 0 second signal P _g shown in FIG. 3G, and the AND gate 14B outputs the 30 second signal P _f .

In this way, the 30 second signal P _f and the 0 second signal P _g output from the AND gates 14B and 14C are connected to the 0 second signal terminal 1A and 30 regardless of the presence of the time adjustment circuit 5.
The signal output to the second signal terminal 1B has its polarity inverted and is input to the polarized signal generating amplifier 15. Therefore, the malfunction prevention circuit 14 can be considered equivalent to the inverter connected in series to the regular pulse transmission line 3 in FIG. As described above, in this invention, since a gate circuit that opens and closes in order to inject a time adjustment pulse into the regular pulse transmission line 3 is not inserted in series, the connection state of the regular pulse transmission line 3 can be changed regardless of the operation of the time adjustment circuit 5. can be ensured, and even if the time adjustment circuit 5 breaks down, an accident such as a failure to send regular pulses to the slave clock 2 will not occur.

As usual, a polarized signal generation amplifier 15 is connected to the regular pulse transmission line 3, and converts the 0 second signal and 30 second signal into positive and negative polarized signals, as well as into a polarized pulse having a predetermined level. , and is supplied to the child clock 2. In this example, the forward/reverse changeover switch 4 uses a relay contact. This relay contact is switched and controlled by a relay 16, which will be explained later.

In this example, the correction pulse generator 6 in the time adjustment device 5 is constructed from a binary counter 6A, three NAND gates 6B, 6C, and 6D, and an inverter 6E. A normal pulse taken out by a NOR gate 14D constituting a malfunction prevention circuit 14 is applied to a reset terminal R of the binary counter 6A, and the counting operation of the binary counter 6A is reset and stopped at the time when the normal pulses of 0 seconds and 30 seconds exist. The NAND gate 6B detects the point in time when, for example, 24 seconds have passed after the regular pulse ends, and
A case is shown in which the gate 6D is controlled to close and the clock supply to the binary counter 6A is stopped from the time point when seconds have elapsed. The correction pulse is taken from output terminal Q ₂ and applied to one input terminal of gate 9. This regular pulse can be, for example, a pulse with a period of 1 second and a pulse width of 0.5 seconds.

7 indicates a correction time memory. In this example, a down counter with a preset function is used, and this down counter also constitutes means for counting the amount of correction. Reference numeral 11 indicates an input means for inputting the correction time into the correction time storage 7. This input means 11 can be constituted by two digital switches 11A and 11B. Digital switch 11A
constitutes a setter for the 1st digit of the minute, and 11B constitutes a setter for the 10th digit of the minute. When the start switch 17 is turned on, one pulse of positive polarity is output from the monostable multivibrator 18, and this pulse is applied to the preset command terminal PE that constitutes the correction time memory 7, and the digital value set in the input means 11 is output. is preset in the corrected time memory 7.

The correction time memory 7 can be constructed by cascading two down counters 7A and 7B having a preset function. 7A memorizes the value of the minute digit,
The stored value is counted down by the correction pulse, and 7B stores the value in the 10th place of minutes, and the stored value is counted down by the correction pulse.

The subtraction outputs of the memories 7A and 7B are given to the comparator 8. The comparator 8 uses a numerical comparator 8A with two input terminals A and B for comparing the values in the 1st digit of the minute, but in this example, when a NAND gate 8B is used as the comparator for the 10th digit of the minute. shows. That is 10 minutes
In this case, it is only necessary to detect that the subtraction result in the memory 7B becomes zero, so it can be configured by, for example, a NAND gate 8B. When all the subtraction values in the memory 7B become "0", the NAND gate 8B is By outputting this H logic and applying this H logic to the comparator 8A, it is possible to detect that the correction of the 10th place of minutes has been completed.

The count output of the counter 19 is given to the B input terminal of the comparator 8A in the first place. This counter 19 is the first
The function is somewhat different from the counter 10 explained in the figure. In other words, this counter 19 is held in a reset state during correction in the forward direction, and gives all "0"s to the input terminal B of the comparator 8A. Yotsutte memory device 7A
When the values become all "0" due to the subtraction operation, the modification is completed and the comparator 8A outputs H logic.

On the other hand, during the correction in the delay direction, the counter 19 counts the regular pulses generated during the correction, and a coincidence is detected before the count value in the memory 7A becomes all "0". In other words, the actual correction time is shortened from the set correction time according to the number of normal pulses, and as a result of this operation, the normal pulse is given during correction in the lag direction, and the display on the slave clock 2 is delayed by 30 seconds. Even if it is driven by the counter 19, the delay corresponding to the
The timing of coincidence detection becomes faster and corrected by the value counted.

Here, the correction pulse given to the memory device 7 will be explained. The correction pulse given to memory 7 is gate 1
The frequency of the 1-second period pulse outputted from 2 is reduced to 1/2 by a flip-flop 21, and the frequency-divided signal is given to the memory 7. By doing this, when two correction pulses are applied to the slave clock 2, the subtraction output of the memory 7A is decreased by one. In other words, when the child clock receives two correction pulses, the display is corrected by one minute. Since the memory device 7A stores the value of the first minute,
In this way, the correction amount of the child clock 2 and the subtraction value of the memory device 7 are matched. However, at this time, conveniently, a normal pulse is output during the correction in the delay direction, and when the counter 19 counts one, when there is only one value left in the memory 7A, the comparator outputs the normal pulse. 8A outputs a coincidence signal. This timing shift corresponds to the time for two correction pulses output from the correction pulse generator 6, and as a result, when the child clock 2 is being corrected in the lag direction, a normal pulse is generated, causing the slave clock 2 to move in the lag direction. Even when driven, two correction pulses are removed from the correction amount and correct correction is performed.

Reference numeral 22 indicates a flip-flop for opening and closing the gate 9. This flip-flop 22 uses a D-type flip-flop, and provides the output signal of the output terminal _Q3 of the binary counter 6A to the clock terminal, and the normal pulse taken out from the NOR gate 14D and the output signal of the output terminal Q of the other D-type flip-flop 23 to the reset terminal. give a signal. Therefore, flip-flop 22 is reset while normal pulses are being output. The output from the output terminal of the flip-flop 22 is applied to the gate 9. Since the gate 9 is a NAND gate in this example, when the flip-flop 22 is reset, an H logic signal is applied to one input terminal of the gate 9, and the gate 9 is controlled to be closed. When the normal pulse ends, the reset of the flip-flop 22 is released, and at this time, H logic is input to the data input terminal D of the flip-flop 22 while the comparator 8 is outputting a mismatch. Yotte Flip Flop 2
2 reads H logic 2 seconds after the end of the regular pulse by a 2 second cycle pulse output from the output terminal Q ₃ of the binary counter 6A, thereby dropping the output terminal to L logic and opening the gate 12 again. Control and continue corrective action.

The flip-flop 23 performs an operation to return the flip-flops 21, 22, the memory 7, and the forward/reverse switching control flip-flop 24 to their initial states when the time adjustment operation is completed. That is, when the count values of the memory 7 and the counter 19 match in the comparator 8, the comparator 8 outputs H logic. Therefore, at this time, it is converted into an L logic signal by the inverter 25, and this L
A flip-flop 23 reads the logic signal. Therefore, the output terminal becomes H logic, and an H logic signal is applied to the reset terminals R of flip-flops 21 and 22 to return them to the initial state.

On the other hand, at this time, all inputs of the NAND gate 26 are L.
The NAND gate 26 outputs H logic. Therefore, an H logic signal is applied to the reset terminal R of the memory 7 and the set terminal S of the flip-flop 24, thereby resetting the memory 7 to the initial state and returning the flip-flop 24 to the set state. When the flip-flop 24 returns to the set state, the relay 16 is deenergized and the changeover switch 4 is returned to the normal rotation side. The timing at which the relay 16 is deenergized is delayed by the timing from when the comparator 7 detects a match until the flip-flop 23 reads the match output. flipflop 2
Since the coincidence detection pulse 3 is read by a pulse having a period of 2 seconds, the contact 4 is returned to the normal rotation direction with a delay of at least 2 seconds from the time when the comparator 7 detects a coincidence. Therefore, since the switch 4 is switched at least 2 seconds after the reverse correction pulse is applied to the slave clock 2, the switching is performed when the reverse power in the slave clock 2 has sufficiently attenuated.

(Operation of Main Parts) In the normal mode, the gate 9 is kept closed, and regular pulses are transmitted from the master clock 1 to the slave clock 2 through the regular pulse transmission path 3.

For a correction operation in the forward direction, a correction time is set in the input means 11 and the start switch 17 is turned on. By operating this switch, the monostable multivibrator 18 outputs a positive pulse, and the time value set in the input means 11 is preset in the memory 7. With this preset, flip-flop 24 is reset and provides a reset signal to counter 19.
Therefore, the counter 19 outputs all "0"s, and inputs all "0s" to the input terminal B of the comparator 8.

Comparator 8 compares the value of memory 7 with the value of counter 19 and outputs a mismatch signal, that is, an L logic signal, which is converted to H logic by inverter 25 and applied to data terminals D of flip-flops 22 and 23. As a result, flip-flops 22 and 23 read H logic. When flip-flop 22 reads H logic, L logic is given to gate 9, and gate 9
opens and 1 is output from binary counter 6A.
And gates 14B and 14
C, and a correction pulse with a period of 1 second is given to the slave clock 2. At this time, when the correction pulse is output, the normal pulse is given to the slave clock 2, and the slave clock 2 advances by one step. At the same time, the flip-flop 22 receives a pulse P _c (third
Since it is reset by Figure C), H is applied to gate 9.
Logic is applied, gate 9 is closed and the sending of correction pulses is suspended. If the comparator 8 does not detect a match when the normal pulse falls, the flip-flop 22 reads H logic again, opens the gate 9, and continues the correction.

When 24 seconds have elapsed since the fall of the normal pulse, the NAND gate 6B detects this and closes the gate 6D, cutting off the clock supplied to the binary counter 6A and interrupting the operation of the binary counter. Therefore, a regular pulse is generated after a gap of 4 seconds,
Drive the child clock 2. Modification pulse P _h applied to AND gates 14B and 14C through gate 9
is shown in Figure 3H. The correction pulse P _h is a signal with a period of 1 second. When one correction pulse P _h is given to the child clock, the display of the child clock 2 is advanced by 30 seconds. However, in the subtraction of the memory 7, since the frequency of the correction pulse is divided by 1/2 by the flip-flop 21, two correction pulses P _h are outputted, and a count value corresponding to one minute is subtracted. Regular pulse when the correction time value is large.
The corrective action is performed distributed over several periods of P _a .

During the correction, the light emitting element 27 lights up to indicate that the correction is in progress.

On the other hand, to correct in the direction of delay, turn on the switch 28 and set it to reverse. When the start switch 17 is turned on in this state, the correction time is input to the memory 7 in the same way as described above, and an H logic signal is sent from the AND gate circuit 29 to the flip-flop 24.
is applied to the reset terminal R of the flip-flop 24 to reset the flip-flop 24. For this reason, the relay 16 is energized and switches the switch 4 to the reverse side. Further, the light emitting element 31 lights up to indicate that the vehicle is traveling in reverse. Further, when the flip-flop 24 is reset, an L logic signal is applied to the reset terminal R of the counter 19, and the reset state of the counter 19 is released. Therefore, when correcting in the direction of delay, the normal pulse
When P _a is output, the counter 19 counts the regular pulses, shortens the amount of correction as described above, and operates to perform correct correction.

``Effects'' As described above, according to the present invention, no gate circuit for correction is inserted into the regular pulse transmission path, so even if the correction circuit 5 fails, the transmission path between the master clock 1 and the slave clock 2 remains unchanged. maintained in normal condition.
Therefore, the relationship between the parent and child clocks is not affected by a failure of the time adjustment device 5, and reliability can be improved.

It is true that the gate 9 provided at the output of the time adjustment device 5
If the circuit fails while still outputting H logic, the gates 14B and 14C provided in the malfunction prevention circuit 14 remain open, causing trouble in the transmission of normal pulses.

However, flip-flop 22 and counter 6A
is always reset every 30 seconds by the regular pulse P _c (Figure 3C), so H logic is always given to one input terminal of the gate 9 from the output terminal of the flip-flop 9, and in this state, the gate 9 is always maintained in a closed state.

The flip-flop 22 reads H logic and the gate 9 is opened only when the comparator 8 detects a mismatch. are extremely rare.

Therefore, it is clear that the probability of failure when both input terminals of the gate 9 are in the L logic state is extremely low, and it will be understood that the reliability of the time adjustment device according to the present invention is high in this respect.

Further, as in the above embodiment, a blank time period is provided before the regular pulse is output during correction, so there is no interference between the corrected pulse and the normal pulse, and malfunctions are prevented.

In addition, the switch 4 is returned to its original state after a gap of 2.0 seconds after the comparator 8 outputs a match signal when the correction is completed after the correction is made in the direction of delay. Since the switch 4 is switched when the power has sufficiently subsided, the structure is such that malfunctions are prevented from occurring in this respect as well.

[Brief explanation of drawings]

Figure 1 is a block diagram for explaining the configuration of this invention, Figure 2 is a connection diagram for explaining an embodiment of this invention, and Figure 3 is a waveform diagram for explaining the operation of Figure 2. be. 1: Master clock, 2: Child clock, 3: Regular pulse transmission line, 4: Forward/reverse switch, 5: Time adjustment device,
6: Modified pulse generator, 7: Memory, 8: Comparator, 9: Gate, 11: Input means.

Claims (1)

[Claims] 1 A A regular pulse is taken in from a regular pulse transmission line, a predetermined time is measured while the regular pulse exists and from the fall of the regular pulse, and a fixed time correction pulse is generated before the rise of the next regular pulse. A correction pulse generator that stops the generation of B. A correction time memory that stores the time to be corrected; C A correction pulse generator that compares the memory value stored in this correction time memory with the amount of correction by the correction pulse and corrects the stored value. D: a comparator for detecting coincidence with the amount; A time adjustment device consisting of.