JPH0243338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device. The device structure of the present invention is smaller than the conventional structure and is more suitable for high-speed operation.

[Conventional technology]

The semiconductor device whose cross-sectional structure is shown in FIG. 1 is a conventional bipolar transistor used in semiconductor integrated circuits (ICs, LSIs).

Taking an npn transistor as an example, the structure of a conventional transistor is such that a p-type base region 14 is formed in an n-type Si epitaxial layer 13 provided on a p-type Si substrate 11, and further an n-type base region 14 is formed in the base region 14. This is obtained by forming a mold emitter region 15. In the figure, 12 and 12' are an n ⁺ -type buried layer and a collector electrode extraction n ⁺ -type diffusion region, and 16 is a p-type region for isolation from adjacent elements.

[Problem that the invention seeks to solve]

In this way, in the conventional device structure, the active region and the inactive region of the transistor are all separated by a pn junction, which has the following main drawbacks.

Since the capacitance between the inactive region in the base region and the collector region is large, power consumption is large and it is unsuitable for high-speed operation.

Since the base region 14, emitter region 15, n ⁺ type diffusion region 12', and isolation region 16 are formed by independent optical etching steps,
The design must take into account the margin due to the alignment accuracy of each photomask. Therefore, the element area becomes large.

In the above, the issue of capacity is particularly important.

In other words, speed and power consumption, which are the basic indicators for expressing the performance of integrated circuit devices, are based on the current value of the transistor used and the static electricity of the element, including the parasitic elements that need to be charged and discharged with this current. It is determined by the capacitance. For a given current value,
The amount of power required to operate a transistor is proportional to this capacitance value, so the smaller the capacitance value, the better. Furthermore, for a given internal resistance, the RC time constant of the transistor is proportional to this capacitance, so in order to increase the operating speed of the transistor, the capacitance value must be reduced.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of conventional semiconductor devices, and to provide a semiconductor device such as a bipolar transistor that has low power consumption, high speed, and small element area.

[Means and actions for solving problems]

Another object of the present invention is to provide a semiconductor device which reduces parasitic capacitance by isolating the outside of the active region of the semiconductor device with an oxide film and has a higher breakdown voltage.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

Example 1 FIG. 2 shows a cross-sectional structure of a first example of the semiconductor device of the present invention.

The bipolar transistor of the present invention shown in the first embodiment uses a polycrystalline silicon layer 28 to form an inactive base region on an insulating film 27, thereby eliminating the drawbacks of the conventional device described above. The emitter region is formed by a self-alignment method, eliminating the above-mentioned drawbacks of the conventional device. The device according to the present invention enables high speed and miniaturization by making the active region of the transistor convex. Note that if the structure in the figure is an npn transistor, 21, 22, 22', 23, and 26 are each p-type.
These are a Si substrate, an n ⁺ type buried layer, an n ⁺ type high concentration region, an n type epitaxial layer (collector regions 22, 22', and 23), a p type isolation region, 24, 25,
27, 28, 29, and 20 are respectively a p-type base region, an n-type emitter region, an oxide film (SiO ₂ film, etc.),
These are a p-type external base region made of polycrystalline Si, an interlayer insulating film (SiO ₂ film, etc.), and an electrode.

FIG. 3 shows the manufacturing process of the semiconductor device according to this embodiment, and shows the state before the cross-sectional structure of FIG. 2 is obtained. The manufacturing process will be explained below according to the drawing numbers. Figure 3a: An n ⁺ type buried layer diffusion 32 is performed on a p type Si substrate 31, an n type Si epitaxial layer 33 is grown, a p type isolation region 36 is formed, and an insulating film other than a silicon oxide film is formed on the entire surface. A film, for example a silicon atomized film (Si ₂ N ₄ ), is deposited and etched to leave the silicon atomized film 301 only in the active portion of the transistor. Furthermore, using 301 as a mask, the silicon epitaxial layer is etched so that the active portion becomes convex. At this time, due to etching,
The silicon layer is made to enter inside the edge of the mask 301. Then, by thermal oxidation, the acid small film 3
7 is formed, and further a metal etc. 302 is vapor-deposited. At this time, the oxide film formed under the mask 301 is not covered with the metal 302.

Figure 3b: The oxide film in the lower part of the mask 301 that is not covered by the mask 302 is removed by etching, the mask 301 is further removed, a polycrystalline silicon layer is formed on the entire surface, p-type impurities are diffused, and the pattern is to open the external base region 38. At this point, only the side surfaces of the convex portion of the epitaxial layer are in contact with the polycrystalline silicon layer. Note that instead of depositing a polycrystalline layer over the entire surface, it is also possible to form the silicon layer 38 by a selective epitaxial method, and in this case, patterning of the silicon layer becomes unnecessary. Next, SiO ₂ film 3 is used as an interlayer insulating film.
Deposit 9.

FIG. 3c: The oxide film 301, polycrystalline silicon 38, and oxide film 39 on the active region are removed by a lift-off method, and p-type impurities are diffused to form an internal base region 34. FIG. Next, thermal oxidation is performed to oxidize the external base region 34'.

FIG. 3d: An n-type emitter region 35 is formed.
Thereafter, the element shown in FIG. 2 can be formed by opening contact holes in the collector region and base region and depositing electrodes.

Embodiment 2 FIG. 4 is an embodiment in which the device structure according to the present invention is applied to an integrated injection logic circuit (IIL circuit).
As shown in the figure, the IIL circuit can be easily constructed by using the epitaxial layer 23 as the emitter and the epitaxial layer 25 as the collector in FIG.

In the figure, 41 is a p-type Si substrate, 42 is an n-type buried layer, 43 is an n-type epitaxial layer, 44 is a p-type region, 45 is an n-type region, 47 is an oxide film, and 48 is polycrystalline silicon. layer (p type), 49 is an interlayer insulating film, 4
0 is an electrode, I is an injector terminal, B is a base terminal, and C ₁ and C ₂ are collector terminals.

Embodiment 3 FIG. 5 shows another manufacturing method for realizing the device structure according to the present invention. The manufacturing method is shown below.

Figure 5a: n ⁺ type buried layer 52 on p type Si substrate 51
and grow an n-type Si epitaxial layer 53.
A p-type isolation region 56 is also formed. On the epitaxial layer, a silicon oxide layer 501, a silicon nitride film 502, and a low resistance polycrystalline silicon layer (which can be p-type or n-type, but in this case the one containing a high concentration of phosphorus atoms) is formed. ) 503, deposit a high concentration glass layer (phosphorus glass here) 504, pattern it by photo-etching as shown in the figure, and further use this multilayer film as a mask to etch the silicon epitaxial layer into a convex shape. . Next, an oxide film 506 is formed by thermal oxidation at a high temperature, and a metal material or the like is further deposited from the upper surface in a high vacuum to form 505. At this time, 505 is not deposited on the overhang portion of the multilayer film.

FIG. 5b: The metal material 505 is masked and etched to remove the oxide film at the end of the convex shape. After that, 505 is removed, and high-resistance polycrystalline silicon 507 is deposited on the entire surface and treated at high temperature. Only the top surface and edges of the plate have low resistance.Next, use an etching solution (e.g.
Only 508 is removed using a mixture of hydrofluoric acid, nitric acid, and glacial acetic acid.

FIG. 5c: The end portion of the silicon film 502 is etched (side etched). Next, while diffusing p-type impurities into the polycrystalline silicon 507,
A base electrode extraction region 509 is formed, and then an interlayer insulating film 510 is formed.

FIG. 5d: Using 510 as a mask, the high concentration glass layer 504 and low resistance polycrystalline layer 503 are removed, and further thermal oxidation is performed to form a thick interlayer insulating film 510.
P-type impurity ions are implanted into the entire surface to form a base region 511.

FIG. 5e: Remove the silicon film 502,
Emitter region 5 is formed by ion-implanting n-type impurities.
form 12.

FIG. 5f: After removing the oxide film 501 and further removing a part of the oxide films 506 and 510, the electrode 51 is removed.
3,514,515 is formed. By using 513 as an emitter, 514 as a base, and 515 as a collector, a device structure according to the present invention can be formed.

The features of Examples 1, 2, and 3 described above are as follows.

By creating a convexly etched portion in the silicon epitaxial layer, the external base region is formed on the oxide film to increase speed.

The internal base and emitter are manufactured using the self-alignment method.

By increasing the thickness of the thermal oxide film at 34' in FIG. 3c, the base-emitter breakdown voltage is increased. Note that even if the conductivity type of the element of the present invention is reversed to p or n, the operation is the same. Further, the element isolation regions (such as 36 in FIG. 3a) may be formed of an oxide film.

Embodiment 4 FIG. 6 shows a cross-sectional area of the element structure of a bipolar transistor according to a fourth embodiment of the semiconductor device of the present invention. N-type buried layer 6 on p-type Si substrate 61
2 is formed, and an oxide film 67 with some holes is formed on the oxide film 62. Polycrystalline silicon and single crystal silicon layers are provided on 67 and 62, respectively, and n-type single crystal silicon layer portions 63 and 6
3' and the n-type buried layer 62 form a collector region, 64 a base region, and 65 an emitter region, forming a bipolar transistor. Note that the area 66 is
An isolation region formed by partially oxidizing polycrystalline silicon. As described above, since the external base region of the bipolar transistor according to this embodiment is located on the oxide film 67, the base-collector capacitance is significantly reduced compared to the conventional element. FIG. 7 shows the manufacturing process of the transistor of this example. An n-type layer 72 is formed in a p-type Si substrate 71. Next, an insulating film such as a silicon oxide film 77 is formed on the surface of the substrate, a portion of which is opened, and an n-type epitaxial layer 73 is then formed on the entire surface of the substrate (FIG. 7a). At this time, a polycrystalline silicon layer is deposited on the oxide film 77, and a single crystal silicon layer is deposited on the exposed portion of the substrate crystal. Note that by imparting selectivity to the epitaxial growth conditions, the thicknesses of the polycrystalline and single crystal layers deposited on the surface can be controlled and the surface can be flattened. After that, a part of the silicon deposit layer 73 is oxidized to form an isolation region 76.
form. Note that the isolation region can also be formed by a pn junction. Thereafter, a p-type high concentration diffusion region 74' and an internal base region 74 are formed to reduce the base resistance (FIG. 3b). Next, an n-type region 75 is formed to serve as an emitter region. Note that at this time, if a high concentration n-type layer is simultaneously formed in the collector extraction region 73', it becomes a normal transistor.
If no n-type layer is formed, a Schottky transistor can be manufactured (FIG. 3c). After that, a passivation film 70 is formed, and electrode wirings 78, 7 are formed.
By performing steps 9 and 80, the transistor of the present invention can be manufactured. Note that when a silicon layer is not deposited on the insulating film 77 during epitaxial growth,
Alternatively, if the silicon layer over 77 is later etched away, the isolation region 76 is unnecessary.

FIGS. 8 and 9 show an example of an element structure in which the withstand voltage is increased in a bipolar transistor of the semiconductor device structure of the present invention.

Example 5 (FIG. 8) A p-type epitaxial layer 82 is formed on a p-type Si cover plate 81.
grow. N-type buried layer 83 and n-type region 83'
This separates the collector region from other elements. Further, the region 84 is a collector region, and is a lightly doped n-type conductive region. Furthermore, an epitaxial layer 84,
An oxide film 89 with a hole partially formed is formed on the oxide film 82, and an n-type layer is further deposited. Areas 83', 83, 84,
If 85 and 85' are used as collectors, an npn transistor can be constructed. This structure differs from the device structure shown in FIG. 6 in that the collector region is thick, so that the withstand voltage of the transistor is increased. Note that 88 is an isolation region formed by an oxide film.

Example 6 Similarly, a high breakdown voltage transistor can also be manufactured by using an n-type epitaxial layer. 9th
The figure is a cross-sectional view thereof, and the n-type layer 92 is an epitaxial layer grown on a p-type Si substrate 91.
93 is an n ⁺ type buried layer, and in this element structure,
A p-type isolation region 90 from adjacent elements is required. The manufacturing process after forming the oxide film 99 is the same as that shown in FIG. In addition, 92, 93, 95, 9
5' is an n-type collector region, 96 is a p-type base region,
97 is an n-type emitter region, and 98 is an oxide film isolation region.

Embodiment 7 FIG. 10 shows an embodiment in which the element structure of a semiconductor device according to the present invention is applied to an IIL circuit (integrated injection logic circuit). An oxide film 1 with a hole partially formed on an n-type buried layer 102 formed in a p-type Si substrate 101
07 and deposit a silicon n-type layer thereon. Part of the silicon n-type layer is oxidized to form isolation region 1.
Form 08. P-type impurities are diffused into 106 and 104 to form an injector region and a base region. By forming the n-type region 105 in the base region 104 and forming the collector region of the npn inverse transistor, an IIL circuit in which the external base region of the npn transistor is formed on the oxide film can be constructed. In addition, 10
3' is the base area of the lateral pnp transistor. Further, 103 is an N type region. The IIL circuit configured in this manner has the following features.

Since the external base region is not in direct contact with the emitter region, the ratio of the collector area to the base area is large, and the reverse current amplification factor is large.

Since the external base region is on the oxide film, the base-emitter capacitance is small and high-speed operation can be expected.

Embodiment 8 FIG. 11 shows an embodiment of the device structure of a bipolar transistor in which a deposited layer on an oxide film 110 with holes partially formed is formed by selective epitaxial method. The manufacturing process is the same as that shown in Figure 7, but since this device has a silicon single crystal layer also formed on the oxide film, there are fewer crystal defects in the deposited layer, and the isolation region is formed during epitaxial growth. Since they are formed simultaneously, high density can be achieved. In addition, 111 and 112 are a p-type substrate and an n-type buried layer, 110 and 119 are oxide films, 113',
112, 113 are collector areas, 114, 115
are the base area and emitter area, respectively, and 1
16, 117, and 118 are electrodes in each region.

As described above, according to Examples 4, 5, 6, 7, and 8, a transistor that operates at high speed can be manufactured because the base capacitance can be reduced, and a high-voltage transistor and a high-speed operation IIL circuit can be manufactured in the same manner. Can be configured within the chip.

The features of the embodiments described above are that an oxide film with a hole partially formed is provided on the substrate, a silicon layer is deposited thereon by a normal or selective epitaxial method, and a base/emitter region is formed in the silicon layer. This is a device structure that allows high-speed transistors to be obtained.

Note that the same operation can be performed even when the p-type conductive layer and the n-type conductive layer are reversed in the above embodiments. Furthermore, if the epitaxial layer on the oxide film is of p-type, the base diffusion step can be omitted.

Example 9 A thermally oxidized SiO ₂ film 122 is formed on a low resistance N-type Si substrate 121 in FIG. 12a, followed by a CVD Si ₂ N ₄ film 123.
form. An opening 124 is formed in a part of this two-layer structure insulating film by photo-etching. after that,
When a Si thin film is epitaxially grown using a mixed gas of SiCl, H ₂ , and HCl, single crystal Si is selectively formed only in the opening 124 . The conductivity type of the epitaxial layer is N type like that of the substrate. When the epitaxial layer grows thicker than the thickness of the insulating film, an overhang 125 of single crystal Si grows along the surface of the insulating film, as shown in FIG. 12b. The length of this overhang is approximately equal to the difference between the thickness of the insulating film and the thickness of the Si epitaxial layer grown on the opening, and by controlling the epitaxial film thickness,
It is possible to control the length of the overhang. A thermal oxide film 126 is again formed on the surface of the selectively grown Si epitaxial film thus obtained. After that, only the Si ₂ N ₄ film is treated with a chemical treatment solution (e.g. 160℃
When etching is performed with phosphoric acid), Fig. 12c
As shown in the figure, a gap 127 is formed below the overhang of the Si epitaxial film. A single crystal layer 128 of Si is again formed by selective epitaxial growth. The conductivity type of this layer is the opposite conductivity type to that of the first grown layer, for example p-type. Also in this case, the thickness of epitaxial layer 128 is increased until an overhang is formed. Next, as shown in FIG. 12d, an opening 129 is formed in a part of the oxide film on the surface of the selective epitaxial layer, and a p-type impurity is introduced through this opening by ion implantation or thermal diffusion. A mold conductive layer 130 is formed. This p
The impurity concentration of the p-type conductive layer 130 is the same as that of the p-type conductive layer 12.
It shall be lower than 8. Subsequently, an N-type impurity is introduced through the opening by ion implantation or thermal diffusion to form a highly concentrated n-type conductive electrode 131. The layers thus formed are the collector of the bipolar transistor (selective epitaxial layer 120 directly above the substrate), the base (p-type conductive layer 130),
An external base (p-type epitaxial layer 128) for forming a base electrode and an emitter (n-type conductive layer 13)
1), respectively. After depositing an ordinary electrode metal mainly made of Al, an electrode pattern is formed using a photoetching method, and each emitter electrode 1
32. A basic bipolar transistor is completed with the base electrode 133. The characteristics of this transistor are that the external base for leading out the base electrode is formed on an insulating film, so the collector-base capacitance can be reduced, and that isolation between adjacent transistors can be automatically achieved. It is possible to use a regular Si single crystal wafer as the epitaxial substrate, and the crystallinity of the Si epitaxial layer is much improved compared to the SOS structure, resulting in improved device characteristics, making it possible to realize devices with high speed and high integration density. suitable for

Embodiment 10 FIG. 13 shows an example of a vertical junction field effect transistor, and FIG. 12 has the same structure as that of FIG. 12 except for the step of forming the p-type conductive layer 130. In this case, the p-type conductive layer 128 is the gate, and the n-type conductive layer 13
1' acts as a source, and the substrate 121 acts as a drain. Since the channel width is determined by the width of the opening 124 in the insulating film, it is possible to control it to 0.5 μm or less, and devices with normally-off operation, which was previously difficult to achieve, can be easily obtained, and high-speed, low-temperature devices can be realized. It is extremely useful for realizing low power consumption and highly integrated devices.

Embodiment 11 FIG. 14 shows an example of a MOS field effect transistor, in which a polycrystalline Si gate 134 is formed following the step shown in FIG. 12c by CVD and photoetching. Thereafter, p-type impurities are implanted into the entire surface from the surface by ion implantation to form a p-type conductive layer 135 in the overhang region of the selective epitaxial layer 120 other than directly under the polycrystalline Si gate. The impurity concentration of this conductive layer is approximately equal to the concentration of selective epitaxial layer 128. By forming electrodes mainly made of Al, the gate 136 and the drain 1
37, source 138. In this example, a p-channel transistor has been described, but for an n-channel transistor, the impurity conductivity type in each step may be reversed. Also in this transistor structure, since the source and drain are formed on the insulating film, parasitic capacitance is reduced and high speed is facilitated.

Embodiment 12 As another embodiment, an example of application to I ² L is shown in FIG. 15. FIG. 15a shows the same process as FIG. 12c, but the distance between adjacent transistors is shortened to create a structure in which the external base layer 136 is continuous. Next, in FIG. 15b, a portion of the oxide film on the surface of one of the transistors is removed to form an exposed portion 140 on the surface of the selective epitaxial layer 120. Thereafter, p-type impurities are diffused by ion implantation or thermal diffusion to form a p-type conductive layer 141. continuation,
Similar to the step in FIG. 12d, an opening 142 is provided in the oxide film on the surface of the other epitaxial layer, and p-type and n-type impurities are ion-implanted to form a p-type conductive layer 143 and an n-type conductive layer 144, respectively. form. Thereafter, electrodes mainly made of Al are provided to form the emitter 147 of the injector, the collector of the injector, and the base 14 of the reverse operation transistor.
5, and the collector 1 of the reverse operation transistor.
46. The base of the injector and the emitter of the reverse operation transistor are from the epitaxial substrate. According to the present invention, the base width of the injector can be easily controlled to be narrower than that of conventional lateral transistors, so the efficiency of current injection from the injector to the base of the reverse operation transistor is improved, which has the advantage of reducing power consumption. big. Furthermore, since the parasitic capacitance of the base is small, high-speed operation is significantly improved.

〔Effect of the invention〕

As described above, the present invention facilitates the realization of high-speed operation, high integration, and low-cost transistors and integrated circuits with a structure completely different from conventional ones, and can provide basic technology for realizing various transistors. Therefore, the benefits are great.

In each of Examples 1 to 12 above, examples were shown in which Si was mainly used as the semiconductor, but the device of the present invention can also be realized using other semiconductors such as GaAs.
Furthermore, it goes without saying that the p-type and n-type conductivity types in each embodiment can be reversed.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a bipolar transistor as an example of a conventional semiconductor device, FIG. 2 is a cross-sectional view showing the structure of a bipolar transistor as an example of the semiconductor device of the present invention, and FIG. 2
A cross-sectional view showing the manufacturing process of the transistor shown in Fig. 4.
The figure is a sectional view showing the structure of an IIL which is one embodiment of the semiconductor device of the present invention, FIG. 5 is a sectional view showing another manufacturing process of the transistor shown in FIG. 2, and FIG. 6 is another embodiment of the present invention. 7 is a sectional view showing the structure of an example bipolar transistor; FIG. 7 is a sectional view showing the manufacturing process of the transistor shown in FIG. 6; FIGS.
Figure 0, Figure 11, Figure 12, Figure 13, Figure 14
15 are cross-sectional views showing another embodiment of the semiconductor device of the present invention. 21...p-type Si substrate, 22...n-type buried layer, 2
3...n-type Si epitaxial layer (collector region),
24... p-type base region, 25... n-type emitter region, 26... p-type isolation region, 27... insulating film (SiO ₂ etc.), 28... polycrystalline Si (external base region),
29... Insulating film (SiO ₂ etc.).

Claims (1)

[Claims] 1. First and second convex portions and a lower portion formed by etching a predetermined portion of a surface region of a single crystal semiconductor substrate, and side portions of the first and second convex portions along the bottom of the lower portion. a first insulating film extending into the first convex portion, a first region having a first conductivity type formed within the first convex portion, and the first conductivity formed in contact with the upper and lower surfaces of the first region, respectively. second and third regions having a second conductivity type opposite to the shape of the second convex portion; 1
fourth and fifth regions having conductivity types;
and a sixth region having the second conductivity type interposed between the fifth region and in contact with the fourth and fifth regions, and formed along the surface of the first insulating film,
at least a low-resistance polycrystalline semiconductor film having the first conductivity type electrically connected to the first and fourth regions, and a second insulating film formed on the polycrystalline semiconductor film. A semiconductor device characterized by: