JPH0247035B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a decoder circuit.

In recent years, in semiconductor integrated circuits, due to the advanced development of process technology represented by microfabrication technology, element dimensions have become smaller year by year, and integration density has increased.
The number of elements that can be housed within a chip is now on the verge of reaching 70,000 to 80,000 transistors. As the number of elements that can be accommodated on one chip increases in this way, N-channel enhancement/depletion insulated gate field effect transistors (hereinafter referred to as MOSFETs)
In integrated circuits that are composed of (referred to as ``chip''), their power consumption is enormous, and the internal temperature of the chip increases, which has an adverse effect on the elements, so it becomes necessary to devise circuitry to reduce the power consumption. One of the measures taken to reduce this power consumption is
It is common for circuits to have a dynamic configuration, eliminating the path through which current constantly flows from the power supply to the ground potential, especially for built-in read-only memory (hereinafter referred to as ROM) and random access memory (ROM). The dynamic configuration of the decoder circuit for ROM (hereinafter referred to as RAM) is
If RAM occupies a large proportion of the chip,
Very effective. Also, in RAM, there are three
Uses dynamic cell using MOSFET
Since RAM requires a decoder circuit that outputs two output signals, a read word signal and a write word signal, from a single decoded signal, it particularly needs to have a dynamic configuration.

A conventional example of a decoder circuit having two output signals having such a dynamic configuration is shown in FIG. 1, and signal waveforms at various parts of this circuit are shown in FIG. 2 and will be explained.

In Figure 1, the power supply Vcc is a positive power supply, and considering that the transistor is an N-channel MOSFET, the drain of MOSFET M _o+1 is connected to the power supply,
The source is connected to terminal A, the clock signal φ ₁ is input to the gate, and φ ₁ is at a high level (in this case, the power supply Vcc
Terminal A is precharged to the potential of (Vcc - V _T ) during the period of the same potential as (Vcc - V T ). (V _T is the threshold voltage of the MOSFET.) At this time, at least while φ ₁ is at a high level, the address signals A ₀ , which are the gate inputs of the MOSFETs M ₀ to _{M o} , are used to prevent current from flowing through the MOSFETs M 0 to M o.
The 2 (n+1) signals ~, A _o and ₀ , ~, _o are all at a low level below V _T . In this way, the potential of the terminal A precharged during the high level period of the clock signal _φ1 is at least the same as that of the clock signal _φ1 during the high level period of the clock signal _φ2 , which does not overlap in high level (in this case, higher than V _T ). is determined as follows. In other words, the address signal
A ₀ , ~, A _o , and ~, _o are activated and A ₀ ,
One of _{the paired address signals with A 0 becomes} high level, and the ( _n +
1) If one of the address signals that are the gate inputs of the two MOSFETs becomes high level, the MOSFETs that use that as gate input become conductive, and the potential of terminal A becomes low level. This represents the non-selected state. (α ₁ in Figure 2) Conversely, if all the address signals are at low level, all of M ₀ , ~, M _o
The MOSFET becomes non-conductive and the potential at terminal A remains at a high level, although the transfer gates M _o+5 and M _o+5 become conductive and are lowered due to charge shear. This represents the selected state. (α ₂ in Figure 2). The direct decoding section of the decoder circuit, which is composed of MOSFETs M ₀ , M ₁ , ...M _o , M _o+1, reduces power consumption because there is no current flowing directly from the power supply Vcc _to the ground potential. , _φ2 , precharging and decoding are repeated, respectively. At this time, the potential of terminal B, which is one of the direct outputs of this decoder circuit and is a read word signal, is transferred to transfer gate M _o+2 during the high level period of φ ₂ .
reads the potential of terminal A, and if the read potential during the subsequent high level period of φ ₁ is high level, it works as a push-up circuit and a high level is output to terminal B (β 2 in Fig. ₂ ), but the reverse is true. If the potential read in is low level, M _o+3 is non-conductive and terminal B maintains the low level discharged during the previous φ ₂ period. (β ₁ in Figure 2) At this time, looking at the flow of the write word signal, it is read from terminal A through transfer gate M _o+5 during the high level period of φ ₂ at the same time as the read word signal. The decoded signal is sent to the M _o+6 depletion MOSFET.
M _o+9 is depleted through the transfer gate M _o+8 during the next period when _φ1 is at high level while the read word signal is being output through the inverter configured by the M _o+7 enhancement MOSFET. It is input to an inverter consisting of a MOSFET and an enhancement MOSFET of M _o+10 and is latched, and during the high level period of φ ₂ following the output of the previous read word signal, and during the high level period of the previous φ ₂ . is selected, M _o+12 conducts and outputs a high level; if _{γ 2} in _FIG . The write word signal at terminal E remains at the low level. (γ ₁ in Figure 2) As explained above, in this conventional circuit, the signal decoded from the address signal during a certain high level period of φ ₂ is used as the read word signal B during the next high level period of φ ₁ . It is output as a write word signal E during the next high level period of φ ₂ , but during the same period of φ ₂ in which this write word signal is output, the next address held is M ₀ ,... The circuit is decoded by the direct decoding section of M _o+1 , and _is designed to achieve high time efficiency and is easy to achieve high speed. However, on the _other hand, the write word signal system is Since the inverters are latched and each consists of depletion and enhancement, the output of either inverter is at a low level in this part, and current flows from the power supply to the ground potential, causing M ₀ ，
Although the direct decoding section consisting of ..., M _o+1 has a dynamic configuration to reduce power consumption, it has the disadvantage of increasing power consumption. In addition, since the two transfer gates M _o+2 and M _o+5 read the signal from terminal A, the terminal A when selected and the other
The rate of charge/shuar between MOSFET gate capacitance of M _o+3 and M _o+7 is large, leading to a high level drop, which in turn lowers G _n of M _o+3 and leads to terminal B.・It also had the drawback of causing a decrease in the high-level output speed of word signals.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and it is an object of the present invention to provide a high-speed decoder circuit having two output signals with low power consumption and without the above-mentioned drawbacks.

According to the present invention, in a decoder circuit that generates second and third signals output in different periods from a first signal selected in a certain period, one of the second and third signals is selected first. The second output signal is the gate input, the drain is connected to the first power supply, and the source is connected to the first terminal.
The MOSFET and the second signal are configured by at least a second MOSFET whose gate input is a fourth signal having a different output period and whose drain is connected to the first terminal to latch the second signal. , a decoder circuit characterized by outputting a third signal is obtained.

An embodiment of the present invention will be shown and explained in detail using the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 shows signal waveforms at various parts of the circuit shown in FIG. MOSFET in Figure 3, MA ₀ ,
...Address signal A ₀ configured by MA _o+1 ,
The direct decoding section which inputs gates to any (n+1) of ~A _o or ₀ , ~, _o is the same as the conventional example. The signal decoded from terminal a is MA _o+2
Load at φ ₂ through the transfer gate of
It outputs a high level as a read word signal to terminal b during the next φ ₁ period, if selected, and maintains the low level discharged in the previous φ ₂ period if not selected. However, since there is no read transfer gate from terminal a to the write word signal system, the high level charge share when terminal a is selected is
Only the gate capacitance of MA _o+3 , its proportion is small,
This has the advantage of increasing the Gm of MA _o+3 without causing a significant drop in the high level, and increasing the speed of outputting the high level to terminal b.

To explain the write word signal system, the signal output to terminal b during the period of φ ₁ is the gate input, and the high level signal selected by MOSFET MA _o+5 whose drain is the power supply Vcc is output to terminal b. In this case, a high level of (Vcc - V _T ) _is applied to terminal C.
MA _o+8 is made conductive and latched, and a high level is output as a write word signal to terminal d during the following period φ ₂ .

Conversely, if the non-selected low level is maintained at terminal b for a period of _φ1 , MA _o+5 is non-conductive, and
It is almost the same as φ ₂ , but the second half of the high level is extended, and the low level previously discharged by MA _o+6 with the gate input of clock signal φ _p is maintained, and this level is transferred to MA _o+7. Latched by the agate, MA _o+8 becomes non-conductive, and the low level discharged during the previous period _φ1 is maintained at the terminal d. As mentioned above, in the present invention,
The depletion MOSFET is not used, and MA _o+5 and MA _o+6 input the selected terminal b signal while both φ ₁ and φ _p are at high level.
There is only one case out of 2 ⁿ⁺¹ decoders in which current flows through the decoder, and it will be understood that power consumption has been significantly reduced compared to the conventional decoder.

As described above, according to the present invention, it is possible to obtain a decoder circuit using two output signals having different output periods with low power consumption and high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional two-output decoder circuit. FIG. 2 is a waveform diagram of each terminal of the conventional circuit shown in FIG. FIG. 3 is a diagram showing a two-output decoder circuit as an example of the present invention. FIG. 4 is a waveform diagram of each terminal of the decoder circuit according to the present invention shown in FIG. M ₀ ~ _{M o +5} , M _{o +7} , M _{o +8} , M _{o +10} ~ _{M o +13} ,
MA ₀ to _{MA o+9} ... enhancement transistors. M _o+6 , M _o+9 ... depletion transistors.

Claims (1)

[Claims] 1. In a decoder circuit that sequentially generates second and third signals in different periods from a first signal selected in a certain period, the second signal is used as a gate input, and the first power supply and the first signal are connected to each other. A first insulated gate field effect transistor (hereinafter referred to as MOSFET) connected between the terminals and a fourth signal having an output period different from the second signal as the gate input and connected to the first terminal. Second MOSFET
A decoder circuit comprising: latching a second signal and outputting a third signal.