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JPH0247866B2 - - Google Patents
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JPH0247866B2 - - Google Patents

Info

Publication number
JPH0247866B2
JPH0247866B2 JP56037606A JP3760681A JPH0247866B2 JP H0247866 B2 JPH0247866 B2 JP H0247866B2 JP 56037606 A JP56037606 A JP 56037606A JP 3760681 A JP3760681 A JP 3760681A JP H0247866 B2 JPH0247866 B2 JP H0247866B2
Authority
JP
Japan
Prior art keywords
floating gate
type
present
integrated circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56037606A
Other languages
Japanese (ja)
Other versions
JPS57152164A (en
Inventor
Yasutaka Nakasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP56037606A priority Critical patent/JPS57152164A/en
Publication of JPS57152164A publication Critical patent/JPS57152164A/en
Publication of JPH0247866B2 publication Critical patent/JPH0247866B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/812Charge-trapping diodes

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)

Description

【発明の詳細な説明】 本発明は、半導体集積回路に関し、特に浮遊ゲ
ートを用いた不揮発性記憶素子を複数個用いた半
導体集積回路である。また本発明は、PLA方式
の回路に用いるに容易な素子の考案である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit using a plurality of nonvolatile memory elements using floating gates. The present invention also devises an element that is easy to use in a PLA type circuit.

本発明の目的は、PLA方式の回路など高集積
な集積回路に面積の増加が殆んどなく容易に適用
可能な素子を提供するとともに、それを用いた集
積回路、PLA方式による回路等を提供せんとす
るものである。従来これらの素子及び回路構成と
しては、配線材の溶断によるものやFAMOSと呼
ばれる浮遊ゲートをもつトランジスター等により
形成されてきた。溶断タイプのものやダイオード
破壊タイプのものは、書換え不可の点と電流大の
点に難がある。またFAMOSタイプのものは、ト
ランジスターを構成する必要性から高集積化に不
向きである。以上の欠点を取り除く目的で本発明
が考案された。
An object of the present invention is to provide an element that can be easily applied to highly integrated circuits such as PLA type circuits with almost no increase in area, and to provide an integrated circuit using the same, a PLA type circuit, etc. This is what I am trying to do. Conventionally, these elements and circuit configurations have been formed by fusing wiring materials, transistors with floating gates called FAMOS, and the like. The fusing type and the diode destruction type have disadvantages in that they cannot be rewritten and require a large current. Furthermore, FAMOS type devices are not suitable for high integration because they require transistors to be configured. The present invention was devised to eliminate the above drawbacks.

本発明の一部をなす記憶素子を第1図に示す。 A memory element forming part of the present invention is shown in FIG.

第1図で、1はN型基板、2はN型拡散層、3
はP型拡散層、4は酸化膜、5は多結晶シリコン
膜による浮遊ゲート、6は配線である。
In Figure 1, 1 is an N-type substrate, 2 is an N-type diffusion layer, and 3 is an N-type substrate.
4 is a P-type diffusion layer, 4 is an oxide film, 5 is a floating gate made of a polycrystalline silicon film, and 6 is a wiring.

この素子の動作は、浮遊ゲート内に電荷が蓄積
されているかどうかで、拡散層3近傍の空乏層が
変化し接合耐圧が上下することを利用したもので
ある。浮遊ゲートへの注入は、接合降伏電流の一
部が、高いエネルギーを得て浮遊ゲートへ到達す
ることでなされる。この時の注入量は、電圧に対
して依存し、また電流も一定以上必要である。
The operation of this device utilizes the fact that the depletion layer near the diffusion layer 3 changes depending on whether or not charges are accumulated in the floating gate, and the junction breakdown voltage rises and falls. Injection into the floating gate is achieved by a portion of the junction breakdown current reaching the floating gate with high energy. The amount of injection at this time depends on the voltage, and the current also needs to be above a certain level.

第2図は注入前の空乏層7を示し、第3図は注
入後の空乏層8を示す。接合破壊耐圧はこの空乏
層の巾に反比例することから、第4図のそれぞれ
9,10の特性に対応する。各素子に対してそれ
ぞれ第2図、第3図の状態を設け、回路を動作さ
せる時には、電圧をVaとして用いる。Vaの時に
は、9の特性では電流が流れ、10の特性では流
れない。このことにより記憶素子としての機能を
果す。またVa程度の電圧であると逆降伏電流も
小さく、浮遊ゲートに電荷が注入されることはな
い。また素子バラツキで降伏電圧に差がある時に
は、バラツキの中の一番高い降伏電圧がVaより
低くなるようにして拡散濃度や基板濃度を設定し
ておけばよい。この時には、降伏電圧の低いもの
は、降伏電流大のため、浮遊ゲートに電荷が注入
され、全ての素子が、Vaより若干低い電圧に、
降伏電圧が統一される。したがつて本発明の素子
では素子間バラツキを殆んど考える必要がない。
またこの素子の書換えは、浮遊ゲート型MOS
(FAMOS)と同じく紫外線で容易に消去できる。
また本素子は接合と浮遊ゲートのみから形成され
るため、面積も極力小さく抑えられる。
FIG. 2 shows the depletion layer 7 before implantation, and FIG. 3 shows the depletion layer 8 after implantation. Since the junction breakdown voltage is inversely proportional to the width of this depletion layer, it corresponds to the characteristics 9 and 10 in FIG. 4, respectively. The states shown in FIGS. 2 and 3 are provided for each element, respectively, and the voltage is used as Va when operating the circuit. At the time of Va, current flows when the characteristic is 9, and it does not flow when the characteristic is 10. This allows it to function as a memory element. Furthermore, when the voltage is around Va, the reverse breakdown current is small, and no charge is injected into the floating gate. Furthermore, when there is a difference in breakdown voltage due to device variations, the diffusion concentration and substrate concentration may be set so that the highest breakdown voltage among the variations is lower than Va. At this time, devices with a low breakdown voltage have a large breakdown current, so charge is injected into the floating gate, and all the elements are at a voltage slightly lower than Va.
Breakdown voltage is unified. Therefore, in the device of the present invention, there is almost no need to consider variations between devices.
In addition, rewriting of this element is done using a floating gate MOS
Like (FAMOS), it can be easily erased with ultraviolet light.
Furthermore, since this device is formed from only a junction and a floating gate, the area can be kept as small as possible.

PLA方式の回路は、ANDとORとの組み合せ
で構成され、ANDとORをどの配線間で行うかを
選択することで実際に必要な回路を求めるもので
ある。このため本素子のように接合に於ける導
通、非導通を用いる素子は、このようなPLA方
式の回路に最も適しており、面積増加がなく、高
集積で書換え可能な集積回路が提供できる。また
このような素子は、これに限らず広い応用が望め
る。
PLA type circuits are composed of a combination of AND and OR, and the actually required circuit is determined by selecting which wirings to perform AND and OR between. Therefore, an element that uses conduction and non-conduction in junctions, such as the present element, is most suitable for such a PLA type circuit, and can provide a highly integrated and rewritable integrated circuit without increasing area. Further, such an element can be expected to have a wide range of applications, not limited to this.

以上本発明は、高集積で、書換え可能であり、
構造が簡単であるため容易に用いることができ、
素子間バラツキを救うことのできる不揮発性記憶
素子及びそれを複数個集積した半導体集積回路で
ある。
As described above, the present invention is highly integrated, rewritable,
It has a simple structure and is easy to use.
The present invention provides a nonvolatile memory element that can eliminate variations between elements, and a semiconductor integrated circuit that integrates a plurality of nonvolatile memory elements.

【図面の簡単な説明】[Brief explanation of drawings]

第1図…本発明の基本となる半導体記憶素子の
断面図、第2図、第3図…第1図の素子の空乏層
の変化図、第4図…第1図の素子の電気特性図。
Fig. 1... A cross-sectional view of the semiconductor memory element which is the basis of the present invention, Figs. 2 and 3... A diagram of changes in the depletion layer of the element shown in Fig. 1, Fig. 4... A diagram of electrical characteristics of the element shown in Fig. 1. .

Claims (1)

【特許請求の範囲】[Claims] 1 PLA(Programable Logic Array)方式の
集積回路において、半導体基板に設置されたダイ
オード、前記ダイオードの接合部の上に配設され
た誘電体膜、および前記誘電体膜を介して配設さ
れた多結晶シリコン膜から構成される浮遊ゲート
からなることを特徴とする半導体集積回路。
1. In a PLA (Programmable Logic Array) type integrated circuit, a diode is installed on a semiconductor substrate, a dielectric film is placed on the junction of the diode, and a multilayer circuit is placed through the dielectric film. A semiconductor integrated circuit characterized by comprising a floating gate made of a crystalline silicon film.
JP56037606A 1981-03-16 1981-03-16 Semiconductor integrated circuit Granted JPS57152164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56037606A JPS57152164A (en) 1981-03-16 1981-03-16 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56037606A JPS57152164A (en) 1981-03-16 1981-03-16 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS57152164A JPS57152164A (en) 1982-09-20
JPH0247866B2 true JPH0247866B2 (en) 1990-10-23

Family

ID=12502232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56037606A Granted JPS57152164A (en) 1981-03-16 1981-03-16 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57152164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580198B2 (en) 1999-11-30 2003-06-17 Tdk Corporation Surface acoustic wave device having a thin metal oxide film fully covering at least the electrodes and method of fabricating same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814853A (en) * 1996-01-22 1998-09-29 Advanced Micro Devices, Inc. Sourceless floating gate memory device and method of storing data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6580198B2 (en) 1999-11-30 2003-06-17 Tdk Corporation Surface acoustic wave device having a thin metal oxide film fully covering at least the electrodes and method of fabricating same

Also Published As

Publication number Publication date
JPS57152164A (en) 1982-09-20

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