Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH024931B2 - - Google Patents
[go: Go Back, main page]

JPH024931B2 - - Google Patents

Info

Publication number
JPH024931B2
JPH024931B2 JP57171561A JP17156182A JPH024931B2 JP H024931 B2 JPH024931 B2 JP H024931B2 JP 57171561 A JP57171561 A JP 57171561A JP 17156182 A JP17156182 A JP 17156182A JP H024931 B2 JPH024931 B2 JP H024931B2
Authority
JP
Japan
Prior art keywords
processing
completion
requested
processing unit
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57171561A
Other languages
Japanese (ja)
Other versions
JPS5960672A (en
Inventor
Hidemi Takashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57171561A priority Critical patent/JPS5960672A/en
Publication of JPS5960672A publication Critical patent/JPS5960672A/en
Publication of JPH024931B2 publication Critical patent/JPH024931B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Computer And Data Communications (AREA)

Description

【発明の詳細な説明】 (A) 発明の技術分野 本発明は、非同期事象同期化処理方式、特に例
えばデータ処理装置におけるアプリケーシヨン・
プログラムが行なつたnバイト分送信依頼に関す
る終了報告をモニタが間欠的にチエツクする如き
非同期事象同期化処理方式において、モニタが間
欠的に行う一連の複数個の対応処理の間に少なく
とも2回分上記終了報告チエツクを行うよう構成
し、終了報告を早期に受取り得るようにした非同
期事象同期化処理方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to an asynchronous event synchronization processing method, particularly for application processing in, for example, a data processing device.
In an asynchronous event synchronization processing method in which the monitor intermittently checks the completion report regarding the n-byte transmission request made by the program, the above-mentioned event occurs at least twice during a series of multiple response processes intermittently performed by the monitor. This invention relates to an asynchronous event synchronization processing method that is configured to check for a completion report and receive the completion report at an early stage.

(B) 技術の背景と問題点 本発明はそれに限られるものではないが、アプ
リケーシヨン・プログラムが依頼したnバイト分
送信依頼に関する終了報告をモニタが間欠的にチ
エツクする如き非同期事象同期化処理方式におい
ては、次の如き問題が内在している。即ち、間欠
的な動作によつてモニタが上記終了報告をチエツ
クした際には未終了であつたがその直後に終了と
なることがあり、このような場合には、次にモニ
タが、間欠的動作に対応して、該当するチエツク
を行うまで確認が待たされる。
(B) Technical Background and Problems Although the present invention is not limited thereto, it is an asynchronous event synchronization processing method in which a monitor intermittently checks a completion report regarding a request to send n bytes requested by an application program. In this case, the following problems are inherent. In other words, when the monitor checks the completion report due to intermittent operation, it may not have finished, but it may end immediately after that. In such a case, the monitor may Confirmation waits until the corresponding check is performed in response to the operation.

(C) 発明の目的と構成 本発明は上記の点を改善することを目的として
おり、本発明の非同期事象同期化処理方式は、所
定のクロツクに同期して処理を進める同期処理部
と、依頼された処理の終了を上記同期処理部に対
して非同期に報告する非同期処理部とをそなえ、
上記同期処理部が、上記非同期処理部に対して依
頼した処理の終了の有無チエツク処理と当該処理
の終了の無に対応する処理とからなる複数個の対
応処理を間欠的に実行し、上記依頼した処理の終
了を上記クロツクに同期して受取る非同期事象同
期化処理方式において、上記同期処理部が上記間
欠的な実行に対応して、上記同期処理部が、上記
依頼した処理の終了についての第1回目の処理の
終了の有無チエツク処理を実行し、終了無に対応
して上記処理の終了の無に対応する処理を実行し
た後に、上記依頼した処理の終了についての第2
回目の処理の終了の有無チエツク処理を行うよう
構成されてなり、上記複数個の対応処理の間に上
記処理の終了の有無チエツクを少なくとも2回実
行するようにしたことを特徴としている。以下図
面を参照しつつ説明する。
(C) Object and Structure of the Invention The present invention aims to improve the above-mentioned points. an asynchronous processing unit that asynchronously reports the completion of the processed processing to the synchronous processing unit,
The synchronous processing unit intermittently executes a plurality of corresponding processes, including a process of checking whether the process requested to the asynchronous process unit has finished, and a process corresponding to whether the process has ended, and In the asynchronous event synchronization processing method, in which the termination of the requested processing is received in synchronization with the clock, the synchronization processing section receives a notification regarding the termination of the requested processing in response to the intermittent execution. After executing the first process to check whether or not the process has been completed, and in response to the non-completion, executing the process corresponding to the non-completion of the above-mentioned process, the second check process regarding the completion of the requested process is executed.
The present invention is characterized in that it is configured to check whether or not the second processing has been completed, and that the check for whether or not the processing has been completed is executed at least twice between the plurality of corresponding processings. This will be explained below with reference to the drawings.

(D) 発明の実施例 第1図は本発明が適用される一実施例構成、第
2図は第1図図示モニタが行う本発明の同期化処
理の一実施例態様を示す。
(D) Embodiment of the Invention FIG. 1 shows the configuration of an embodiment to which the present invention is applied, and FIG. 2 shows an embodiment of the synchronization process of the present invention performed by the monitor shown in FIG.

第1図において、1は例えば日本語入力装置な
どのマイクロプロセツサ制御装置、2はデイスプ
レイ、3はキーボード、4は回線、5はモデム、
6はモニタ、7はアプリケーシヨン・プログラ
ム、8は回線制御部、9はデイスプレイ制御部、
10はキーボード制御部、11は回線終了情報域
であつて依頼されたnバイト分の送信が終了した
とき非同期に回線制御部8が終了フラグを立てる
もの、12はキーボード上の中断キーであつて先
に依頼したnバイト分送信依頼を中断せしめるた
めなどのものを表わしている。
In FIG. 1, 1 is a microprocessor control device such as a Japanese input device, 2 is a display, 3 is a keyboard, 4 is a line, 5 is a modem,
6 is a monitor, 7 is an application program, 8 is a line control section, 9 is a display control section,
10 is a keyboard control unit, 11 is a line termination information area in which the line control unit 8 sets a termination flag asynchronously when the requested transmission of n bytes is completed, and 12 is an interrupt key on the keyboard. This indicates a request to interrupt a previously requested transmission request for n bytes.

本発明の非同期事象同期化処理方式は、第1図
に関連して説明すると次の如き事態に対応してい
る。即ち、キーボード3からの送信指示に対応し
てアプリケーシヨン・プログラム7がnバイト分
送信依頼を発し、回線制御部8が当該nバイト分
のデータを送信し終つた時点で回線終了情報域1
1に非同期に終了フラグを立てるのを、モニタ6
が間欠的にチエツクを行うが上記事態はこの終了
フラグの存在を確認する事態に対応している。該
モニタによる対応処理は、(i)回線終了情報域11
の内容チエツク、(ii)中断キー12の押下有無のチ
エツク、(iii)モデムが送信可能状態にあるか否かの
モデム状態チエツクを少なくとも含んでおり、モ
ニタ6が間欠的に上記チエツク処理を行うに当つ
て従来から少なくとも上記(i)(ii)のチエツクが付随
して行われている。なお上記(i)のチエツクを本明
細書において「処理の終了の有無チエツク処理」
と呼び、上記(ii)(iii)のチエツクなどを「処理の終了
の無に対応する処理」と呼んでいる。勿論、上記
回線終了情報域11の内容にもとづいて送信終了
が確認されれば当該確認に関連した処理にジヤン
プするようにされる。
The asynchronous event synchronization processing method of the present invention corresponds to the following situation, which will be explained with reference to FIG. That is, in response to a transmission instruction from the keyboard 3, the application program 7 issues a request to transmit n bytes, and when the line control unit 8 has finished transmitting the n bytes of data, the line termination information area 1 is
Monitor 6 sets the end flag asynchronously to 1.
checks intermittently, and the above situation corresponds to the situation in which the existence of this end flag is confirmed. The corresponding processing by the monitor is as follows: (i) Line termination information area 11
(ii) checking whether the interrupt key 12 has been pressed; (iii) checking the modem status to see if the modem is in a transmittable state; the monitor 6 intermittently performs the above checking process. Conventionally, at least the checks (i) and (ii) above have been carried out in conjunction with this. In this specification, the check in (i) above is referred to as "processing to check whether processing is completed".
, and the checks in (ii) and (iii) above are called ``processing corresponding to no termination of processing.'' Of course, if the completion of transmission is confirmed based on the contents of the line termination information area 11, the process jumps to the process related to the confirmation.

第2図は第1図図示モニタが行う本発明の同期
化処理の一実施例態様を示している。なお従来の
場合、図示判定が存在せず図示ルートAを通つ
ていたと考えてよい。
FIG. 2 shows an embodiment of the synchronization process of the present invention performed by the monitor shown in FIG. Note that in the conventional case, it may be considered that the illustrated route A was taken without the illustrated determination.

本発明の場合、上記(i)に対応する回線終了情報
域11の内容チエツク(図示「判定」)が少なく
とも2回(即ち判定と判定)行われる。そし
て、図示の「完了待ちのための処理」は、上記(ii)
に対応する中断キー12の押下の有無チエツクや
(iii)モデムが送信可能状態にあるか否かのモデム状
態チエツクに対応する処理と考えてよい。第2図
図示の場合、判定の際に上記終了フラグが立つ
ていなかつたとし判定までの間にフラグが立て
られたとすると、所定の待ち時間を非所望に経過
してしまうことなく、終了フラグの存在をモニタ
6が確認することが可能となる。
In the case of the present invention, the content check (determination shown in the figure) of the line termination information area 11 corresponding to (i) above is performed at least twice (i.e., determination and determination). The "processing for waiting for completion" shown in the figure is described in (ii) above.
Check whether the interrupt key 12 corresponding to the button is pressed or not.
(iii) This process can be considered to correspond to checking the modem status to determine whether the modem is in a transmittable state. In the case shown in Fig. 2, if the end flag is not set at the time of determination, but if the flag is set before the determination, the end flag can be set without undesired elapse of the predetermined waiting time. It becomes possible for the monitor 6 to confirm the existence.

従来から間欠的にチエツクを行うようにしてい
る理由は、高頻度で繰返しチエツクを行つてもそ
れ程には効果がないということもあるが、上記(ii)
に対応するチエツクが上記(iii)に対応するチエツク
を行つており、それらのチエツクのために要する
時間を確保することが必要であるということもあ
る。上記間欠的にチエツクを行う周期に占める上
記後者の理由に対応したチエツクのために要する
時間が比較的大であるようなシステムであつて、
上記(i)に対応するチエツクに要する時間にくらべ
て上記(ii)(iii)に対応するチエツクに要する時間が大
であるシステムにおいては、効率のよい動作とな
る。
The reason why checks have traditionally been performed intermittently is that repeated checks at high frequencies are not as effective, but (ii)
The check corresponding to (iii) above is performed, and it may be necessary to secure the time required for these checks. A system in which the time required for checking corresponding to the latter reason in the period of intermittent checking is relatively large,
In a system in which the time required for the checks corresponding to (ii) and (iii) above is longer than the time required for the checks corresponding to (i) above, efficient operation is achieved.

(E) 発明の効果 以上説明した如く、本発明によれば、同期処理
部が間欠的に行う処理終了報告チエツクを、一連
の複数個の対応処理の間に複数回行うようにして
いる。このために、同期確認処理に当つて無駄時
間が減少される。される。即ち、例えば、定期的
な「処理の終了の有無チエツク処理」の時間間隔
がWであつたとしかつ本発明にいう「終了無に対
応する処理」に要する時間がαであつたとした場
合において、 (i) α/W≒0(%) (ii) α/W≒100(%) の場合には、本発明にいう「第2回目の処理の終
了の有無チエツク処理」が実行されても、あまり
効果はない。しかし、 (iii) α/W=50(%) の場合には、「処理の終了の有無チエツク」が、
「第1回目の処理の終了の有無チエツク処理」に
おいて終了でない場合において、実質上上記時間
間隔W/2の間に1回行われる形となる。なお、
第1回目の処理の終了の有無チエツク処理」にお
いて終了とされた場合には時間間隔Wの間に1回
だけ行われることとなる。
(E) Effects of the Invention As described above, according to the present invention, the synchronization processing unit intermittently checks the process completion report multiple times during a series of a plurality of corresponding processes. Therefore, wasted time is reduced in the synchronization confirmation process. be done. That is, for example, if the time interval of the periodic "processing to check whether or not the processing is completed" is W, and the time required for the "processing corresponding to the non-completion" according to the present invention is α, (i) α/W≒0(%) (ii) In the case of α/W≒100(%), even if the “second processing completion check processing” according to the present invention is executed, It doesn't have much effect. However, in the case of (iii) α/W = 50 (%), "check for completion of processing" is
If the process is not completed in the "first process to check whether or not the process has been completed", the process is substantially performed once during the above-mentioned time interval W/2. In addition,
If the process is determined to have ended in the "first process termination check process", it will be performed only once during the time interval W.

なお、上記説明における第2図図示の「所定の
待ち時間」が仮に実質上零となつた如き間欠動作
となる場合にも、判定が複数回連続されるだけで
本発明の効果が失われるものではない。
In addition, even if the "predetermined waiting time" shown in FIG. 2 in the above explanation becomes an intermittent operation such that it becomes substantially zero, the effect of the present invention will be lost if the determination is repeated multiple times. isn't it.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明が適用される一実施例構成、第
2図は第1図図示モニタが行う本発明の同期化処
理の一実施例態様を示す。 図中、1はマイクロプロセツサ、2はデイスプ
レイ、3はキーボード、4は回線、5はモデム、
6はモニタ、7はアプリケーシヨン・プログラ
ム、8は回線制御部、11は回線終了情報域を表
わす。
FIG. 1 shows the configuration of an embodiment to which the present invention is applied, and FIG. 2 shows an embodiment of the synchronization process of the present invention performed by the monitor shown in FIG. In the figure, 1 is a microprocessor, 2 is a display, 3 is a keyboard, 4 is a line, 5 is a modem,
Reference numeral 6 represents a monitor, 7 an application program, 8 a line control unit, and 11 a line termination information area.

Claims (1)

【特許請求の範囲】[Claims] 1 所定のクロツクに同期して処理を進める同期
処理部と、依頼された処理の終了を上記同期処理
部に対して非同期に報告する非同期処理部とをそ
なえ、上記同期処理部が、上記非同期処理部に対
して依頼した処理の終了の有無チエツク処理と当
該処理の終了の無に対応する処理とからなる複数
個の対応処理を間欠的に実行し、上記依頼した処
理の終了を上記クロツクに同期して受取る非同期
事象同期化処理方式において、上記同期処理部が
上記間欠的な実行に対応して、上記同期処理部
が、上記依頼した処理の終了についての第1回目
の処理の終了の有無チエツク処理を実行し、終了
無に対応して上記処理の終了の無に対応する処理
を実行した後に、上記依頼した処理の終了につい
ての第2回目の処理の終了の有無チエツク処理を
行うよう構成されてなり、上記複数個の対応処理
の間に上記処理の終了の有無チエツクを少なくと
も2回実行するようにしたことを特徴とする非同
期事象同期化処理方式。
1. A synchronous processing unit that advances processing in synchronization with a predetermined clock, and an asynchronous processing unit that asynchronously reports completion of the requested processing to the synchronous processing unit, and the synchronous processing unit carries out the asynchronous processing. A plurality of corresponding processes are executed intermittently, consisting of a process to check whether the process requested to the department has finished, and a process corresponding to whether the process has ended, and the completion of the requested process is synchronized with the clock. In the asynchronous event synchronization processing method, the synchronization processing unit checks whether or not the first processing has finished regarding the completion of the requested processing, in response to the intermittent execution. After executing the process and executing the process corresponding to the non-termination of the above-mentioned process in response to the non-termination of the above-mentioned process, it is configured to perform a process of checking whether or not the second process has been completed regarding the completion of the requested process. An asynchronous event synchronization processing method, characterized in that, between the plurality of corresponding processings, a check for completion of the processing is executed at least twice.
JP57171561A 1982-09-30 1982-09-30 Asynchronous even synchronization processing system Granted JPS5960672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57171561A JPS5960672A (en) 1982-09-30 1982-09-30 Asynchronous even synchronization processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57171561A JPS5960672A (en) 1982-09-30 1982-09-30 Asynchronous even synchronization processing system

Publications (2)

Publication Number Publication Date
JPS5960672A JPS5960672A (en) 1984-04-06
JPH024931B2 true JPH024931B2 (en) 1990-01-31

Family

ID=15925414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57171561A Granted JPS5960672A (en) 1982-09-30 1982-09-30 Asynchronous even synchronization processing system

Country Status (1)

Country Link
JP (1) JPS5960672A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5435459B2 (en) * 1972-12-29 1979-11-02

Also Published As

Publication number Publication date
JPS5960672A (en) 1984-04-06

Similar Documents

Publication Publication Date Title
JPH024931B2 (en)
JP3133413B2 (en) Task omission control method
EP0288191B1 (en) Method and apparatus for data transfer handshake pipelining
JP2727847B2 (en) Debug device
JP3112287B2 (en) Message management processor
JP2747154B2 (en) Input/Output Processor
JPH0648473B2 (en) Message transmission / reception processing method
JPH0343653B2 (en)
JPH04107663A (en) Control system for synchronous communication system
JPH0583303A (en) Non-procedural communication control system
JPS62204354A (en) Control system for input/output instruction
JPS58168170A (en) Multiplex processor
JPS6022249A (en) Analysis method of process interruption
JPH05324554A (en) Local terminal stopping system for online real time processing system
JPH06131271A (en) How to avoid illegal timeout processing
JPH0239143B2 (en)
JPS63219042A (en) Program debug device
JPH03294952A (en) Input/output processing system
JPS62194552A (en) Task synchronizing system for central processing unit
JPH02311933A (en) Interruption control system
JPH0830538A (en) I / O processor
JPS59220823A (en) Interface control system
JPH01292560A (en) Inter-processor communication system
JPH04114540A (en) Communication control processor control system
JPH03109645A (en) Communication request processing method