JPH0777080B2 - Sense amplifier circuit - Google Patents

Description

The present invention relates to a sense amplifier circuit in a semiconductor memory device.

[Outline of Invention]

According to the present invention, in a sense amplifier circuit, a current flowing in a memory cell is compared with a current of a dummy MOS transistor, and the currents of a memory cell and a dummy MOS transistor are proportionally amplified and compared, so that stable operation and high speed are achieved. Is realized.

[Conventional technology]

Generally, in a semiconductor memory device in which a memory cell is composed of one MOS transistor, in the semiconductor manufacturing process, or
In a floating gate structure memory cell, etc., the MO
The data of the memory cell is written by changing the threshold voltage of the S transistor. Further, even when data is written depending on whether the memory cell and its output line are connected or not, the data is read by the same operation as the change in the threshold voltage depending on whether the MOS transistor is connected or not. Has become.

Conventionally, in such a semiconductor memory device, as shown in 1982 IEEE Solid-State Circuit Conference Digest P182, the capacity and load of the memory cell are
It is configured to detect the voltage by converting it according to the capability of the MOS transistor. FIG. 2 shows the main part of the conventional example for explaining the example. Here, the memory cell 2 is an N channel MO.
This is an example in the case of being composed of S transistors. Second
In the figure, 1 is a power supply terminal, 3 is a word line that selects a memory cell 2, and 4 is an N-channel MOS that selects a bit line 15.
Transistors, 5 are decoder output lines, 6 and 10 are N-channel MOS transistors, 7 is a P-channel MOS transistor for charging the bit line 15, and 8 is for stabilizing the bit line 15 against the data of the memory cell. Detection N-channel MOS transistor, 9 is a load P-channel MOS transistor of the stabilization detection circuit, 17 is its feedback signal, 11 is a memory cell data detection load P-channel MOS transistor, and 13 is a data detection MOS inverter. Is a P-channel MOS transistor, 14 is an N-channel MOS transistor, 16 is a data detection terminal, and 18 is an output terminal.
Now, the memory cell 2 is in a low threshold value state, and the word line 3
Also, the decoder output line 5 goes high and the memory cell 2
Is selected, if the potential of the bit line 15 is low, the output 17 of the bit line potential detection circuit becomes high level and the N channel MO
P-channel MOS transistor 7 via S-transistor 6
Charges the bit line. Then, the potential is stabilized at a potential determined by the bit line potential detection circuit and the N-channel MOS transistors 6 and 10, and at this time, the current of the memory cell is N
The flow is divided according to the size ratio of the channel MOS transistors 6 and 10. The capability of the N-channel MOS transistor 10 is determined by its source potential, gate potential 17 and size, and the load P-channel MOS transistor 11 is set lower than the capability of the N-channel MOS transistor 10 at this time. Move to the level side, output terminal
18 is high level. Next, when the threshold voltage of the memory cell 2 is high and in the OFF state, the bit line is further charged from the potential state of the bit line, the output 17 of the bit line potential stabilizing circuit goes down, and the N-channel MOS transistors 6 and 10 are connected to the substrate. It stabilizes at the potential that is turned off by the effect. N channel M at this time
The OS transistor 10 is OFF, the data detection point 16 is pulled up to the high level side by the load MOS transistor 11, and the output terminal 18 becomes low level. In this way, the data is detected depending on the state of the squeeze value voltage written in the memory cell.

[Problems and Objectives to be Solved by the Invention]

However, in the above-described sense amplifier circuit, only the value obtained by dividing the current flowing through the memory cell by the N-channel MOS transistors 6 and 10 flows at the data detection point 16. Also, the detection point
The amplitude of 16 swings only from a value approximately equal to the source potential of the N-channel MOS transistor 10 when the memory cell 2 is OFF to the power supply potential, and the potential when OFF is lowered by setting the bit line potential stabilizing circuit. Memory cell
The bit line potential when turned on also drops, and the current flowing through the memory cell becomes small. As a result, the amplitude of the detection point is inevitably set to be higher than the power supply potential. The inversion voltage of the MOS inverter that detects the potential of this detection point is set to approximately the middle of the amplitude of the detection point, and as a result, the P channel MO
The S transistor 13 becomes much larger than the N channel MOS transistor 14. Then, the load capacitance at the detection point 16 increases, and the operation speed becomes slower together with the current at the detection point 16 described above. Also, N channel MOS
Since the capability of the transistor 10, that is, the capability of the memory cell 2 and the capability of the P-channel MOS transistor 11 are compared,
A sufficient margin is required for manufacturing variations, and as a result, the capacity of the P-channel MOS transistor 11 needs to be set to a small value, which further slows down the operation of the detection point 16 to a high level.

Therefore, the present invention solves such a problem, and an object of the present invention is to increase the current at the detection point without limiting the current of the memory cell and to reduce the load capacitance at the detection point. The purpose is to reduce the size and increase the speed, and further to obtain a sense amplifier circuit that operates stably against variations in manufacturing.

[Means for solving problems]

In the sense amplifier circuit of the present invention, the memory cell includes a bit line connected to the memory cell, a first transistor whose conduction state is controlled according to the potential of the bit line, a power supply terminal, and the bit line. A second transistor connected between the first transistor and the second transistor for detecting the current of the bit line via the first transistor, and the second transistor connected in parallel with the second transistor via the first transistor. A third transistor for charging the memory cell, a dummy cell having characteristics similar to those of the memory cell, a fourth transistor connected between a power supply terminal and the dummy cell, and detecting a current flowing through the dummy cell; A fifth transistor that forms a first current mirror circuit with the transistor and a second current mirror circuit with the fourth transistor. And a sixth transistor that,
It is characterized by comprising a current mirror type differential amplifier circuit for comparing currents flowing through the fifth transistor and the sixth transistor.

〔Example〕

FIG. 1 shows an embodiment of the present invention. In FIG. 1, 19 is a P-channel MOS transistor for current detection of the memory cell 2, 20 is a P-channel MOS transistor for converting the voltage level of the P-channel MOS transistor 19 for current detection, and 21 is also an N-channel MOS. A transistor, 25 is a dummy MOS transistor having characteristics similar to those of the memory cell 2, 24 is a P-channel MOS transistor for current detection of the dummy MOS transistor 25, and 23 is P constituting a current comparison circuit.
Channel MOS transistor 22 is also an N channel MOS transistor. In FIG. 1, elements and contacts having the same numbers as those in FIG. 2 of the conventional example have the same functions.

Now, when the threshold voltage of the memory cell 2 is low, when the bit line 15 is at the low level, the word line 3 and the decoder output line 5 are at the high level, and when the memory cell 2 is selected, the bit line becomes stable. The feedback terminal 17 of the digitalization circuit becomes high level, and the P-channel M
The bit line 15 is charged by the OS transistor 19. Then, the bit line potential becomes a potential determined by the bit line stabilizing circuit, at this time, the same current as that of the memory cell 2 flows in the P-channel MOS transistor 19, and the gate-source potential corresponding to the current is between the power supply terminal 1 and Occurs in. Then P
The gate-source potential of the channel MOS transistor 20 also becomes the same as that of the P-channel MOS transistor 19, and a current corresponding to the size ratio of the MOS transistor flows through the P-channel MOS transistor 20. Here, it is assumed that the P channel MOS transistors 19 and 20 are set to have a current capacity sufficiently larger than that of the memory cell 2. For example, P channel MO
S-transistor 20 has the same channel length as 19
When the channel width is double and the MOS transistors have the same characteristics, a current that is twice as large as that of the memory cell 2 flows through the P-channel MOS transistor 20. And N channel MOS
The current is replaced by the transistor 21, and a current proportional to the current of the MOS transistor 21 flows in the N-channel MOS transistor 22 as described above. As a result, the N-channel MOS transistor 22 is proportional to the memory cell 2. Current capacity of. Similarly, the current of the dummy MOS transistor 25 is given as the current capacity of the P-channel MOS transistor 23 by the size ratio of the P-channel MOS transistors 24 and 23, and the current capacity of the P-channel MOS transistor 23 is the same as that of the N-channel MOS transistor 22. Since it is set to be smaller than the current capacity, its output terminal becomes low level and the output terminal 26 becomes high level. It can be easily understood that the output terminal 26 becomes low level by similar operation when the threshold voltage of the memory cell 2 is high. In FIG. 1, the P-channel MOS transistor 20 may have a size similar to that of 19, and the N-channel MOS transistor 21 may have a small MOS transistor size because of its high mobility.
Even if the ratio from 22 to 22 is increased, the current capacity can be increased without increasing the load capacity, and as a result, the operating speed can be increased. The current ratio from the memory cell 2 to the N-channel MOS transistor 22 of the current comparison circuit is determined only by the size ratio of the MOp transistors having the same characteristics. Similarly, the current ratio from the dummy MOS transistor 25 to the P-channel MOS transistor 23 is the same. However, since it is determined by the size ratio of the MOS transistors having the same characteristics, it is possible to stably manufacture the MOS transistors with little consideration given to manufacturing variations.

FIG. 3 shows another embodiment of the present invention. Reference numeral 27 is an N-channel MOS transistor for charging the bit line, and the other functions are the same as those of the elements having the same numbers in FIG. In FIG. 3, the function of the P-channel MOS transistor is only the current detection function of the memory cell 2, and the current capacity can be made sufficiently smaller than that of the embodiment of FIG.
As a result, the current capacity of the P channel MOS transistor 20 can be reduced. Here, the current capability of the P-channel MOS transistors 19 and 20 is reduced, but the current flowing in this MOS transistor is determined by the current of the memory cell 2, so the current value does not change from that of FIG. It is possible to further reduce the load capacitance by decreasing the capacity, that is, the size, and the same can be said for the N-channel MOS transistors 21 and 22, so that the load capacitance can be reduced without changing the current value. Yes, it can be faster.

The current comparison circuit of the embodiment can be a differential amplifier circuit without voltage level conversion after detecting the current of the memory cell, and the circuit from the dummy MOS transistor to the current detection circuit can be matched with that of the memory cell. By making the initial state constant when is selected, it is possible to obtain a comparison output before the bit line potential stabilizes.

〔The invention's effect〕

As described above, according to the present invention, the memory cell and the dummy MO are
By detecting the current of the S-transistor, amplifying it proportionally and inputting it to the comparison circuit, the current in the comparison circuit section can be increased and the speed can be increased. or,
The conventional example uses N-channel to extract the current of the memory cell.
Two signals of the source and the gate of the MOS transistor 10 are required, but according to the present invention, only one signal of the current detection terminal is required, and patterning can be performed when the sense amplifier circuit section has a selection function. Easy to do. Furthermore, by making the memory cell and the dummy MOS transistor have the same characteristics, the current capacity in the comparison circuit and the memory cell and the dummy MOS transistor are
By making the transistors have the same characteristics, the current capacity of the comparison circuit and the current capacity of the memory cell and dummy MOS transistor are determined only by the size ratio of the MOS transistors of the same characteristics, and can be stable without considering variations. Can be made.

Further, since the load capacity of each transistor can be reduced by providing the charging transistor, the speed can be increased.

[Brief description of drawings]

1 is an example of a sense amplifier circuit according to the present invention. FIG. 2 is a conventional sense amplifier circuit diagram. FIG. 3 is an example of a sense amplifier circuit according to the present invention. ...... MOS transistors that compose the bit line potential stabilization circuit 10,11 …… Data detection MOS transistors 20,21 …… Voltage level conversion MOS transistors 22,23 …… MOS transistors that compose the current comparison circuit 19,24 ... MOS transistor for current detection

Claims (1)

[Claims] 1. A memory cell, a bit line connected to the memory cell, and a conduction state controlled according to a potential of the bit line.
A second transistor that is connected between the power supply terminal and the bit line, and that detects the current of the bit line through the first transistor, and is connected in parallel with the second transistor, A third transistor that charges the bit line via the first transistor, a dummy cell having the same characteristics as the memory cell, and a current flowing in the dummy cell connected between a power supply terminal and the dummy cell A fourth transistor for detecting, a fifth transistor forming a first current mirror circuit together with the second transistor, and a sixth transistor forming a second current mirror circuit together with the fourth transistor.
And a current mirror type differential amplifier circuit that compares the currents flowing in the fifth transistor and the sixth transistor.