JPH0250617A - Programmable logic array - Google Patents

Abstract

PURPOSE:To simplify circuit constitution, to make the size small and to reduce the cost by providing a logic section in a logic arithmetic circuit, providing a gate circuit generating a logic arithmetic reset signal, and using a logic of the logic arithmetic circuit so as to generate a reset timing signal. CONSTITUTION:The logic of the logic arithmetic circuit 4 is programmed at the normal operation so as to output a reset timing signal RS representing the point of time when the required timing is finished. When the signal RS goes to an H level, since a system reset signal SRS in the normal operation is at an H level, a logic arithmetic reset signal PLARS goes to an L level. Then flip-flops FF3-FFn of a frequency division circuit 2 are reset and the operation of the logic arithmetic circuit 4 is stopped. Thus, since the initial reset and the start of the logic arithmetic circuit 4 are applied in a desired by having only to rearrange the logic of the logic arithmetic circuit 4, the circuit constitution is simplified remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to programmable logic arrays.

C. Conventional Technology] Conventionally, as this type of programmable logic array,
There was something like the one shown in Figure 2 (Japanese Patent Laid-Open No. 59-5327). That is, an oscillation circuit 2, a frequency division circuit 2 that divides the output of the oscillation circuit 1, an input latch circuit 3 that latches the output of a predetermined frequency division stage of the frequency division circuit 2, and the data latched in the input latch circuit 3. A logic operation circuit 4 that performs logical operations using programmable logic, and a signal processing circuit 6 that performs specific logic conversion (timing control using a frequency dividing circuit, etc.)
There was one equipped with '. In this case, after the necessary timing output is obtained from the logic operation circuit 4 (after a series of operations are completed), the frequency divider circuit 2 is returned to its original state to initialize the logic operation circuit, and the frequency remains constant after being reset. It is necessary to restart the device after a certain amount of time has elapsed, and in the conventional example above,
Oscillating mouth #! The t1 output is divided into two, one output signal S1 is used as an input to the programmable logic array, and the other output signal S2 is input to the signal processing circuit 6' to perform a specific logic conversion to determine the logic operation reset timing. It is now possible to obtain Here, the output signal S1 is input to one input terminal of the NOR circuit NOR, and the output signal S1 is input to one input terminal of the NOR circuit NOR.
The output PLAI of the logic operation circuit 4 is input to the other input terminal of the logic operation circuit 4. In addition, this output PL A + is input to the reset terminal of the frequency divider circuit 2, and the output PLAI becomes "H".
When this happens, the frequency divider circuit 2 is reset. moreover,
The restart of the frequency dividing circuit 2 is achieved by inputting PLA 2, which has undergone logic conversion processing in the signal processing circuit 6° that received the output signal S2, to the logic operation circuit 4, so that the output PLA
+ becomes "L", the reset of the frequency dividing circuit 2 is released, and the logic operation circuit 4 is restarted.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, the timing of resetting and restarting the logic operation circuit is controlled by the signal processing circuit 6° formed using a frequency dividing circuit or the like. As a result, the circuit configuration becomes complicated, making it impossible to reduce the size (reducing the area) and resulting in high costs.

The present invention has been made in view of the above points, and an object thereof is to provide a programmable logic array whose circuit configuration can be simplified and whose size and cost can be easily reduced.

[Means for Solving the Problems] The programmable logic array of the present invention includes an oscillation circuit, a frequency division circuit that divides the output of the oscillation circuit, an input latch circuit that latches the output of a predetermined frequency division stage of the frequency division circuit, Logic that includes a logic operation circuit that performs a logical operation on data latched in an input latch circuit using programmable logic, and an output latch circuit that latches the output of the logic operation circuit, and that creates a reset timing signal in the logic operation circuit. In addition, a gate circuit is provided that generates a logic operation reset signal based on a reset timing signal outputted via an output latch circuit.

[Function] The present invention is configured as described above, and in a programmable logic array in which a logic operation circuit is operated by a predetermined frequency division stage output of a frequency division circuit that divides an oscillation circuit output. A logic section for creating a reset timing signal is provided in the circuit, and a gate circuit is provided for generating a logical operation reset signal based on the reset timing signal outputted via an output latch circuit. Since the reset timing signal is formed using logic, the circuit configuration can be simplified and miniaturization and cost reduction can be easily achieved.

[Embodiment] FIG. 1 shows an embodiment of the present invention, which includes an oscillation circuit 1 using a CR time constant circuit and n 7-lip flops 1FF, to FFn that divide the output of the oscillation circuit 1. Circuit 2
and an input latch circuit 3 that latches the output of a predetermined frequency division stage of the frequency divider circuit 2 (in the embodiment, the outputs of flip-flops FF and ~FFn), and the data latched in the input latch circuit 3 is logically processed by programmable logic. The logic operation circuit 4 includes a logic operation circuit 4 that performs operations, and an output latch circuit 5 that latches the output of the logic operation circuit 4. A logic section that generates a reset timing signal RS is provided in the logic operation circuit 4, and the output latch circuit 5 A logic operation reset signal PL is generated based on a reset timing signal RS outputted via a
A gate circuit 6 that generates AR8 is provided. Here, in the embodiment, the gate circuit 6 is composed of two NAND gates NANDI and NAND2 and one inverter, and receives the reset timing signal R3.
A logic operation reset signal PLAR8 is generated based on the system reset signal SR3.

The operation of the embodiment will be described below. Now, all the clocks input to the logic operation circuit 4 are formed by frequency-dividing the output of the oscillation circuit 1 by the frequency divider circuit 2, and in the embodiment, the output is sent to the flip-flop FF and the output is sent to the input latch circuit 3. It is used as the latch clock CLK of the output latch circuit 5 to latch the outputs of the flip-flops FF2 to FFn to the input latch circuit 3, and to latch the output of the logic operation circuit 4 to the output latch circuit 5.

Here, at the time of power-on reset and forced reset, both the system reset signal SR3 and the logic operation reset signal PLAR8 become "L", and the entire system is brought to a halt state. On the other hand, during normal operation, the logic of the logic operation circuit 4 is programmed to output a reset timing signal R3 indicating the end of a series of operations (the point at which a series of operations ends). When the reset timing signal R3 becomes °H'°, the system reset signal SRS during normal operation becomes "H".
', so the logic operation reset node signal PLAR
S becomes L', and the flip-flop FF of the frequency divider circuit 2,
~FFn is reset, and the operation of the logical operation circuit 4 is stopped. In this state, the oscillation circuit 1 and flip-flops FF, FF2 are in the operating state, so
The initial values of FFco to FFn are latched in the input latch circuit 3 by the "H" and "L" levels of the latch clock CLK, and the logic operation circuit 4 is activated.At this point, the reset timing signal R9 becomes "L" and the necessary The level is maintained at "L" until the end of the specified timing.

As described above, in the embodiment, the reset timing signal R8 uses a part of the logic operation circuit 4 (one line in the embodiment) to set the initialization reset and startup timing.
Therefore, by simply rearranging the logic of the logic operation circuit 4, the initial reset and start-up of the logic operation circuit 4 can be performed at a desired timing, and the gate circuit 6 can be connected to a NAND gate NAND, , NAND2, or an inverter. The circuit configuration can be significantly simplified compared to the conventional example which requires a signal processing circuit 6' using a frequency dividing circuit, and it is easy to downsize and reduce costs. It is now possible to do this.

[Effects of the Invention] The present invention is configured as described above, and provides a programmable logic array in which a logic operation circuit is operated by a predetermined frequency division stage output of a frequency division circuit that divides an oscillation circuit output. A logic operation circuit is provided with a logic section that generates a reset timing signal within the arithmetic circuit, and a gate circuit that generates a logic operation reset signal based on the reset timing signal outputted via an output latch circuit. Since the reset timing signal is formed using this logic, the circuit configuration can be simplified, and there is an effect that miniaturization and cost reduction can be easily achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 1 is an oscillation circuit, 2 is a frequency divider circuit, 3 is an input latch circuit, 4
5 is a logic operation circuit, 5 is an output latch circuit, and 6 is a gate circuit. Agent Patent Attorney Ishi 1) Chief Seven Procedural Amendment Voluntary w2v! J 1, Indication of the case Patent Application No. 202301 filed in 1988 2, Name of the invention Programmable logic array 3, Person making the amendment Relationship to the case Patent applicant address 1048 Kadoma, Kadoma City, Osaka Prefecture Name (58
3) Matsushita Electric Works Co., Ltd. Representative: Toshio Miyoshi 4, agent postal code: 530 5, date of amendment order: 6.4: Number of claims increased by: None [1] Line 4 of page 2 of the specification of the present application "Oscillation circuit 2", "Oscillation circuit 1"
I will correct it. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] (1) An oscillation circuit, a frequency divider circuit that divides the oscillation circuit output, an input latch circuit that latches the output of a predetermined frequency division stage of the frequency divider circuit, and the data latched in the input latch circuit is logically processed using programmable logic. A logic operation circuit that operates,
An output latch circuit that latches the output of the logic operation circuit is provided, and a logic section that creates a reset timing signal is provided in the logic operation circuit, and a logic section that generates a reset timing signal is provided in the logic operation circuit. A programmable logic array characterized by being provided with a gate circuit that generates an arithmetic reset signal.