JPH0256692B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control system in a microprocessor or the like.

In a processing system having a main storage device and a cache memory, a phenomenon occurs in which a memory access (DMA) request issued from an external common bus to which an I/O control device is connected and a memory access request issued from a processor compete with each other. The cache memory in which part of the data in the main memory is stored is connected to the processor via an internal common bus, so a DMA request issued from the external common bus while the processor is accessing the cache memory is not processed by the processor. The process is forced to wait until the access to the cache memory is completed. however
Some DMA requests may only update data in main memory, so in such cases, even if the processor is accessing cache memory (using the internal bus), the data in main memory based on the DMA request may be updated. If data can be updated, processing efficiency can be improved.

The present invention focuses on the above points, and aims to provide a memory access control method that improves processing efficiency.

The present invention provides an internal common bus connected to a processing device, a main memory device, and a cache memory in which data that is part of the data stored in the main memory device but whose contents change from time to time, In a system having an external common bus connected to an output device, etc., and a common bus control section connected to the internal common bus and the external common bus, the common bus control section is configured to store data stored in the cache memory. An address table for storing address A' in the main memory device, a determining means for comparing and determining coincidence/mismatch between two input addresses, and a switching unit are provided, and a direct memory access request from the external common bus is made. When input to the common bus control unit, the determining means compares and determines the address A included in the direct memory access request and the address A' read from the address table, and when they do not match, operates based on the comparison result. This memory access control method is characterized in that the main memory device is accessed via a switching unit based on the direct memory access request.

Hereinafter, the present invention will be explained with reference to the drawings. The drawing is a block diagram illustrating an embodiment of the present invention.
1 is a cache memory, 2 is a processor, 3 is an internal common bus, 4 is an internal bus control section, 5 is a common bus control section, 6 is a signal transmission/reception section, 7 is a discrimination section, 8 is an address table, 9 is a switching section, 10 is the memory control unit, 1
1 is memory, 12 is external common bus, 13 is I/
OA, A' is address data, B is DMA request, C,
G is a control signal, D is data, E is a request signal, F is a permission signal, and A and B are contact points. Address table 8 in the drawing stores address data A' in cash memory 1, and as the contents of cache memory 1 are updated, address data A' in address table 8 is also updated. . In the drawing, from I/O13
When a DMA request B is issued, the common bus control section 5 that receives the request compares and discriminates the address data A included in the DMA request B with the address data A' in the address table 8 in the discriminating section 7.
When the address data A and A' match, this is a request for access to the cache memory 1, so the determining section 7 sends a control signal G to the signal transmitting/receiving section 6. Therefore, a request signal E is sent to the internal bus control section 4. If the processor 2 is accessing the internal common bus 3 (reading data from the cache memory 1), the internal bus control unit 4 issues a permission signal F upon completion of this access, so the common bus control unit 5 receives the DMA request B. The data in the cache memory 1 is updated by

In the discrimination section 7, address data A and
A' does not match (DMA request B requests only data writing to memory 11),
The determining unit 7 issues a control signal C to switch the switching unit 9 to contact RO, and then sends the data D from the external common bus 12 to the memory control unit 10 to write the data into the memory 11.

As described above, the present invention enables
It has means for determining the address included in a DMA request, and when the DMA request is only to update data in the main memory, it is possible to write data to the main memory even while the processor is accessing the cache memory. This has the advantage of significantly improving system processing efficiency.

[Brief explanation of drawings]

The drawing is a block diagram illustrating an embodiment of the present invention, and the symbols used in the drawing are as follows. 1 is a cache memory, 2 is a processor, 3 is an internal common bus, 4 is an internal bus control section, 5 is a common bus control section, 6 is a signal transmission/reception section, 7 is a discrimination section, 8 is an address table, 9 is a switching section, 10 is the memory control section,
11 is memory, 12 is external common bus, 13 is I/
OA, A' is address data, B is DMA request, C,
G indicates a control signal, D indicates data, E indicates a request signal, F indicates a permission signal, and A and B indicate contact points.

Claims (1)

[Scope of Claims] 1. An internal common bus connected to a processing device, a main memory device, and a cache memory in which data that is part of the data stored in the main memory device but whose contents change from moment to moment is stored. , an external common bus connected to input/output devices, etc., and a common bus control section connected to the internal common bus and the external common bus, an address table for storing an address A' in the main memory device of the data to be input, a determining means for comparing and determining whether two input addresses match or do not match, and a switching unit, When an access request is input to the common bus control unit, the determining means compares and determines the address A included in the direct memory access request and the address A' read from the address table, and if they do not match, the determination means determines the result of the comparison. A memory access control method characterized in that the main memory device is accessed based on the direct memory access request via a switching unit operated by.