JPH035619B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control method for controlling reading of data from a memory.

A processing system equipped with cache memory has an internal bus and a common (external) bus, and determines conflicts between DMA requests from the common bus and memory access requests from the processing unit, and A method of giving exclusive use of the bus is adopted. The conventional method will be explained using figures. FIG. 1 is a block diagram explaining the conventional system, in which 1 is a processing unit, 2 is a cache memory, 3 is an internal bus, 4 is a memory control section, 5 is a memory, 6 is a bus control section, 7 is a common bus, 8 is an input/output device, A is a DMA request, B
is a memory access request, and d is data. 1st
A part of data d in the memory 5 is stored in the cache memory 2 in the figure, and data is transferred to and from the processing device 1 at high speed. In FIG. 1, a bus controller 6 handles a conflict between a DMA request A from the common bus 7 and a memory access request B from the processing device 1.
makes a decision and allows one of them to exclusively use the internal bus. In such a processing system, if a DMA request A is issued from the common bus 7 side while the processing device 1 is reading data d from the cache memory 2, the DMA request A is ), it is possible to satisfy the READ request in parallel with data reading from the cache memory 2 by the processing device 1. If the DMA request is WRITE, a data mismatch occurs between cache memory 2 and memory 5, so the corresponding address in cache memory 2 is invalidated. When invalidated, the cache memory 2 is not hit and is accessed from the memory 5, and at that point, the latest data updated by DMAWRITE is taken into the cache memory 2. This is because in the case of READ, it is only necessary to read data from the memory 5. If parallel reading is possible in this way, the processing efficiency of the system can be significantly improved.

The present invention has focused on the above points, and aims to provide a memory access control method that improves the processing efficiency of a processing system.

The present invention includes a first control section that controls a common bus to which input/output devices, etc. are connected, a second control section that controls a main storage device, and an interface between the second control section and the main storage device. in a data processing system having a cache memory storing part of data of a storage device, and a processing device connected to the cache memory, wherein the processing device is connected to the cache memory from the common bus to the first control unit while the processing device is reading data from the cache memory. On the other hand, the present invention is a memory access control system characterized by comprising means for enabling reading of data from the main storage device when a memory access request for reading data is generated.

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 is a block diagram illustrating an embodiment of the present invention, in which 9 is a reception section, 10 and 11 are flag sections, 12 is a discrimination section, C is a read command, H is a hit signal, F ₁ ,
F ₂ , f ₁ , and f ₂ are flags, and the others are the same as in FIG. 1. In FIG. 2, a flag f ₁ is sent to the flag section 10 in response to a memory access request B from the processing device 1.
(READ) is set, data d in the cache memory 2 is read out to the processing device 1, and processing is executed. While reading data from cache memory 2, DMA request A (READ) is issued from the common bus 7 side.
When this is issued, the reception section 9 accepts it and sets the flag F ₁ (READ) of the flag 11. The determining unit 12 checks the flag units 10 and 11, and issues a read command C when the flags _F1 and _f1 are set while the hit signal H is valid. Therefore, the memory control unit 4 reads out the data in the memory 5 and sends it to the common bus 7 side. On the other hand, reading of data d from cache memory 2 by processing device 1 continues as is.

As described above, the present invention enables the main memory data to be read from the common bus side in parallel with the data read from the cache memory by the processing device, and has the advantage of significantly improving the processing efficiency of the processing system. .

[Brief explanation of the drawing]

Figure 1 is a block diagram explaining the conventional method, and Figure 2 is a block diagram explaining the conventional method.
The figure is a block diagram illustrating one embodiment of the present invention, and the symbols used in the figure are as follows. 1 is a processing unit, 2 is a cache memory, 3 is an internal bus, 4 is a memory control unit, 5 is a memory, 6 is a bus control unit, 7 is a common bus, 8 is an input/output device, 9 is a reception unit, 10 and 11 are flag section, 12 is a discrimination section, A
is a DMA request, B is a memory access request, C is a read command, d is data, F ₁ , F ₂ , f ₁ , f ₂ are flags,
H indicates a human signal.

Claims (1)

[Scope of Claims] 1. A first control unit that controls a common bus connected to input/output devices, etc., a second control unit that controls a main storage device, and the second control unit and the main storage device. In a data processing system, the data processing system includes a cache memory storing part of data in the device, and a processing device connected to the cache memory, wherein while the processing device is reading data from the cache memory, the first 1. A memory access control system, comprising means for enabling data reading from the main storage device when a memory access request for reading data is issued to a control unit.