JPH0258652B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic processing device such as a highly functional microprocessor.

[Technical Background of the Invention] FIG. 10 is a block diagram showing the general configuration of a conventional microprocessor. In the figure, 1
is an external bus, 2 is a bus control unit, 3 is a bus switching control unit, 4 is a machine instruction bus, 5 is an instruction register,
6 is an instruction decoder, 7 is a micro operation sequence control logic section, 8 is a random control logic circuit group, 9 and 10 are internal data buses, 11 is an address register group, 12 is a data register group, 13 is a temporary register group, 14 is a Arithmetic unit (ALU) 15 is a flag group.

In such a microprocessor, an instruction register 5 takes in instructions from an external bus 1 via a bus control section 2, a bus switching control section 3, and a machine instruction word bus. The instruction taken into the instruction register 5 is decoded by the instruction decoder 6, and the decoding result is given to the micro operation sequence control logic section 7. This micro operation sequence control logic section 7
consists of a programmable logic array (PLA) that generates micro-operation instructions, and based on these micro-operation instructions, random control logic circuit group 8
is controlled. This random control logic circuit group 8
constitute a part of each of the bus control unit 2, instruction decoder 6, address register group 11, data register group 12, temporary register group 13, and ALU 14, and this random control logic circuit group 8
The operation of each of the circuits described above is controlled by controlling.

In the micro-operation sequence control logic unit 7, a large number of sequences of different types and functional levels are stored together in a form that significantly interferes with each other (some of them are used). Based on the micro operation instructions that are the output, the physical data structures scattered through the random control logic circuit group 8 can be accessed, and the physical data structures that have a strong correlation with the random control logic circuit group in the bus control section 2 can be accessed. It takes the form of continued control.

[Problems with the background technology] As mentioned above, in the conventional microprocessor,
Since the system design is not hierarchically functionally decomposed according to processing requirement specifications, the independence of each circuit block is weak. In other words, blocks are physically decomposed at a fairly low level, such as registers, buses, switching circuits, selection circuits, encoders, and decoders.
All of this is centrally controlled by the micro operation sequence control logic section.

Therefore, it is possible to uniquely determine the operating period of each circuit block and the relationship with other circuit blocks to which resources such as data groups, control signals, status signals, and clock signals are transferred during the operation. It's hard to do. Therefore, there is a drawback that it is difficult to effectively improve the operating speed and yield at the system design level.

Furthermore, when developing a new high-performance VLSI microprocessor, changes in the micro operation sequence and changes in each data structure strongly interfere with other blocks, making design and product verification difficult and reducing development time. It also has the disadvantage of being costly.

For example, FIGS. 11 and 12, respectively,
This figure shows the commonly seen controlled states of conventional microprocessors. In the case of Fig. 11, when the target controlled system is C, in this example there are multiple control systems A and B that directly act on the controlled system C, and what is worse is that the control system A and B strongly interfere with each other. On the other hand, in the case of Fig. 12, the controlled system C is directly operated by the only control system D, but the control system D itself is driven by multiple control systems A and B. There is. However,
Since these control systems A and B strongly interfere with each other as in the case of Fig. 11, the controlled system C is unable to respond to the state changing due to the multiple control systems A and B. I will be working. Each of the control systems described above is composed of a logic section 20 and various state storage sections 30, respectively. In general, the situation is even more serious; the state memory of control system C is not local, but is updated directly by control systems A, B, D, etc., so not only the timing but also the function of C is slightly changed. is added, and the foresight of the operation of the control system C is often lost. For this reason, it is difficult to effectively improve the operating speed and yield as described above at the system design level. It is difficult to verify designs and products, which increases development time and costs. This results in disadvantages such as:

[Objective of the Invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to connect functional blocks of a single function in a hierarchical manner in order to meet the required specifications.
We provide concrete means to ensure that each function and timing has foresight and independence, thereby improving operating speed, yield, lower power consumption, and reducing chip size when integrating circuits. An object of the present invention is to provide an arithmetic processing device capable of achieving the following.

[Summary of the invention] In order to achieve the above object, this invention has the following features:
First, the required specifications of the arithmetic processing device are hierarchically broken down into system description language-oriented levels such as the task level, control structure level, calculation level, and lower levels than the calculation level. The processing functions and operating time ranges are configured so that the lower level is always narrower than the upper level, and when the upper level function block operates the lower level function block, it is configured so that the range of processing functions and operating time is narrower than that of the upper level. A control gate circuit for passing signals and data is provided for each functional block at each level. Furthermore, the data storage circuit and timing control circuit in each level of functional block have a dynamic circuit configuration that operates only while the block is active.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

An arithmetic processing device according to the present invention, for example a microprocessor, has an operation code field and an operation target field of a machine instruction word as shown in FIG.
As shown in FIG. 2, it is configured in a hierarchical structure.

That is, as shown in FIG. 1, the operation code field is level-separated to have n functional hierarchical levels from the highest level 1 to the lowest level n. On the other hand, the field to be manipulated is also level-separated to have n functional hierarchical levels from the highest level 1 to the lowest level n, as shown in FIG. 2, corresponding to the above operation code field. There is. Accordingly, in terms of functionality, the microprocessor itself is composed of a plurality of functional blocks 40 that have a hierarchical structure as a whole and have levels corresponding to the operation code fields, as shown in FIG. As shown in FIG. 4, the operation object 50 also has a number of levels corresponding to the operation object field level, and has a hierarchical structure as a whole.

FIG. 5 is a diagram showing an example of a controlled state of a microprocessor for explaining the principle of the present invention. In the figure, 60 is a storage circuit with a dynamic circuit configuration that can store data only when a clock signal is supplied from an upper-level functional block (not shown), and a memory circuit that generates various timing signals only when a clock signal is supplied. The level 1 (top level) functional blocks 61 and 62 each have a storage circuit and a timing control circuit with a dynamic circuit configuration inside, and have a timing control circuit with a dynamic circuit configuration inside. The level 2 functional block 63 used in the level 2 functional block 60 has an internal memory circuit and timing control circuit of a dynamic circuit configuration, and is a level 3 functional block used in the level 2 functional block 61. be. Here, the level 1 functional block 60 is as follows:
For example, processing functions can be hierarchically oriented toward system description languages at the task level, control structure level, calculation level, etc.
It corresponds to the task level when the level is decomposed into lower levels than the calculation level. Further, the level 2 function blocks 61 and 62 correspond to the control structure level, and the level 3 function block 63 corresponds to the calculation level.

Each of the functional blocks 60 to 63 has only a single processing function among the various functions at the corresponding level. In other words, each function block always performs the same processing operation during the operation period based on the operation instruction from the upper level, and the operation time and processing functions of the lower level function blocks are always narrower than those of the upper level function blocks. ing. Furthermore, each of the above functional blocks is provided with a control date circuit that supplies and controls various signals including data and clock signals to other functional blocks. only opened when using .

Now, when the functional block 60 executes a certain process, it calls a lower-level functional block 61 or 62 based on its own judgment as necessary, and utilizes the processing function of that functional block. At this time, function block 60 and function block 61 or 6
2, various signals including data and clock signals are supplied through the control gate circuit only during the execution period of each function block 61 or 62. Further, within the functional blocks 61 and 62, only temporarily necessary state memory is stored in the memory circuit. Similarly, function block 61
When executing a certain process, a function block 63 at a lower level is called based solely on one's own judgment, and the processing function of that function block is utilized. At this time, various signals including data and clock signals exchanged between the functional block 61 and the functional block 63 are limited to those necessary only during the execution period of the functional block 63. Furthermore, when each functional block executes an operation,
It operates the timing control circuit provided inside each to generate various timing signals,
Control is executed sequentially using this signal.

In this way, when a higher-level functional block uses a lower-level functional block, the processing behavior of the lower-level functional block is always the same;
Since the processing time is also approximately constant, foresight into lower level functional blocks is guaranteed in terms of both functionality and timing. In other words, the operating period of each functional block and its relationship with other circuit blocks to which resources such as data groups, control signals, status signals, and clock signals are transferred can be uniquely determined. Therefore, it is possible to effectively improve operating speed and yield at the system design level.

Furthermore, when developing a new high-performance VLSI microprocessor, changing the micro operation sequence or each data structure will not interfere with other blocks, making design and product verification easier. Therefore, it is possible to shorten the development period and reduce costs.

Furthermore, various signals including a clock signal are supplied to the lower-level functional blocks only when the higher-level functional block uses the processing function of that functional block, that is, only during the execution period of the operation.
During other periods, it does not operate and is at rest, so no power is consumed during this rest period. Therefore, it is possible to reduce power consumption.

In addition, since the memory circuit and timing control circuit within each functional level have a dynamic circuit configuration, the number of elements can be reduced compared to a static type circuit configuration, which reduces the chip size when integrating circuits. It is possible to aim for

FIG. 6 is a diagram showing another example of the controlled state of the microprocessor for explaining the principle of the present invention. In the case of FIG. 5 above, each functional block was provided with an independent memory circuit, but in this example, one memory circuit block 71 is provided for a plurality of functional blocks 70 at the same level, and this memory circuit The block 71 is replaced by the plurality of function blocks 7 mentioned above.
0 for common use. The plurality of functional blocks 70 and memory circuit block 71 are connected to the upper level functional block 72 via a bus 73.

The memory circuit in each functional block consists of flip-flops, latches, registers, etc., and if this memory circuit exists locally in the same level of functional blocks, the overall circuit scale will increase. Therefore, in this example, a common memory circuit block 71 is provided, and some or all of the memory circuits in each functional block are omitted to reduce the circuit scale.

FIG. 7 is a block diagram showing the structure of an embodiment of the present invention based on the above principle. In the figure, 80 is an upper level functional block, 81 to 83 are directly lower level functional blocks, and 84 is a bus that connects the upper level and lower level functional blocks.
Each of the above functional blocks includes an execution control section 91, a completion status synthesis section 92, and a data distribution/combination section 9, as illustrated in the upper level functional block 80.
3, an internal clock generation section 94, a logic section 95, a storage section 96, and a control date section 97.

The execution control unit 91 is composed of a PLA that stores microprograms in advance, and selects one microsequence according to the operation instruction code supplied from the upper level function block, and outputs various timing signals according to this sequence. Occurs sequentially. The execution control section 91 has a dynamic circuit configuration as described above, and operates only when a clock signal is supplied from the internal clock generation section 94.

The completion status synthesis section 92 synthesizes status signals when the processing operations in the corresponding functional blocks are completed, and outputs the synthesized status signals to other functional blocks.

The data distribution/combining section 93 internally distributes various data supplied from other functional blocks, and combines the resulting data to be supplied to other functional blocks upon completion of processing.

The internal clock generator 94 generates all the clock signals required within the functional block from clock signals supplied from the outside or from other functional blocks.

The logic section 95 includes AND, OR, NOT,
It is composed of a combination circuit of gate circuits such as NAND, NOR, and exclusive OR, and executes processing based on the microsequence selected by the execution control section 91.

The storage section 96 is composed of registers, latches, counters, etc., and stores initial data required when the logic section 95 executes processing, as well as data in the middle of processing and data on processing results.
The storage section 96 has a dynamic circuit configuration as described above, and operates only when a clock signal is supplied from the internal clock generation section 94.

The control gate unit 97 exchanges data, operation instruction codes, and operation with other functional blocks when it becomes necessary to use functional blocks at other levels when executing its own processing. Controls the transfer of result status, clock signals, etc.

In such a configuration, an operation instruction code is now given to the upper-level function block 80, the time when the operation starts is tsO, the time when the operation ends is teO, and the execution time from the start to the end of the operation is TO. and lower level functional block 8
1, 82, and 83, and the times at which the operations start are ts1, ts2, and ts3, and the times at which the operations end are te1, te2, and te3, the lower-level function blocks 81, 82, and In 83, the execution time T1, T2, T3 until the operation ends
are given by the following equations.

T1=te1-ts1...1 T2=te2-ts2...2 T3=te3-ts3...3 Now, between the times ts1, ts2, and ts3 when the function blocks 81, 82, and 83 start operating, It is assumed that a relationship such as the following four equations holds true, and a relationship such as the following five equations holds between the times te1, te2, and te3 at which the operation ends.

ts1≦ts2≦ts3 …4 te1≦te2≦te3 …5 The above formulas 4 and 5 are
2, 83 at the same time or functional blocks 81, 8
The operations are started in the order of function blocks 2 and 83, and the termination of the operations means that the operations of function blocks 81, 82, and 83 are terminated at the same time or in the order of function blocks 81, 82, and 83. 4 and 5 above
When the formula is satisfied, this device always ensures that tsO is faster than ts1 and teO is slower than te3.

Therefore, the minimum value of the execution time TO in the upper-level function block 80 is the execution time (T1) + α when the lower-level function blocks 81, 82, and 83 operate in parallel or when only the function block 81 operates. The maximum value is the execution time (T1+T2+T3)+β when the lower level functional blocks 81, 82, and 83 operate in series and sequentially.

The above relationship means that the lower-level functional blocks can operate in parallel, each functional block can independently determine its own power consumption period, and each block must hold the signal for that period. It shows that it is good.

FIG. 8 is a block diagram showing the detailed structure of the control gate 97 provided in each of the functional blocks. As shown, the control gate 97 in each functional block is composed of three parts. The three parts are the upper gate Gu, which transfers the data and various signals to and from the upper level;
These are a lower gate Gd that transfers the data and various signals to and from the lower level, and a local gate G1 that transfers the data and various signals between the same levels. The control gates 97 at each level are connected via a bus 100 connecting the upper and lower levels, and the control gates 97 at the same level are connected to other control gates 97 via a local bus 101.

Here, the operation instruction code, data, and clock signal are controlled to be supplied from the upper level to the lower level, and the completion status and return data are controlled to be supplied from the lower level to the upper level.

The upper gate Gu, lower gate Gd, and local gate G1 of each of these control gates are constituted by well-known bidirectional or unidirectional gate circuits.

FIG. 9 is a diagram showing a specific configuration of a microprocessor according to the present invention to which the above-described principle is applied. This microprocessor has a functional division compatible with system description languages such as Ada or concurrent Pascal.

First, the top level 1 function block 1
In step 11, task control level processing such as task switching, task delay, task rendezvous, task start, task stop, task priority, task number, task waiting queue, task execution/preparation/wait/delay time, etc. is performed, and the task is Any one of the program control structure levels at the next level 2 within is selected.

Function blocks 121, 122, 123, and 124 at the level 2 program control structure level include repetition control structures such as WHILE, REPEAT, and FOR, selection control structures such as IF and CASE, and interruption control such as interrupts, procedures, and function calls. , processing of the control level such as sequential control of data processing, etc. is performed, and within the processing, any one of the calculation levels such as the next level 3 is selected.

Function block 13 of this level 3 calculation level
1, 132, 133,..., evaluation of logical expressions, evaluation of arithmetic expressions, input/output of data, evaluation of external events,
Performs calculation level processing such as parameter extraction and instruction word extraction, and performs processing at the next level 4 within that processing.
One of the lower levels is selected.

Function block 14 at the lower level of this level 4
1, 142, and 143 perform processing such as ALU, intermediate value register, address conversion, bus cycle generation/interruption/stop, and bus release.

These functional blocks from level 1 to level 4 are connected to buses 201, 202, 203, 20
Connected via 4.

When the functional blocks at each level perform their respective processes, the data to be processed is read out from each memory circuit as necessary, and
The ALU (function block 141) actually performs the necessary calculations.

A feature of this microprocessor is that, as described above, each control gate section implements an access method that selectively determines functions and timing.

In this way, in the microprocessor according to the present invention, when the upper-level functional block performs its own function, the functions to be shared by the lower-level functional block are clearly separated, and the operating period is also longer than that of the lower-level functional block. This is the minimum amount of time that a function block performs its function, and it performs the same operation no matter how many times it is called. Therefore, each lower level functional block is operated independently and in parallel from the upper level functional block as necessary. Therefore,
System-based margin time can be predicted for the operating speed of individual functional blocks, improving overall operating speed.
Yields can be expected to improve by increasing the margin for variations in VLSI microprocessor manufacturing.

In addition, all functional blocks can retain data for the minimum amount of time required and can match the timing, so each CMOS circuit configuration (especially the memory circuit) can be made into a dynamic type circuit configuration, which allows the elements to The chip size can be reduced by reducing the number of chips. Furthermore, since only the lower-level functional blocks activated by the higher-level functional blocks operate, unnecessary functional blocks do not operate during that period and do not consume power. Therefore, the power consumption of the entire chip during operation is significantly reduced.

[Effects of the Invention] As explained above, according to the present invention, in order to meet the required specifications, functional blocks of a single function are connected in a hierarchical manner, and the functions and timings to be performed by each unit are determined with foresight and independence. It is possible to provide an arithmetic processing device that can improve operating speed, increase yield, reduce power consumption, and reduce chip size when integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the operation field of the machine instruction word used in the present invention, FIG. 2 is a diagram also showing the configuration of the operation target field, and FIG. 3 is a schematic configuration of the arithmetic processing device of the present invention. FIG. 4 is a diagram showing the configuration of the operating target of the device, FIG. 5 is a diagram showing an example of the controlled state of the microprocessor for explaining the principle of the invention, and FIG. Figures showing other examples of controlled states of a microprocessor for explaining the principle of the invention, Figure 7 is a block diagram showing the configuration of an embodiment of the invention, and Figure 8 is a diagram showing the state provided in a functional block. FIG. 9 is a block diagram showing the detailed structure of the control gate; FIG. 9 is a diagram showing the specific structure of the microprocessor according to the present invention;
FIG. 10 is a block diagram showing the general configuration of a conventional microprocessor, and FIGS. 11 and 12 are diagrams showing controlled states of the conventional microprocessor, respectively. 60, 61, 62, 63, 70, 72, 80,
81, 82, 83, 111, 121, ..., 13
1,...,141,...Function block, 71...Storage circuit block, 91...Execution control section, 92...Completion status synthesis section, 93...Data distribution/combination section, 9
4...Internal clock creation section, 95...Logic section, 96...
Storage section, 97...control gate section, Gu...upper gate,
Gd...lower gate, Gl...local gate.

Claims (1)

[Scope of Claims] 1. The operation code field of the machine instruction code has a hierarchical structure of requested functions, and the field to be operated has a corresponding hierarchical data structure, wherein It consists of a functional block and a lower functional level functional block, each block containing multiple functional blocks that execute the function specified by the above operation code field, and these functional blocks are configured so as to form a hierarchical structure as a whole. The plurality of function blocks are at least a function block at the task level, a function block at the control structure level that is combined with the function block at the task level, and a function block at the control structure level that has a lower function level than the function block at the task level, and a function block at the control structure level. A function block at the calculation level that is combined with a function block at the control structure level and has a lower function level than the function block at the control structure level; Each functional block executes processing operations by passing data groups, operation instruction codes, operation result statuses, and clock signals between the upper and lower levels. Each functional block has a control gate means for passing the data group, operation instruction code, status of operation result, and clock signal between the upper level and lower level functional blocks only during the period when the lower level executes the processing operation; A storage means having a dynamic circuit configuration, whose operation is controlled based on the above clock signal, and which stores necessary data during the period when the functional block executes the processing operation; 1. An arithmetic processing device comprising timing control means having a dynamic circuit configuration that generates various timing signals required for the processing. 2. A first control gate circuit in which the control gate means transfers the data group, operation instruction code, operation result status, and clock signal between an upper level functional block and the function block at that level; A second control gate circuit that transfers the data group, operation instruction code, operation result status, and clock signal between the function block at the same level and the function block at the lower level; and a third control gate circuit that transfers the data group, operation instruction code, operation result status, and clock signal to and from other functional blocks. Processing equipment. 3. The arithmetic processing device according to claim 1, wherein the storage means of the dynamic circuit configuration is provided as a common block for functional blocks at the same level.