JPH026067B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-value voltage source circuit for a liquid crystal display device configured with MISFETs (insulated gate field effect transistors).

As a multi-value voltage source circuit for liquid crystal display devices,
A circuit as shown in FIG. 4, which is described in Japanese Patent No. 50-158294, is known.

This circuit consists of series-connected switching MISFETs that output an intermediate level voltage of −V ₃ .
MISFETs Q ₁₃ and Q ₁₄ are used, and their common substrate area is connected to the above series MISFETs Q _{13 and} Q 14.
It connects to the connection point of _Q14 .

As a result, when the maximum voltage -V ₁ is output, the maximum voltage is supplied from the output terminal OUT to the substrate region through the forward pn junction between the drain of MISFET Q ₁₄ and the substrate region, and the intermediate voltage -
The purpose is to reverse bias the pn junction between the drain and substrate region of MISFET Q ₁₃ to which V ₃ is applied, and prevent DC current from flowing between the output terminal OUT and the intermediate voltage terminal -V ₃ .

In this circuit, as mentioned above, _the channel _width W/
The ratio of channel length L must be increased,
The disadvantage was that MISFETs Q ₁₃ and Q ₁₄ had to occupy a large area.

The present invention was made in order to provide a multi-value voltage source circuit for a liquid crystal display device that can reduce the occupied area.

This invention is a switching device for intermediate voltage output.
As a MISFET, in series to change the potential of the substrate region according to the output voltage.
It is intended to be configured with a MISFET and an intermediate voltage output MISFET.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This circuit is a circuit that outputs three levels of voltages -V ₁ , -V ₃ , and V ₂ .For example, -V ₁ is 3 volts,
-V ₃ is 1.5 volts and V ₂ is 0 volts.

Provided between the above maximum voltage -V ₁ and the output terminal OUT, and the substrate area is the above voltage terminal -
An n-channel MISFET Q ₁ connected to V ₁ and controlled by the output control timing pulse φ ₁ is for supplying the above voltage −V ₁ at the output.

Also, a substrate area is provided between the minimum voltage V ₂ and the output terminal OUT, and the substrate area is connected to the voltage terminal V ₂ above.
A p-channel MISFET _{Q 2 connected} to the
It is for supplying _V2 .

The n-channel MISFETs Q ₃ and Q ₄ , which are installed in series between the intermediate voltage -V ₃ and the output terminal OUT, are used to apply a bias voltage to the substrate region according to the output voltage. The n-channel MISFET Q ₅ , which is connected _to the
It is connected to the connection point of MISFETs Q ₃ and Q ₄ , and an output control timing pulse φ ₃ is commonly applied to the gates.

FIG. 3 shows a cross-sectional view of one embodiment of this circuit constructed into a monolithic semiconductor integrated circuit device.

In the same figure, an n-type silicon substrate
W ₂ includes a p-type well region that is simultaneously diffused to a depth of approximately 8 microns using conventional selective diffusion techniques.
It has W ₁ and W ₃ .

By selectively diffusing n-type impurities into each of the well regions _W1 and _W3 ,
Source regions S ₁ and S ₃ of MISFETs Q ₁ and Q ₃ to _{Q 5}
˜S ₅ and drain regions D ₁ and D ₃ ˜D ₅ are simultaneously formed. The source and drain regions created by these diffusions extend approximately 1.5 microns deep into the well region.

On the other hand, the silicon substrate W ₂ has p
By selectively diffusing type impurities,
The source region S ₂ and drain region D ₂ of MISFET Q ₂ are formed at the same time.

The surface of each gate region of the MISFET is covered with a layer of insulator about 1200 Å thick, and a silicon gate electrode layer about 4000 Å thick is formed on this insulating layer. As a gate electrode layer,
When aluminum is used, a layer with a thickness of 10,000 Å is used on the above insulating layer.

The above well region W ₁ constitutes the substrate region of MISFET Q ₁ , and the well region W ₃ constitutes the substrate region of MISFET Q 1.
The silicon substrate W ₂ constitutes the common substrate area of MISFETs Q ₃ to _{Q 5} .
This constitutes the substrate area of MISFET Q ₂ .

MISFET Q ₁ to _{Q 5} with the above configuration can be
It is connected like the circuit above.

This circuit can alternatively perform the above switching
The MISFET is turned on to obtain any level among the three levels.

For example, by output control timing pulse φ ₂ ,
When MISFET Q ₂ is turned on, the output OUT is 0.
A volt voltage V ₂ is obtained.

Next, the above MISFET Q ₂ is turned off, and the output control timing pulse φ ₁ is used to turn off the MISFET Q 2.
When MISFET Q ₁ is turned on, the output OUT is
The maximum voltage −V ₁ is obtained.

At this time, the above output voltage is supplied to the substrate region through the pn junction between the drains (output terminal side electrodes) of MISFETs Q ₄ and Q ₅ and the substrate region. Therefore, since this substrate region and the drains and sources of MISFETs Q ₃ and Q ₅ are reverse biased, no direct current flows between the output terminal OUT and the intermediate voltage −V ₃ .

Then, while turning off the above MISFET Q ₁ , the output control timing pulse φ ₃ is used to
When MISFET Q ₃ to _{Q 5} are turned on, an intermediate voltage -V ₃ is obtained at the output OUT.

At this time, by turning on the MISFET Q ₃ , the substrate region is fixed at the intermediate voltage -V ₃ . And in this example,
MISFET Q ₅ mainly supplies the output current, and the series MISFETs Q ₃ and Q ₄ are used to switch the bias voltage in the substrate region, thereby significantly reducing the occupied area. .

In other words, since the series MISFETs Q ₃ and Q ₄ are used simply to switch the bias of the substrate region, the mutual conductance W/L
This is because MISFET Q ₅ can have a transconductance W/L that is half that of series MISFET Q ₁₃ or Q ₁₄ in the prior art. Therefore, the above series MISFET Q ₅ ,
Even considering the area occupied by _Q4 , it is possible to reduce the area occupied by more than half of the conventional one.

In addition, in this circuit, when the maximum voltage -V ₁ is output, the maximum voltage -V ₁ is supplied to the substrate region through the pn junction between the drain of MISFET Q ₄ or Q ₅ and the substrate region. Therefore, it is not a fixed potential, and a discharge path is not formed for a voltage that is larger in absolute value than the voltage level-shifted by the p-n junction forward voltage from the maximum voltage -V ₁ above, so static It will fluctuate depending on electrical coupling, etc. Therefore, when the potential of the substrate region changes in this way,
In the relative relationship with the gate potential of MISFET Q ₃ to _{Q 5} , the gate potential is level-shifted in the direction of on-level, so there is no malfunction or off-level margin where the gate potential turns on even when off-level control voltage is applied. It lowers the

Therefore, as shown in FIG. 2, in a circuit similar to the above embodiment, the intermediate voltage output control timing pulse φ ₃ and the maximum voltage output control timing pulse φ ₁ are used as the output control timing pulses of MISFET Q ₄ . Assume that the logical sum φ ₁ +φ ₃ is used.

As a result, at maximum voltage output,
Since MISFET Q ₄ turns on and the potential of the substrate region of MISFET Q ₃ to _{Q 5} is fixed at the maximum voltage obtained at the output, it is possible to prevent the above-mentioned malfunction or decrease in the off-level margin. .

The present invention is not limited to the embodiments described above, and when outputting a multi-value level of four or more levels, a circuit similar to that of the embodiments described above may be provided as an intermediate level output switching MISFET. When fixing the potential of the substrate region of the switching MISFET for intermediate voltage output, it may be controlled by the OR output of timing pulses that output a voltage larger in absolute value than the intermediate voltage to be output. .

Furthermore, when the polarity of the power supply is changed, the polarity of the control pulse and the conductivity type of the MISFET may be changed accordingly.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing one embodiment of the present invention, FIG. 3 is a structural sectional view when the first circuit is configured as a monolithic semiconductor integrated circuit device, and FIG. 4 is a circuit diagram showing an embodiment of the present invention. FIG. 1 is a circuit diagram showing an example of a conventional technique.

Claims (1)

[Scope of Claims] 1. Provided between a first voltage source forming a voltage having a large absolute value and an output terminal, a substrate region is coupled to the first voltage source, and the first voltage source generates a voltage having a large absolute value. a first switching MISFET of a first conductivity type that is switch-controlled by a timing signal; and a second voltage source and the output terminal, the substrate region being coupled to the second voltage source; and a second switching of a second conductivity type that is switch-controlled by the second timing signal.
MISFET; and a third voltage source having a voltage value between the voltage of the first voltage source and the voltage of the second voltage source and the output terminal, and is provided in accordance with a third timing signal. a third switching MISFET of a first conductivity type that is switch-controlled; and the third voltage source and the third switching MISFET.
Provided between the MISFET substrate,
and a fourth switching of the first conductivity type that is switch-controlled by the third timing signal.
MISFET; and a fifth switching MISFET of a first conductivity type, which is provided between the substrate of the third switching MISFET and the output terminal and whose switch is controlled by the third timing signal, The substrates of the fourth and fifth switching MISFETs are commonly coupled to the substrate of the third switching MISFET, and the voltages of the first to third voltage sources are selected via the first to fifth switching MISFETs. A multi-value voltage source circuit for a liquid crystal display device, characterized in that the voltage is supplied to the output terminal. 2 The above third to fifth switching MISFETs
2. A multi-value voltage source circuit for a liquid crystal display device according to claim 1, wherein said voltage source circuit is formed in a common substrate region. 3 The fifth switching MISFET performs ON control of the first switching MISFET and the third switching MISFET.
2. The multi-value voltage source circuit for a liquid crystal display device according to claim 1, wherein the switch is controlled by any timing signal that turns on the switching MISFET.