JPH0261139B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device suitable for use in obtaining semiconductor devices, particularly semiconductor integrated circuits.

In semiconductor integrated circuits, miniaturization of each semiconductor element structure is required in order to improve the integration density and operation speed. In order to miniaturize such a semiconductor element structure, if this element adopts a bipolar structure, or a so-called
Regardless of whether a MOS structure is adopted, it is necessary to microfabricate the plane pattern, and at the same time, with the miniaturization of the plane pattern, microfabrication in the depth direction, i.e. rectifying junctions at shallow positions from the semiconductor surface, is required. Formation of junctions or ohmic junctions such as P ⁺ P junctions and N ⁺ N junctions, so-called shallow type junction formation, and the extraction of low resistance electrodes for this will become important issues. Moreover, such a shallowing technique is not only necessary for increasing the density of integrated circuits in general, including bipolar integrated circuits, but is also effective for improving the characteristics of semiconductor elements themselves. Further, if the junction depth becomes shallower, the total amount of impurity diffusion and the heat treatment time are reduced, which leads to an improvement in the shortening and simplification of the semiconductor device manufacturing process.

In this way, although the joining shearing technology brings many advantages, this technology has
It is not only necessary to achieve simple shallowing, but also to improve its accuracy and reproducibility.

On the other hand, in order to suppress as much as possible the occurrence of defects induced during the semiconductor device manufacturing process, there is a need to lower the temperature in the semiconductor manufacturing process. To meet these demands, an impurity-containing SiO ₂ film or a polycrystalline semiconductor (polycrystalline silicon) film is formed on the semiconductor surface as an impurity diffusion source for the semiconductor substrate, and then the impurities from this film are removed. The so-called doped oxide method, doped polysilicon method, etc., in which shallow doping is performed from the surface of a semiconductor substrate to form a shallow diffusion layer, are known.

On the other hand, electrode formation technology has an extremely important relationship with this shallowing process. That is, when making ohmic contact with, for example, an Al electrode to such a shallow junction, the diffusion of these Al atoms into the silicon semiconductor substrate, so-called infiltration, may destroy the PN junction or impede its rectification. There are problems such as. In order to prevent such inconveniences, for example, there is a method of adding Si or the like to the Al electrode and alloying it at least in the contact area to the semiconductor substrate, or a method of adding Si or the like to the Al electrode and adding it to the contact area between the Al electrode and the Si substrate. Methods such as interposing a polycrystalline silicon layer are known. However, the process of forming a polycrystalline silicon layer after forming such a shallow junction is complicated.

As mentioned above, the method for forming shallow junctions is as follows:
Various methods have been adopted, all of which have many or important drawbacks. That is,
For example, when using ion implantation, although it has the advantage of uniformly forming a shallow impurity doped layer as described above, the ion implantation damages the surface of the semiconductor substrate. Therefore, in order to prevent crystal defects from being induced by the primary defects caused by this damage, the implanted impurities are further removed after the ion implantation process as a recovery heat treatment to eliminate the primary defects. As a so-called activation treatment for substituting crystal lattice points, it is necessary to perform high-temperature annealing at 900° C. or higher. Further, the formation of an electrode on this impurity doped layer needs to be performed in a process separate from the impurity doping step.

In addition, when using the doped oxide method,
It is necessary to perform the work of diffusing the impurity in the doped oxide into the semiconductor substrate and then removing the oxide film and the work of forming the electrode described above as separate processes.

On the other hand, when using the doped polysilicon method, there is no need to remove the polysilicon layer on the surface in order to diffuse impurities into the substrate, and the doped polysilicon layer itself becomes part of the electrode. On top of the
Metal electrodes such as Al can be formed. However, when this doped polysilicon method is used, impurities tend to precipitate at the interface between the polysilicon film and the surface of the semiconductor substrate due to abnormal diffusion at the crystal grain boundaries of the polysilicon, and the resistance of this polysilicon film However, even when doped with impurities at a high concentration, the electrode resistance does not become very low, resulting in a large electrode resistance.
Incidentally, such precipitation of impurities on the surface of the semiconductor substrate occurs at the interface between the oxide film and the semiconductor substrate even when using the doped oxide method, but when using the doped oxide method, the atmosphere is This can be prevented by making it oxidizing. Compared to this,
In the above-mentioned doped polysilicon method, such an oxidizing atmosphere cannot be applied.

In the present invention, the above-mentioned drawbacks are avoided, and a uniform and sufficiently shallow junction is achieved, and a silicon layer capable of acting as a barrier layer to prevent metal electrodes, such as Al electrodes, from entering the junction. epitaxial layers can be formed at the same time, and in particular, the residual primary defects that cause ^crystal defects can be drastically reduced ^. A method for manufacturing a semiconductor device that enables the formation of junctions such as N junctions in fine patterns, making it possible to form especially shallow junctions and to take out electrodes from them using a good and simple process. It provides:

An example of forming a shallow PN junction according to the present invention will be described in detail with reference to the drawings. In the figure, 1 is a single-crystal semiconductor substrate, for example, a silicon semiconductor substrate 1, and the surface of the semiconductor having a first conductivity type, for example, P type, facing the main surface 1a of the 1, is doped with an impurity of a second conductivity type, for example, N type. and shallow PN
It attempts to form a bond. For this reason, first, as shown in FIG.
A mask layer 2 doped with impurities, such as SiO ₂ , is deposited by a well-known technique, and windows 2 a are formed in the portions of this layer 2 where the PN junction is to be formed by any method such as photo etching or plasma etching. Then, make a hole.

On the other hand, in the present invention, as shown in FIG. 2, a special epitaxial growth apparatus is provided. This epitaxial growth apparatus includes a bell gear 12 whose interior can be maintained at a high degree of vacuum by a vacuum pump 11. For example, in the lower part of this bell gear 12, Si of a semiconductor epitaxial material is placed.
A vapor deposition source 13 is provided. This vapor deposition source 13 may take the form of vapor deposition by heating with a heater or the like, vapor deposition by electron impact, or the like. Reference numeral 14 denotes a cooling device, a so-called cold trap, which prevents impurities from entering the vapor deposition source. A susceptor 15 for the semiconductor substrate 1 made of, for example, graphite is provided above the evaporation source 13 in the belgia 12, and a susceptor 15 for the semiconductor substrate 1 made of, for example, graphite is provided on the susceptor 15 for the semiconductor substrate 1 on which the mask layer 2 is formed on the surface 1a described in FIG. Base 1
Place the support. This susceptor 15 and therefore the base 1
is heated to a required temperature by a heating means such as a heating lamp or a high-frequency heating coil 16 as shown. Reference numeral 17 denotes a shield body disposed around the supporting portion of the base 1, and the evaporation source 1
A window 17a is provided on the side facing 3. Further, a vapor deposition source 1 is provided between the vapor deposition source 13 and the arrangement portion of the base body 1.
an electron beam irradiation device 18 that irradiates an electron beam across the path of the vapor deposition material from 3 to the substrate 1;
will be provided. This electron beam irradiation device 18 is
For example, a cylindrical repeller 19 and a filament 20 coated with an annular cathode material arranged inside the repeller 19
A cylindrical, for example, mesh-shaped anode 21 is placed inside the anode 21, and -400V is applied to the repeller 19 and filament 20 with the anode 21 set at 0V. Further, between the electron beam irradiation device 18 and the support portion of the substrate 1, an impurity of the second conductivity type, which serves as a dopant, for example, an N-type antimony Sb evaporation source 22 is arranged.
For example, a heater 24 is disposed around the container 23 of the evaporation source 22, thereby maintaining the dopant 22 at a required temperature and transferring it to the evaporation source 22.
3 and the substrate 1 on the evaporation path. The susceptor 15 holding the base 1 is given, for example, 10 KV, and the shield body 17 is given -
10.2KV is given. A shutter 25 opens and closes the window 17a of the shield body 17.

In such a configuration, the substrate temperature Ts is, for example,
When Si is evaporated from the evaporation source 13 toward the substrate 1 at 750°C, the electron beam from the electron beam irradiation device 18 impacts the evaporation material gas in its path, ionizing a part of it. do.
This ionization amounts to approximately 1% of the silicon vapor deposition material gas. On the other hand, a portion of the impurity vapor is ionized due to the collision of the vaporized gas from the impurity source 22 with the ionized Si, that is, due to the charge exchange effect. These ions are accelerated and impact the substrate 1, and at the same time, a semiconductor doped with Sb in Si is grown on the semiconductor substrate 1 at a growth rate of about 12 Å per second, as shown in FIG. Layer 3 is grown. Semiconductor layer 3 grown in this way
In the part grown directly on the single crystal semiconductor silicon substrate 1 through the window 2a of the mask layer 2, it grows as a single crystal layer 3A, and in the part grown on the mask layer 2, it grows as a polycrystalline layer 3B. grow up. In addition, the main surface 1a of the base 1 can be seen through the window 2a.
Part 3A epitaxially grown directly on
Below, a PN junction J is formed at a shallow position at a depth of about 300 Å from the main surface 1a of the base 1. Furthermore, the third
In the figure, the broken lines in the mask layer 2 schematically indicate the positions where impurity atoms enter.

The substrate 1 with the semiconductor layer 3 formed thereon is taken out from the Belgian 12 and, as shown in FIG. Form. In this case, the thickness of the semiconductor layer 3 is such that when the Al electrode 4 is deposited on the semiconductor layer 3, the Al atoms penetrate into the junction J and deteriorate the characteristics of the junction J or destroy it. The thickness is selected to such an extent that such problems will not occur, for example, about 1000 Å.

The semiconductor layer 3 formed in this way has impurities such as Sb doped into Si and is formed to have a low specific resistance at least in the single crystal portion 3A, so that the electrical resistance can be made sufficiently small. In addition, in the case of such a method, since a part of Si and Sb is ionized and bombarded with the substrate 1 while vapor phase growth is performed, the growth of the semiconductor layer 3 is performed by forming a window on the substrate 1. The crystallinity of the substrate surface is once destroyed by the Si and Sb ions directly implanted through 2a, and then the crystallinity of the substrate surface is recrystallized, that is, the crystal is recovered, and the semiconductor layer 3 is successively destroyed.
As a result, the portion directly grown on the main surface 1a of the substrate 1 through the window 2a epitaxially grows as a single crystal portion 3A with excellent crystallinity. Moreover, for this reason, the PN junction J thus formed is formed at a shallow position and as an excellent rectifying junction with good characteristics.

Note that the doping concentration of the impurity Sb to the semiconductor layer 3 is
This can be selected by selecting the heating temperature Tc of the impurity evaporation source 23. Fifth
The figure shows the measured relationship between this temperature Tc and the impurity concentration in the grown semiconductor layer. The square △ marks contain 0.6% Si and
It can be seen that in the case of 10% ionization, the concentration can be increased by ionizing Si, but there is almost no difference even if the ionization is increased beyond a certain level.

Formed by the manufacturing method of the present invention as described above
A PN junction is formed by generating an epitaxial semiconductor layer doped with impurities. In this case, a part of the epitaxial semiconductor layer is ionized to destroy the base crystal and recrystallize it, and the effect of ion implantation is Since the epitaxial growth is carried out using a mechanism of obtaining Semiconductor devices with specific characteristics can be mass-produced. In addition, by forming a shallow PN junction, it is possible to miniaturize the pattern, further improve characteristics and response speed, etc., as mentioned at the beginning. Since the resistivity single crystal semiconductor layer 3A is formed, there is no need to remove it, so there is no need to take the trouble of removing it, and in fact, the presence of this layer makes it difficult to remove metal electrodes such as Al. In depositing the semiconductor layer, this semiconductor layer can act as a buffer layer for breaking shallow junctions due to metal deposition.

In particular, in the present invention, during vapor deposition, Si forming the semiconductor layer 3, that is, the evaporated gas of the main constituent element, that is, a large amount of Si, is ionized and a small amount of impurity is present due to the charge exchange effect with this. For example, this method employs Sb ionization, which makes it possible to reliably and highly controllably ionize low-concentration impurity elements that exist in only a small amount relative to the entire structure, thereby improving the junction quality. It is possible to reliably form the semiconductor layer 3 and reduce the specific resistance of the semiconductor layer 3.

In the above example, a single vapor deposition source for the impurity Sb is provided separately from the Si vapor deposition source for the semiconductor material, but if the impurity material has a low vapor pressure, the compound containing the impurity may be Alternatively, this impurity can be mixed into the semiconductor material deposition source.

[Brief explanation of the drawing]

1, 3, and 4 are enlarged sectional views of each step showing an example of the manufacturing method of the present invention, FIG. 2 is a schematic sectional view of an example of an apparatus for implementing the manufacturing method of the present invention, and FIG. 5 is a It is a measurement curve diagram showing the relationship between the heating temperature of the impurity source and the amount of impurity doping. 1 is a semiconductor substrate, 2 is a mask layer, 2a is a window thereof, 3 is a semiconductor layer, and 4 is a metal electrode.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device including a step of forming a shallow junction on the surface of a semiconductor substrate, wherein the shallow junction is formed together with vapor deposition of a semiconductor layer containing impurities on the surface of the semiconductor substrate, and this vapor deposition , by ionizing a part of the vapor deposition material gas of the main constituent element of the semiconductor layer to ionize a part of the impurity and accelerating the impact toward the surface of the semiconductor substrate, A method for manufacturing a semiconductor device, characterized by forming a shallow junction on a surface and growing a single crystal semiconductor layer thereon.