JPH028274B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscilloscope with a multi-phenomenon display function.

In recent years, with the rapid development of electronic equipment that handles logical signals, the number of electrical circuits that have signals with complex cycles and many signal systems controlled by one signal has rapidly increased. When observing such a signal or a group of signals, regardless of the operating mode, if you simultaneously display the signal waveforms in the synchronization signal circuit on the screen of the cathode ray tube at any time, you can confirm the signal components that provide synchronization. This makes synchronization operations easier and less likely to cause errors, and the number of observed phenomena can be easily increased.Furthermore, several types of filtering circuits inserted into the synchronization signal circuit allow It is possible to ensure synchronization while observing the signal waveform from which specific frequency components are extracted and monitoring unnecessary frequency components.

The present invention provides an oscilloscope having the above functions. FIG. 1 shows an embodiment of the present invention, in which a so-called two-phenomenon oscilloscope having two channels of vertical axis input circuits is equipped with a synchronous signal monitoring channel. 1 is the vertical axis first channel input terminal, 2 is the vertical axis second channel input terminal
Channel input terminal, 3 is external synchronization signal input terminal, 4 is vertical axis first channel input circuit, 5 is its output terminal, 6 is vertical axis second channel input circuit, 7 is its output terminal, 8 is synchronization signal amplification circuit ,
9 is its vertical axis output terminal. 9' is a synchronization signal output terminal, 10 is a first channel internal synchronization signal generation terminal, 11 is a second channel internal synchronization signal generation terminal, 12 is an internal synchronization signal switching circuit, and 13
is an internal synchronization signal output terminal; 14 is a transistor that amplifies the first channel output signal; 15 is a transistor that amplifies the second channel output signal; 16 is a transistor that amplifies the second channel output signal;
is a transistor that amplifies the third channel output for displaying a synchronization signal, 17 is a diode D ₁ ,
D ₂ D ₃ , D ₄ , D ₅ , D ₆ , D ₇ , D ₈ , D ₉ , D ₁₀ , D ₁₁ ,
A channel switching gate circuit consisting of _D12 .
18 is an input stage transistor of the vertical axis output amplification circuit, 19 is the vertical axis output amplification circuit, and 20 is a terminal from which a vertical axis deflection output signal is generated. 21 is a JK flip-flop for switching the first channel, 22 is a K input terminal of this flip-flop 21, 23 is an output terminal of flip-flop 21, and 24 is a second
JK flip-flop for channel switching, 25
is the K input terminal of the flip-flop 24, 26 is the output terminal of the flip-flop 24, 27 is a JK flip-flop for switching the third channel for synchronizing signal display, 28 is the K input terminal of the flip-flop 27, 29 is the output terminal of the flip-flop 27,
Reference numeral 30 denotes a vertical axis operation mode changeover switch, which operates in conjunction with the parts connected by broken lines; at position a, one phenomenon display mode for only the first channel; at position b, one phenomenon display mode for only the second channel; and at position c. Now, the first
Instructs a two-phenomenon display format using a channel and a second channel. 31 is a switch that changes the operation of the third channel for displaying the synchronization signal, which is linked with the part connected by the broken line, and the position d is for no display operation, and the position for e is
The position indicates the display operation. 32 is an AND circuit, 33 is a NAND circuit for preventing malfunctions, 34 is a clock signal input line, and 35 is a multi-phenomenal display format changeover switch, which instructs the alternate display format at the f position and the CHOP display format at the g position. .
36 is a line to which the alternate switching pulse signal is applied, 37 is a line to which the CHOP switching pulse signal is applied,
38 is a CHOP switching pulse generation circuit.

Figure 2 shows the operating waveforms of this embodiment.a
denotes the clock signal on the line 34, b the first channel switching signal at the terminal 23, c the second channel switching signal at the terminal 26, and d the third channel switching signal for synchronization signal display at the terminal 29, respectively. Further, FIG. 3 shows an example of the image waveform on the screen of the cathode ray tube in this embodiment.

Next, the operation of this embodiment will be explained using FIGS. 1, 2, and 3.

(1) Operating state of only the first flip-flop.

At time t ₀ , vertical axis operation mode changeover switch 3
0 is connected to position a as shown in Figure 1 to display one phenomenon only on the first channel, and the third channel operation changeover switch 31 for synchronizing signal display is connected to position d to disable the third channel. In the display operation state, the K input terminal 22 and output terminal 23 of the first channel switching flip-flop 21 are coupled in phase through the AND circuit 32.
The K input terminal 25 of the flip-flop 24 for switching the second channel and the K input terminal 28 of the flip-flop 27 for switching the third channel are +5V H.
Connected to level voltage. The three JK flip-flops 21, 24, 27 receive the clock signal 34.
Since the signal level of the K input is transmitted to the output terminal when the voltage changes from an L level voltage to an H level voltage, if a clock signal is generated at time _t1 , the first channel switching flip-flop 21 is always activated.
The output terminal 23 of the flip-flop 24 for switching the second channel is at the L level, and the output terminal 23 of the second channel switching flip-flop 24 is at the L level.
6 becomes H level, and the output terminal 29 of the third channel switching flip-flop 27 becomes H level, and remains in the same state for subsequent clock signals. On the other hand, the output terminal of the channel switching circuit 17 is received at the emitter having extremely low input impedance of a base-grounded balanced amplifier circuit consisting of a transistor 18 and an amplifier circuit 19.
The emitter voltage is set approximately midway between the L level voltage and the H level voltage indicated by the output of each flip-flop, and therefore the diodes D ₁ , D ₄ ,
D ₆ , D ₇ , D ₁₀ , and D ₁₁ are biased in a conductive state, and diodes D ₂ , D ₃ , D ₅ , D ₈ , D ₉ , and D ₁₂ are biased in a non-conductive state.

Therefore, only the signal of the first channel is transmitted to the transistor 18 and the vertical axis output amplification circuit 19, and the vertical axis operation mode of the oscilloscope becomes one phenomenon display of only the first channel, as shown as an example in FIG. 3a.

(2) Operating state of only the second flip-flop.

This means that the vertical axis operation mode changeover switch 30
It can be explained in the same way if it is connected to position b and one phenomenon is displayed only in the second channel. In that case, the operation of the part related to the first channel and the part related to the second channel are completely opposite. Since the other parts are exactly the same, the explanation will be omitted.

(3) A method in which the first and third flip-flops are operated alternately.

Next, at time _t2, when the operation changeover switch 31 of the third channel for synchronizing signal display is switched to the position e while only one phenomenon is displayed on the first channel, the flip-flop 2 for switching the first channel is turned on.
The output terminal 23 of the third channel switching flip-flop 27 is connected to the K input terminal 28 of the third channel switching flip-flop 27.
The output terminal 29 of 7 is ANDed to the K input terminal 22 of the flip-flop 21 for switching the first channel.
Since these two flip-flops 22 and 27 are connected through the circuit 32, they constitute a binary ring counter. Therefore, when a clock signal is generated at time _t3 , the L level of the output terminal 23 of the first channel switching flip-flop 21 is transmitted to the output terminal 29 of the third channel switching flip-flop 27, and the output of the third channel switching flip-flop 27 is transmitted to the output terminal 29 of the third channel switching flip-flop 27. Time at terminal 29
The H level that was in the state before _t3 is the output terminal 23 of the flip-flop 21 for switching the first channel.
It is transmitted to

Subsequently, when the clock signal is input again at time _t4 , both flip-flops 21 and 27 transmit the respective input levels at the K input obtained from the output of the previous stage to each output, that is, the output of the first channel switching flip-flop 21 becomes L. return to level,
The Q output of the third channel switching flip-flop 27 returns to H level.

In this way, when the next clock signal is input at time _t5 , the entire circuit will be exactly the same as at time _t3 ,
Similar operations are repeated with subsequent generation of clock signals. In this state, the K input terminal 25 of the flip-flop 24 for switching the second channel
remains at the H level, and therefore the output terminal 26 also remains at the H level. At this time, the channel transmitted to the vertical axis output amplification circuits 18 and 19 and shown on the screen of the cathode ray tube is the one in which the output of the switching flip-flop is at the L level, so from time t ₃ to time t ₄ the channel is the third channel.
The channel signal is displayed on the first channel from time _t4 to time _t5 , and the third channel is shown again from time _t5 to time _t6 , and so on every time a clock signal arrives. A switching display is performed between. As a result, on the screen of the cathode ray tube, as shown in Figure 3b, in addition to the single phenomenon waveform of the first channel shown in Figure 3a, the synchronization signal waveform of the third channel is also displayed. .

(4) A state in which the second and third flip-flops are operated alternately.

The above operation can be similarly explained in the case of simultaneous display operation of the third channel when only one phenomenon is displayed on the second channel, and
The operation is completely the same except that the operations of the channel-related portion and the second channel-related portion are completely reversed.

(5) A state in which the first and second flip-flops are operated alternately.

Next, at time _t7 , the third channel operation changeover switch 31 is connected to the position d to make the third channel signal non-displayed, and the vertical axis operation mode changeover switch 30 is connected to the bottom position shown in FIG. c.
When connected to the position, the K input terminal 28 of the third channel switching flip-flop 27 is connected to the H level voltage of 5 volts, and the first channel switching flip-flop 21 and the second channel switching flip-flop 24 form a binary ring counter circuit. will now be configured. The operation is the same except that the state from time t ₂ to time t ₇ and the parts related to the second channel and the parts related to the third channel are completely reversed, so a repeated explanation will be omitted.

Therefore, when the clock signal is generated after time _t8 , the vertical axis circuit displays switching between the first channel and the second channel, and the two-phenomenal signal is displayed on the screen of the cathode ray tube as shown in FIG. 3c as an example. will be carried out.

(6) A state in which the first, second, and third flip-flops are sequentially switched and operated.

Next, at time _t9 , the operation changeover switch 31 of the third channel is connected to position e to set the display operation state, leaving the two-phenomenon display operation state of the first channel and the second channel unchanged, and the third channel is switched. The K input terminal 28 of the flip-flop 27 for switching the second channel is connected to the output terminal 26 of the flip-flop 24 for switching the second channel, and the output terminal 29 of the flip-flop 27 for switching the third channel is connected to the K input of the flip-flop 21 for switching the first channel through the AND circuit 32. Since it is connected to the terminal 22, the first, second, and third channel switching flip-flops 21, 24,
27 constitutes a ternary ring counter circuit. Therefore, when the clock signal is generated at time _t10 , the L level indicated by the Q output terminal 23 of the first channel switching flip-flop 21 is transferred to the output terminal 26 of the second channel switching flip-flop 24, and the L level is transferred to the output terminal 26 of the second channel switching flip-flop 24. The outputs 23, 29 of the channel switching flip-flops 21, 27 are at H level.

Furthermore, when a clock signal is generated at time _t11 , the L level of the Q output of the flip-flop 24 for switching the second channel is transferred to the output terminal 29 of the flip-flop 27 for switching the third channel, and the flip-flop 21 for each of the first and second channels switches. , 24 output terminals 23 and 26 are H
level.

Thereafter, when a clock signal is generated at time _t12 , the third channel switching flip-flop 27
The L level of the output terminal 29 of is connected to the AND circuit 32.
to the output terminal 23 of the first channel switching flip-flop 21 through the second and third channels.
flip-flop 24 for switching each channel,
The output terminals 26 and 29 of 27 become H level, and the entire circuit completely returns to the state at time _t9 .

Therefore, in accordance with the subsequent generation of the clock signal, the entire circuit repeats the operation from time _t9 to time _t12 , and the vertical axis output amplification circuits 18 and 19 have the first channel → second channel → third channel. →The signals of each channel are connected one channel at a time repeatedly in the order of the first channel. In this way, the synchronizing signal waveform of the third channel is displayed on the screen of the cathode ray tube in addition to the two-phenomenon display waveform of FIG. 3c, as shown as an example in FIG. 3d.

Note that the clock signal used in the above operation is connected to line 3 by the multi-phenomenal display format changeover switch 35.
6 alternate switching pulse signal or line 3
Although any one of the 7 CHOP switching pulse signals can be selected and used, the differences in their respective operations have little meaning in the explanation of the present invention, and will therefore be omitted. In addition, in the NAND circuit 33, all of the output terminals 23, 26, 29 of the flip-flops 21, 24, 27 for channel switching go to H level, or all of them go to L level immediately after power is turned on or when the operation mode of the circuit is switched. This circuit is designed to prevent malfunctions in which the signals of either channel are not passed to the vertical output amplifier circuits 18 and 19, or the signals of two or more channels are supplied at the same time. When it occurs
The output of the NAND circuit 33 is passed through the AND circuit 32 to the channel switching flip-flops 21, 24,
27 to escape from the malfunctioning state to the normal operating state.

Therefore, the NAND circuit 33 to the AND circuit 32
The output of shows H level during normal operation, so
The AND circuit 32 functions as a mere buffer amplifier circuit for signals sent to other input terminals during normal operation, and the output of the AND circuit 32 as a logic signal can be considered to be the same as the input signal input from the switch 31. As described above, according to this embodiment, it is possible to satisfy the vertical axis function of a normal two-phenomenon oscilloscope, and at the same time to display the synchronizing signal waveform at any time in any operation mode.

As described above, according to the present invention, it is possible to provide an oscilloscope that can display synchronized signal waveforms in both single-phenomenon display operation and multi-phenomenon display operation for vertical axis input, thereby greatly increasing the number of phenomena that can be displayed. It has a function that can be easily increased, a function that allows you to observe the sync signal waveform, and a function that allows you to check the frequency component discrimination effect of the signal obtained through the filter circuit inserted in the sync signal circuit as a waveform on the screen of the cathode ray tube. can be done.
Methods to obtain this function include temporarily displaying only the synchronization signal system signal on the CRT screen instead of the vertical channel signal, or displaying the synchronization signal circuit signal together only during multi-phenomenal display. Although it is conceivable, it would be extremely inferior in terms of simultaneous measurement, speed, and degree of freedom of operation. Furthermore, when measuring signals with a long repetition period, the brightness of the image tends to decrease, so it is necessary to reduce the number of phenomena to be displayed as much as possible, and when performing simple measurements, it is generally overwhelming to display only one phenomenon. It is very useful that the waveform observation function of the synchronization signal circuit can be performed even in the case of such vertical axis one-channel display operation.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram of the main parts of a multiphenomenal oscilloscope according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram of the main parts, and FIG. 3 is a diagram showing the state displayed on the oscilloscope. 8... Synchronous signal amplification circuit, 17... Channel gate switching circuit, 21, 24, 27... Flip-flop.

Claims (1)

[Claims] 1 A first channel gate circuit that controls the input signal of the first channel on and off, a second channel gate circuit that controls the input signal of the second channel on and off, and a synchronization signal gate that controls the synchronization signal on and off. a vertical axis output amplification circuit that synthesizes the output signals of these gate circuits and applies it to the CRT as a vertical axis signal, and a vertical axis output amplifier circuit that individually controls the first and second channel gate circuits and the synchronization signal gate circuit. The first, second, and third flip-flops are switched and connected to each other, and the operating state of only the first flip-flop, the operating state of only the second flip-flop, and the operating state of the first, second, and third flip-flops are controlled. A state in which the second flip-flop is operated alternately, a state in which the first and third flip-flops are operated alternately, a state in which the second and third flip-flops are operated alternately,
A multi-phenomenon oscilloscope is provided with a change-over switch that can obtain six states in which the first, second, and third flip-flops are sequentially switched and operated.