JPH028346B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for forming a lattice-like wiring pattern that can automatically form a non-conducting pattern in a lattice-like wiring pattern that becomes the power supply wiring or ground wiring of an electronic circuit board. It is related to.

[Conventional technology]

Electronic circuit boards generally have multilayer wiring configurations, and grid-like patterns with a pitch of several millimeters are relatively often used for power supply wiring or ground wiring. When forming component insertion holes, connection pin insertion holes, etc. in such a grid wiring pattern, it is necessary to remove a part of the grid wiring pattern so as not to contact the wiring pattern.

In recent years, wiring patterns for electronic circuit boards like this have been created using computers.
In the case of a lattice-like wiring pattern, data such as the width and spacing of the lattice-like wiring pattern are stored in a file, so by reading out that data and inputting information that defines the outer circumference, the specified periphery can be determined. A grid-like wiring pattern according to the read data is formed within the outer periphery and displayed on the display device. Then, an input operation is performed on the displayed lattice-like wiring pattern to form a non-conducting pattern corresponding to a component insertion hole or the like.

When a desired wiring pattern is formed, the data is added to an artwork device or the like to automatically create a film that serves as an exposure mask for forming the wiring pattern.

[Problem that the invention seeks to solve]

Input of the non-conducting pattern to the grid wiring pattern is performed using an input device such as a keyboard or mouse, but a predetermined interval must be maintained so that the insertion hole etc. and the grid wiring pattern do not come into contact. Therefore, it is necessary to erase the lattice sides of the lattice wiring pattern in relation to the dimensions of the non-conductive pattern to be formed, which is a complicated task as well as specifying the placement position. It was hot. Moreover, when there are a large number of such non-conducting patterns, there is a drawback that the working time for forming the respective non-conducting patterns by hollowing them out in the grid-like wiring pattern becomes very long.

The present invention aims to improve the above-mentioned conventional drawbacks.

[Means for solving problems]

The method for forming a lattice-like wiring pattern of the present invention assumes that the width of the lattice-like wiring pattern is zero, and enlarges a non-conducting pattern to be formed within the lattice-like wiring pattern. The dimension is the sum of 1/2 of the width of the wiring pattern and the minimum distance required between the non-conducting pattern and the wiring pattern. Then, by erasing the lattice sides of the lattice-like wiring pattern within the expanded non-conductive pattern, a lattice-like wiring pattern is formed in which the non-conductive pattern is hollowed out with a predetermined interval between it and the wiring pattern. It is something.

[Effect]

The value obtained by adding 1/2 the width of the lattice wiring pattern and the minimum interval required between the non-conductive pattern and the wiring pattern is added to the non-conductive pattern and expanded, and this expanded non-conductive pattern is This method erases the lattice sides of the lattice wiring pattern in the conductive pattern to create a lattice wiring pattern with a predetermined interval between the wiring pattern and the non-conductive pattern, and it also involves enlarging the non-conducting pattern, Grid side deletion processing can be achieved by applying enlargement/reduction processing in figure processing, figure overlap deletion processing, etc., and by simply inputting the outer circumference data, non-conducting patterns can be automatically erased. It is possible to create a lattice-like wiring pattern with hollow holes.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
1 is a processor (CPU), 2 is a memory (MEM) that has areas A, B, and C as well as an area that stores programs, etc., 3, 4, and 5 are input/output control units (I/O), and 6 is a keyboard. 7 is a display device, 8 is an artwork device which performs exposure, development, etc. according to pattern data and outputs a film such as a mask pattern, and 9 is a file device. The file device 9 stores circuit pattern data including data such as the wiring width and pitch of the lattice wiring pattern, non-conducting pattern data, and the like.

First, under the control of the processor 1, circuit pattern data is read from the file device 9 and stored in area A of the memory 2. Next, outer circumference data specifying the outer circumference of the lattice wiring pattern is inputted from the input device 6. Processor 1 stores this peripheral data in area B of memory 2. Then, the processor 1 reads the outer circumference data and the lattice wiring pattern data of the circuit pattern data, generates a lattice pattern within the specified outer circumference, and stores it in area B of the memory 2. , to the display device 7 via the input/output control device 4. Thereby, a grid pattern of a predetermined pitch is displayed on the display device 7 within the designated outer periphery.

Next, the processor 1 reads out one piece of non-conducting pattern data from the area A of the memory 2, enlarges this non-conducting pattern, and expands the non-conducting pattern data from the area A of the memory 2.
Store in. This enlargement process assumes that the line width of the lattice wiring pattern is zero, and calculates (width of the lattice wiring pattern) x (1/2) + (minimum spacing between conductors) = additional dimension. It performs arithmetic processing to add the value of the additional dimension to the dimension of the non-conductive pattern, and can be realized by processing similar to enlargement and reduction processing in graphic processing.

Next, processor 1 processes areas B and C of memory 2.
This is to identify the overlap between the lattice pattern read from the lattice pattern and the enlarged non-conducting pattern. In addition,
Since the non-conducting pattern data also includes position data specifying the arrangement position, it is possible to easily identify when a portion of the enlarged non-conducting pattern overlaps with the lattice pattern. Then, the lattice sides of the lattice pattern within the non-conductive pattern are erased. In this case, the lattice sides that intersect with the outer periphery of the enlarged non-conductive pattern are also erased. This grid edge elimination process is
This can be realized by a process similar to the process of erasing overlapping parts of figures in graphic processing. The lattice pattern whose lattice sides have been erased is stored in area B of the memory 2.

If a non-conducting pattern remains in area A of the memory 2, one of the remaining non-conducting patterns is read out, and the same enlargement process as described above is performed, and the lattice sides of the lattice pattern stored in area B are erased. The data is processed and stored in area B of the memory 2.

The process of erasing grid edges may result in grid edges that are completely separated from the surrounding grid pattern. In such a case, process to make it continuous with the surrounding grid pattern by adding grid edges, or
Processing such as changing the arrangement position of the non-conducting pattern will be performed.

When all the processing for the non-conducting pattern is completed, the area B of the memory 2 stores the data of the lattice-like wiring pattern in which the non-conducting pattern has been hollowed out. When data is output to the artwork device 8 via the input/output control device 5, a grid wiring pattern
By exposing and developing a pattern according to the data, a lattice wiring pattern film for an electronic circuit board is created and output.

FIGS. 2 and 3 are explanatory diagrams of the grid-like wiring pattern, and the outer peripheral data of the grid-like wiring pattern include a(x ₁ , y ₁ ), b(x _l , y _j ), c(x _n , y _j ), d
(x _n , y _k ), e (x _i , y _k ), f (x _i , y _l ) from the input device 6
Input from etc. It is also possible to employ means for directly inputting this outer circumference data onto the display screen of the display device using a light pen or the like. Furthermore, in the case of a rectangular outer periphery, it is sufficient to input coordinate information of four points.

Also, the lattice wiring pattern data is read out as described above, and a lattice pattern of a predetermined pitch is formed within the designated outer periphery a to f. Also, hatched P1, P2, and P3 indicate non-conductive patterns, and the data of these non-conductive patterns P1, P2, and P3 are sequentially read out from area A of the memory 2.
The image is enlarged as shown by the chain line. As mentioned above, this enlargement process assumes that the line width of the lattice wiring pattern is zero, and requires 1/2 of the width of the lattice wiring pattern and the space between the wiring pattern and the non-conducting pattern. The process of adding the sum of the minimum distance and the minimum interval to the non-conductive patterns P1, P2, and P3 as an additional dimension is performed.

By erasing the lattice sides of the lattice pattern within the enlarged non-conducting pattern, that is, within the chain lines, the non-conducting patterns P1, P2,
A grid-like wiring pattern is formed in which hollow regions N1, N2, and N3 are formed around P3. The non-conducting pattern and the wiring pattern have an interval equal to at least 1/2 of the width of the lattice wiring pattern plus the minimum necessary interval, so even if parts are inserted, there will be no short circuit. This results in a wiring pattern that does not cause accidents.

Furthermore, depending on the arrangement position of the non-conductive pattern, the grid-like wiring pattern may be separated into islands. This can be detected by sequentially scanning the created lattice-like wiring pattern and checking whether there is a wiring pattern surrounded by a hollow area. If it is detected that there is a lattice side, a grid side is added or the placement position of the non-conductive pattern is changed.

FIG. 4 shows an example of a flowchart of an embodiment of the present invention, in which circuit pattern data is read from the file device 9, stored in area A of the memory 2, and outer circumference data specifying the outer circumference is input to the input device. 6
Input from etc. Thereby, lattice wiring pattern data is read from area A, and a lattice pattern is generated within the designated outer periphery.

Next, the non-conductive pattern data is read from area A of the memory 2, the non-conductive pattern is enlarged, and the lattice sides in the enlarged non-conductive pattern are erased to form a lattice with hollows formed. The wiring pattern data is stored in area B of the memory 2.

It is determined whether or not a non-conductive pattern remains in the area A of the memory 2, and if it remains, the non-conductive pattern is read out, and if it does not remain, the formation of the lattice wiring pattern is performed. This means that the data is transferred to the artwork device 8, and a lattice wiring pattern film is created and output.

〔Effect of the invention〕

As explained above, the present invention assumes that the width of the lattice wiring pattern is zero, and creates a non-conductive pattern for inserting a component to be formed in the lattice wiring pattern by adjusting the width of the lattice wiring pattern. The lattice of the lattice-like wiring pattern within this enlarged non-conducting pattern is enlarged to the sum of 1/2 of By performing the process of erasing the edges,
It forms a lattice-like wiring pattern in which non-conducting patterns are cut out, and by simply inputting the outer circumferential data of the lattice-like wiring pattern, the inner part corresponding to the non-conducting pattern in the desired circuit pattern is automatically created. Since punching can be formed, there is an advantage that a grid wiring pattern for an electronic circuit board can be formed easily and in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams of the process of creating a grid wiring pattern, and FIG. 4 is an example of a flowchart of an embodiment of the present invention. be. 1 is a processor (CPU), 2 is a memory (MEM), 3 to 5 are input/output control devices (I/O),
6 is an input device, 7 is a display device, 8 is an artwork device, and 9 is a file device.

Claims (1)

[Claims] 1. In a method for creating a lattice wiring pattern for an electronic circuit board in which a non-conductive pattern is hollowed out, the width of the lattice wiring pattern is assumed to be zero, and the The conductive pattern is enlarged to a dimension equal to the sum of 1/2 the width of the lattice-like wiring pattern and the minimum interval required between the non-conductive pattern and the wiring pattern, and the expanded non-conductive pattern 1. A method for forming a lattice-like wiring pattern, the method comprising: erasing the lattice sides of the lattice-like wiring pattern inside the lattice-like wiring pattern to remove the inside of the non-conducting pattern.