JPH02854B2 - - Google Patents
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- Publication number
- JPH02854B2 JPH02854B2 JP59121563A JP12156384A JPH02854B2 JP H02854 B2 JPH02854 B2 JP H02854B2 JP 59121563 A JP59121563 A JP 59121563A JP 12156384 A JP12156384 A JP 12156384A JP H02854 B2 JPH02854 B2 JP H02854B2
- Authority
- JP
- Japan
- Prior art keywords
- transfer plate
- semiconductor chips
- polarity
- defective
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】
[発明の技術分野]
本発明は多数の半導体チツプをその極性を特定
方向に揃えて整列させる半導体チツプの整列方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor chip alignment method for aligning a large number of semiconductor chips with their polarities aligned in a specific direction.
[従来技術]
半導体素子を量産する場合、例えば第3図に示
すように所定のP−N接合を形成した半導体ウエ
ハ1を個々の半導体チツプ2に分割した後、この
チツプ2の電気的特性をチエツクしながら1個毎
に図示を省略した真空ピンセツトで吸着しリード
フレーム3上の所定位置に搭載し以後所定の処理
が施されるという方法が採られている。[Prior Art] When mass producing semiconductor devices, for example, as shown in FIG. 3, a semiconductor wafer 1 on which a predetermined PN junction is formed is divided into individual semiconductor chips 2, and then the electrical characteristics of the chips 2 are determined. A method is adopted in which each piece is picked up using vacuum tweezers (not shown) while being checked, mounted at a predetermined position on the lead frame 3, and then subjected to predetermined processing.
あるいはリードフレーム3に搭載する前にシー
ト4上の個々に分割された半導体チツプ2の特性
をチエツクした後、別に用意されたトレイに1個
毎に真空ピンセツトで吸着し極性を揃えこれをさ
らにリードフレーム3上に移すという方法が採ら
れている。 Alternatively, after checking the characteristics of the individually divided semiconductor chips 2 on the sheet 4 before mounting them on the lead frame 3, the semiconductor chips 2 are sucked one by one onto a separately prepared tray using vacuum tweezers to align the polarity and then lead further. A method is adopted in which the image is moved onto frame 3.
しかるに上記の方法による場合、多数かつ小片
の半導体チツプを手作業で取扱うので作業能率が
向上しないという欠点があつた。 However, the above method has the disadvantage that work efficiency cannot be improved because a large number of small pieces of semiconductor chips must be handled manually.
[発明の概要]
本発明は上記の事情に基づきなされたもので、
半導体チツプの電気的特性および極性をチエツク
しつつ良品の半導体チツプのみを特定方向に極性
を揃えて大量に整列させることができる半導体チ
ツプの整列方法を提供することを目的とする。[Summary of the invention] The present invention has been made based on the above circumstances, and
To provide a semiconductor chip arranging method capable of arranging only non-defective semiconductor chips in large quantities with their polarities aligned in a specific direction while checking the electrical characteristics and polarity of the semiconductor chips.
[発明の実施例]
以下に本発明の一実施例につき第1図および第
2図を参照して説明する。[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
第1図は本発明の方法を実施するための装置の
要素を概略的に示したものである。 FIG. 1 schematically shows the elements of an apparatus for carrying out the method of the invention.
同図において10は第1の転写板、11は第2
の転写板であつて、これらはその表面には縦、横
に半導体チツプを収納するための多数の凹所10
a,11aが形成されこの凹所10a,11aは
同一ピツチおよび第2の転写板11上に第1の転
写板10を反転させて重ね合せた場合に相互に一
致する位置に形成されている。 In the figure, 10 is the first transfer plate, 11 is the second transfer plate, and 11 is the second transfer plate.
These are transfer plates having a large number of recesses 10 vertically and horizontally on the surface for storing semiconductor chips.
The recesses 10a and 11a are formed at the same pitch and at positions that coincide with each other when the first transfer plate 10 is inverted and stacked on the second transfer plate 11.
上記第1の転写板10および第2の転写板11
は絶縁材料で形成され上記第1の転写板10には
凹所10aに連通する導体12が設けられてい
る。 The first transfer plate 10 and the second transfer plate 11
is made of an insulating material, and the first transfer plate 10 is provided with a conductor 12 communicating with the recess 10a.
この導体12は凹所10a内に収納される半導
体チツプ13の一方の面に接触し電気的特性およ
び極性をチエツクする際の共通電極となる。 This conductor 12 contacts one surface of the semiconductor chip 13 housed in the recess 10a and serves as a common electrode for checking electrical characteristics and polarity.
また、第1の転写板10には各凹所10aに通
じる透孔10bが設けられこの透孔10bはメイ
ン通路10cに連通し、このメイン通路10cは
その一端が真空ポンプ14に接続される。 Further, the first transfer plate 10 is provided with a through hole 10b communicating with each recess 10a, and this through hole 10b communicates with a main passage 10c, and one end of this main passage 10c is connected to a vacuum pump 14.
15は半導体チツプ13の電気的特性および極
性をチエツクするための測定用移動ヘツドであつ
てこのヘツド15には第1の転写板10の凹所1
0aのピツチに一致するピツチの複数の測定針1
5aを有する。この測定針15aはそれぞれ接続
線16を介して測定電源17に接続されこの測定
電源17は制御装置18に連結されている。 Reference numeral 15 denotes a moving measuring head for checking the electrical characteristics and polarity of the semiconductor chip 13.
A plurality of measuring needles 1 whose pitch matches the pitch of 0a
It has 5a. The measuring needles 15a are each connected to a measuring power source 17 via a connecting line 16, and the measuring power source 17 is connected to a control device 18.
制御装置18では測定針15aで測定した半導
体チツプ13の電気的特性および極性を記憶し、
特性不良および特定極性の半導体チツプ13のみ
を吸着するように後述の真空吸着ノズルに出力指
令を与えるとともに半導体チツプ13の吸着移動
工程中に特性不良の半導体チツプ13の吸着を解
除するように真空吸着ノズルに指令を与える機能
を備えている。 The control device 18 stores the electrical characteristics and polarity of the semiconductor chip 13 measured by the measuring needle 15a,
An output command is given to a vacuum suction nozzle, which will be described later, so as to pick up only semiconductor chips 13 with poor characteristics and a specific polarity, and vacuum suction is performed to release semiconductor chips 13 with poor characteristics from being picked up during the suction movement process of the semiconductor chips 13. It has the function of giving commands to the nozzle.
19は吸着ノズル台であつて、このノズル台1
9には前記凹所10a,11aのピツチに合せた
複数の吸着ノズル19aが設けてあり、この吸着
ノズル19aはそれぞれ真空バルブ19bを介し
て真空ポンプ20に接続されている。 19 is a suction nozzle stand, and this nozzle stand 1
9 is provided with a plurality of suction nozzles 19a matching the pitch of the recesses 10a, 11a, and each of the suction nozzles 19a is connected to a vacuum pump 20 via a vacuum valve 19b.
上記の吸着ノズル台19は制御装置18の出力
指令によつて第1の転写板10、第2の転写板1
1間の水平移動およびそれらの所定列への昇降を
なすように構成されている。 The suction nozzle stand 19 is connected to the first transfer plate 10 and the second transfer plate 1 according to an output command from the control device 18.
1 horizontal movement and raising and lowering them to predetermined columns.
図中、21は第1の転写板10と第2の転写板
11の間に配置された不良半導体チツプ収納箱で
ある。 In the figure, 21 is a defective semiconductor chip storage box disposed between the first transfer plate 10 and the second transfer plate 11.
次に上記構成の装置を用いて本発明の半導体チ
ツプの整列方法について述べる。 Next, a method for aligning semiconductor chips according to the present invention will be described using the apparatus configured as described above.
まず所定のP−N接合が形成された半導体ウ
エハから個々の細片チツプに分割された半導体
チツプ13が第1の転写板10の凹所10aに
供給される。 First, semiconductor chips 13, which are divided into individual chip chips from a semiconductor wafer on which predetermined PN junctions have been formed, are supplied to the recesses 10a of the first transfer plate 10.
制御装置18からの指令により測定用移動ヘ
ツド15が第1の転写板10の第1列目の凹所
10a上に下降しその測定針15aを各凹所1
0a内の半導体チツプ13の表面に接触させ
る。 In response to a command from the control device 18, the measuring movable head 15 descends onto the first row of recesses 10a of the first transfer plate 10, and the measuring needles 15a are moved to each recess 1.
It is brought into contact with the surface of the semiconductor chip 13 in 0a.
半導体チツプ13の下面は導体12に接触
し、この導体12は接続線22を介して測定電
源17に接続され閉回路を構成し、半導体チツ
プ13の耐圧、順方向特性等の電気的特性の良
品、不良品と、極性を測定し、その測定結果を
制御装置18で記憶する。 The lower surface of the semiconductor chip 13 is in contact with a conductor 12, and this conductor 12 is connected to a measurement power source 17 via a connecting wire 22 to form a closed circuit, and the semiconductor chip 13 has good electrical characteristics such as withstand voltage and forward characteristics. , defective products, and polarity are measured, and the measurement results are stored in the control device 18.
次に測定用移動ヘツド15を所定位置まで上
昇させた後、同じく制御装置18からの指令に
より吸着ノズル台19を水平方向に移動しかつ
第1の転写板10の第1列目の凹所10a上に
下降させる。 Next, after raising the measurement moving head 15 to a predetermined position, the suction nozzle stand 19 is moved in the horizontal direction according to a command from the control device 18, and the recess 10a of the first row of the first transfer plate 10 is moved. lower to the top.
制御装置18では記憶した測定結果に基づき
特定方向の極性および特性不良の半導体チツプ
13を判別し、これらのチツプ13のみを吸着
すべく真空バルブ19bに「開」の出力指令を
出す。 Based on the stored measurement results, the control device 18 determines which semiconductor chips 13 have polarity in a particular direction and which have defective characteristics, and issues an "open" output command to the vacuum valve 19b in order to attract only these chips 13.
これにより真空ポンプ20から真空が吸着ノ
ズル19aに供給され特定方向の極性に対して
反対極性となる半導体チツプ13を残して他の
半導体チツプ13が吸着ノズル19aに吸着さ
れる。 As a result, vacuum is supplied from the vacuum pump 20 to the suction nozzle 19a, and the other semiconductor chips 13 are suctioned by the suction nozzle 19a, except for the semiconductor chips 13 whose polarity is opposite to the polarity in the specific direction.
制御装置18の出力指令により吸着ノズル台
19が所定位置まで上昇した後、不良半導体チ
ツプ収納箱21の位置まで水平移動し、ここで
同じく制御装置18の出力指令により特性不良
と判別された半導体チツプ13を吸着している
吸着ノズル19aの真空バルブ19bを「閉」
にすべく出力指令を出し、吸着ノズル19aか
ら特性不良と判別された半導体チツプ13を不
良半導体チツプ収納箱21内に落下させる。 After the suction nozzle stand 19 is raised to a predetermined position by the output command from the control device 18, it is horizontally moved to the position of the defective semiconductor chip storage box 21, where it picks up the semiconductor chips determined to have defective characteristics by the output command from the control device 18 as well. "Close" the vacuum valve 19b of the suction nozzle 19a that is suctioning 13.
An output command is issued to make the semiconductor chips 13 with defective characteristics fall from the suction nozzle 19a into the defective semiconductor chip storage box 21.
次いで、再び吸着ノズル台19を第2の転写
板11の対応例、例えば第1の転写板10の
[]列を移動しているときには第2の転写板
11の[]列の直上位置まで水平移動させた
後、下降させ凹所11a内に半導体チツプ13
を収納する。 Next, the suction nozzle stand 19 is moved horizontally again to the corresponding example of the second transfer plate 11, for example, when moving the column [] of the first transfer plate 10, to a position directly above the column [] of the second transfer plate 11. After moving, the semiconductor chip 13 is lowered into the recess 11a.
to store.
こうして第2の転写板11の[]列には同
一極性に揃えられた半導体チツプ13が先の不
良半導体チツプおよび第1の転写板10に残さ
れた半導体チツプ13を除いて所謂歯抜けの状
態で整列される。 In this way, the semiconductor chips 13 aligned with the same polarity are in the [] column of the second transfer plate 11, except for the previous defective semiconductor chip and the semiconductor chips 13 left on the first transfer plate 10, in a so-called missing state. are aligned.
以上の動作を最終列まで繰返した後、次の工
程に移る。 After repeating the above operations until the final row, move on to the next step.
第1の転写板10の内部に設けたメイン通路
10cに連通する外部パイプ10dに制御装置
18の出力指令により真空バルブ14aを開き
真空ポンプ14からの真空を供給し第1の転写
板10の凹所10aに残つた良品かつ前記特定
極性と反対極性の半導体チツプ13を吸着しつ
つ第1の転写板10を第2の転写板11上に反
転させて重ね合せ第2図Bに示す状態とする。 The vacuum valve 14a is opened in response to an output command from the control device 18 to supply vacuum from the vacuum pump 14 to the external pipe 10d communicating with the main passage 10c provided inside the first transfer plate 10, and the recess of the first transfer plate 10 is The first transfer plate 10 is inverted onto the second transfer plate 11 while adsorbing the remaining non-defective semiconductor chips 13 of the polarity opposite to the specific polarity 10a, and the first transfer plate 10 is superimposed on the second transfer plate 11 to form the state shown in FIG. 2B. .
制御装置18からの出力指令により真空バル
ブ14aを閉じ、凹所10a内への真空の供給
を断つと、凹所10a内の残余の半導体チツプ
13が反転されて第2の転写板11の凹所11
a内に移る。 When the vacuum valve 14a is closed in response to an output command from the control device 18 and the supply of vacuum to the recess 10a is cut off, the remaining semiconductor chips 13 in the recess 10a are turned over and transferred to the recess of the second transfer plate 11. 11
Move inside a.
最後に制御装置18からの出力指令により第
1の転写板10を初期位置に復帰させた後、第
2の転写板11の半導体チツプ13が収納され
ていない部分、すなわち特性不良として取除か
れた第1の転写板10の凹所10aに対応する
凹所11aの部分にはその数も少いため手作業
により特定方向に極性を揃えて半導体チツプ1
3を補充する。 Finally, after the first transfer plate 10 is returned to the initial position by an output command from the control device 18, the portion of the second transfer plate 11 where the semiconductor chip 13 is not housed, that is, the part with defective characteristics, is removed. Since the number of recesses 11a corresponding to the recesses 10a of the first transfer plate 10 is small, the semiconductor chip 1 is manually aligned in a specific direction.
Replenish 3.
なお、測定針15aおよび吸着ノズル19a
のピツチは転写板10a,11aのピツチの一
つおきのピツチとして、1列の穴を2回に分け
て測定、吸着を行いチツプを移動させることに
より、微小サイズのチツプを取り扱うこともで
きる。 Note that the measuring needle 15a and the suction nozzle 19a
By setting the pitch at every other pitch of the transfer plates 10a and 11a, and moving the chips by measuring and suctioning the holes in one row twice, micro-sized chips can also be handled.
[発明の効果]
本発明は上記のように構成したので、第2の転
写板上には半導体チツプの極性がすべて同一方向
に揃えられしかも一列毎に同時に自動的に行なわ
れるので、整列作業の作業能率を向上させるとと
もに次工程の例えば半導体チツプをリードフレー
ムに供給する場合に極性が同一方向に揃えられて
いるので、容易に供給工程の自動化が可能であ
る。すなわち、半導体ウエハ内に多数個の素子を
作り込んで、粘着テープ上で個々の半導体チツプ
に分割し、この半導体チツプの電気的特性検査後
に不良チツプのみを除去したものでは、粘着テー
プ上に不良チツプの抜け跡があり、そのため、前
記半導体チツプをリードフレーム上に複数個単位
で載置する場合に、不良チツプを除去した部分
は、リードフレーム上に半導体チツプが載置され
ないことになり、何んらかの補充工程を付加しな
ければ、半導体チツプ供給工程の自動化ができな
い。しかしながら本発明では良品半導体チツプが
抜けなく転写板上に整列させているので、リード
フレーム上で列単位で容易に自動供給が可能とな
る。[Effects of the Invention] Since the present invention is constructed as described above, the polarities of the semiconductor chips on the second transfer plate are all aligned in the same direction, and the alignment is automatically performed for each row at the same time. In addition to improving work efficiency, since the polarities are aligned in the same direction in the next step, for example, when semiconductor chips are fed to a lead frame, the feeding process can be easily automated. In other words, if a large number of devices are fabricated in a semiconductor wafer, divided into individual semiconductor chips on an adhesive tape, and only the defective chips are removed after testing the electrical characteristics of the semiconductor chips, there will be no defective chips on the adhesive tape. There are traces of missing chips, so when multiple semiconductor chips are placed on a lead frame, no semiconductor chips will be placed on the lead frame in the area where the defective chip was removed, and nothing will happen. The semiconductor chip supply process cannot be automated unless some replenishment process is added. However, in the present invention, since the non-defective semiconductor chips are aligned on the transfer plate without falling out, it is possible to easily automatically supply them in rows on the lead frame.
さらに特性不良の半導体チツプが第1の転写板
から第2の転写板へ移動させる工程で自動的に除
去することができ最終製品の信頼性の向上に寄与
することができる。 Furthermore, semiconductor chips with poor characteristics can be automatically removed in the process of transferring from the first transfer plate to the second transfer plate, contributing to improved reliability of the final product.
第1図は本発明の半導体チツプの整列方法を実
施するために使用する装置の一例を示す構成図、
第2図Aは上記装置の第1の転写板の構成を示す
一部切欠断面図、同図Bは上記第1の転写板と第
2転写板を反転させて重ね合せた状態の一部切欠
断面図、第3図は従来の整列方法を説明するため
の図である。
10……第1の転写板、10a……凹所、11
……第2の転写板、11a……凹所、13……半
導体チツプ、15……測定用移動ヘツド、15…
…測定針、18……制御装置、19……吸着ノズ
ル台、19a……吸着ノズル。
FIG. 1 is a configuration diagram showing an example of an apparatus used to carry out the semiconductor chip alignment method of the present invention;
FIG. 2A is a partially cutaway cross-sectional view showing the configuration of the first transfer plate of the above device, and FIG. The cross-sectional view and FIG. 3 are diagrams for explaining a conventional alignment method. 10...First transfer plate, 10a...Recess, 11
... second transfer plate, 11a ... recess, 13 ... semiconductor chip, 15 ... moving head for measurement, 15 ...
... Measuring needle, 18 ... Control device, 19 ... Suction nozzle stand, 19a ... Suction nozzle.
Claims (1)
の転写板上に個々に分離された半導体チツプが供
給される工程と、前記第1の転写板に供給された
前記半導体チツプの特性および極性を1列毎に測
定し、その結果を記憶しかつ特定方向の極性およ
び特性不良の半導体チツプを判別する工程と、こ
の工程で判別された特定方向の極性および特性不
良の半導体チツプのみを1列毎に第1の転写板か
ら同時に吸着し搬送工程上で前記特性不良の半導
体チツプのみを除去する工程と、前記吸着された
良品かつ特定方向の極性の半導体チツプを第2の
転写板の対応凹所内に1列毎に移す工程と、前記
第1の転写板に残つた良品かつ前記特定極性に対
して反対極性になる半導体チツプを当該第1の転
写板とともに第2の転写板上に反転させて重ね合
せ残りの半導体チツプを第2の転写板の空所部分
に移し第2の転写板上に同一極性かつ良品の半導
体チツプを整列させる工程とを有することを特徴
とする半導体チツプの整列方法。1. A first having a plurality of recesses arranged vertically and horizontally.
A process of supplying individually separated semiconductor chips onto a first transfer plate, measuring the characteristics and polarity of the semiconductor chips supplied to the first transfer plate for each row, and storing the results. A process of identifying semiconductor chips with polarity in a specific direction and defective characteristics, and a process in which only the semiconductor chips with polarity in a specific direction and defective characteristics determined in this process are simultaneously picked up from the first transfer plate one row at a time during the conveyance process. a step of removing only the semiconductor chips with poor characteristics; a step of transferring the adsorbed semiconductor chips of good quality and polarity in a specific direction one by one into corresponding recesses of the second transfer plate; The semiconductor chips remaining on the transfer plate that are good and have a polarity opposite to the specific polarity are inverted and stacked together with the first transfer plate on a second transfer plate, and the remaining semiconductor chips are transferred to the second transfer plate. 1. A method for arranging semiconductor chips, comprising the step of transferring semiconductor chips of the same polarity and good quality to a vacant space and arranging them on a second transfer plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12156384A JPS611036A (en) | 1984-06-13 | 1984-06-13 | Aligning method of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12156384A JPS611036A (en) | 1984-06-13 | 1984-06-13 | Aligning method of semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS611036A JPS611036A (en) | 1986-01-07 |
| JPH02854B2 true JPH02854B2 (en) | 1990-01-09 |
Family
ID=14814328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12156384A Granted JPS611036A (en) | 1984-06-13 | 1984-06-13 | Aligning method of semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS611036A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02131118U (en) * | 1989-03-31 | 1990-10-31 | ||
| KR102630948B1 (en) * | 2020-12-29 | 2024-01-30 | 세메스 주식회사 | Semiconductor package transfer method, semiconductor package transfer module and semiconductor package sawing and sorting apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51148375A (en) * | 1975-06-14 | 1976-12-20 | Fujitsu Ltd | Mesuring method of specific characteristics of semicondutor element |
| JPS5439576A (en) * | 1977-09-02 | 1979-03-27 | Nec Corp | Inspection method for semiconductor device |
-
1984
- 1984-06-13 JP JP12156384A patent/JPS611036A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS611036A (en) | 1986-01-07 |
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