JPH02886B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal amplification circuit with a large amplitude output that can be used in a deflection output circuit of a flat display device using an electron beam.

Conventional Structures and Problems There is a display device proposed in Japanese Patent Application Laid-open No. 135590/1983 as an example of achieving a flat display device using electron beams. Furthermore, a new proposal regarding the horizontal deflection direction of the present display device is described in Japanese Patent Application No. 58-26531 (Japanese Unexamined Patent Publication No. 59-151734) filed by the same applicant.

This flat display device generates an electron beam for each section when the screen is divided into a plurality of sections in the horizontal and vertical directions. It deflects and displays a plurality of lines to display a television image as a whole.

First, a basic configuration example of the image display element used here will be explained with reference to FIG.

This display element is arranged in order from the back to the front.
Back electrode 101, line cathode 10 as a beam source
2. Vertical focusing electrodes 103, 103', vertical deflection electrode 104, beam flow control electrode 105, horizontal focusing electrode 106, horizontal deflection electrode 107, beam accelerating electrode 108 and screen plate 109 are arranged. It is housed within the evacuated interior of a flat glass bulb (not shown).

A line cathode 102 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of line cathodes 102 (here, 102
Only four pieces, 1 to 102, are shown. ) is provided. In this embodiment, it is assumed that 15 pieces are provided. Let them be 102 i to 102 yo. These wire cathodes 102 are constructed by coating the surface of a tungsten wire with a diameter of 10 to 20 μΦ with an oxide cathode material for thermionic emission. These line cathodes 102a to 102y are heated so as to generate a thermionic beam when a current is passed through them, and as described later, the line cathodes 102a
The electron beams are controlled to be emitted sequentially from A to A for a fixed period of time. The back electrode 101 is a line cathode 10 that is controlled to emit an electron beam for a certain period of time.
This functions to suppress the generation of electron beams from other line cathodes 102 other than 2, and to push out the generated electron beams only in the forward direction. This back electrode 101 may be formed by a coating of conductive material applied to the inner surface of the rear wall of the glass bulb. Moreover, a planar electron beam emitting electrode may be used instead of the back electrode 101 and the line cathode 102.

The vertical focusing electrode 103 is connected to the line cathodes 102a-102.
It is a conductive plate 111 having horizontally long slits 110 facing each of the wire cathodes 10 and 10.
The electron beam emitted from 2 is passed through the slit 11.
0 through and vertically focused. An electron beam for one horizontal line (360 pixels) is extracted at the same time. In the figure, only one section in the horizontal direction is shown. The slit 110 may be provided with crosspieces at appropriate intervals along the way, or may be substantially configured as a slit by a row of through holes arranged horizontally at small intervals (nearly touching). may have been done. The vertical focusing electrode 103' is also similar.

A plurality of vertical deflection electrodes 104 are arranged horizontally in the middle of each of the slits 110, and are each composed of conductors 113 and 113' provided on the upper and lower surfaces of an insulating substrate 112. has been done. Then, a vertical deflection voltage is applied between the opposing conductors 113 and 113' to deflect the electron beam in the vertical direction. In this embodiment, the electron beam from one line cathode 102 is vertically deflected to a position corresponding to 16 lines by a pair of conductors 113, 113'. Then, 15 line cathodes 102 are formed by 16 vertical deflection electrodes 104.
15 pairs of conductors are constructed, corresponding to each of the
In the end, the electron beam is deflected so as to draw 240 horizontal lines on the screen 109.

Next, the control electrodes 105 are composed of conductive plates 115 each having a vertically long slit 114, and a plurality of control electrodes 115 are arranged in parallel in the horizontal direction at predetermined intervals. In this embodiment, 180 control electrode conductive plates 115a to 115n are provided. (Only 9 lines are shown in the figure). The control electrodes 105 each direct the electron beam in two directions in the horizontal direction.
Each picture element is divided and taken out, and the amount of passage thereof is controlled in accordance with the video signal for displaying each picture element. Therefore, if 180 conductive plates 115a to 115n for control electrodes 105 are provided, 360 picture elements can be displayed per horizontal line. In addition, in order to display images in color, each picture element is R, G, B
Display is performed using phosphors of three colors, and R, G, and B video signals for two picture elements are sequentially applied to each control electrode 105. In addition, 180 control electrodes 105
180 sets of video signals for one line (two picture elements per set) are simultaneously applied to each of the conductive plates 15a to 15n, and the video for one line is displayed at one time.

The horizontal focusing electrode 106 is a conductive plate 117 having a plurality of vertically long slits 116 (180 slits) facing the slits 114 of the control electrode 105.
The electron beam for each pixel divided horizontally is focused horizontally into a narrow electron beam.

The horizontal deflection electrode 107 is composed of a plurality of conductive plates 118, 118' arranged vertically on both sides of the slit 116,
Six levels of horizontal deflection voltages are applied to the respective electrodes 118 and 118' to deflect the electron beams of each picture element in the horizontal direction, and the screen 109
Above, the two sets of R, G, and B phosphors are sequentially irradiated to emit light. In this embodiment, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode 108 is composed of a plurality of conductive plates 119 provided horizontally at the same position as the vertical deflection electrode 104, and accelerates the electron beam so that it collides with the screen 109 with sufficient energy.

The screen 109 has a phosphor 120 that emits light when irradiated with an electron beam applied to the back surface of a glass plate 121, and a metal back layer (not shown).
is added and configured. The phosphor 120 is attached to one slit 114 of the control electrode 105.
That is, two pairs of three-color phosphors, R, G, and B, are provided for each electron beam divided in the horizontal direction, and are applied in stripes in the vertical direction. The broken lines drawn on the screen 109 in FIG.
The dashed dotted lines indicate horizontal divisions displayed corresponding to each of the plurality of control electrodes 5. As shown in the enlarged view in Fig. 2, one section partitioned by these two pixels has R, G, and R pixels for two pixels in the horizontal direction.
There is a B phosphor 120, which has a width of 16 lines in the vertical direction. The size of one section is, for example, 1 mm in the horizontal direction and 10 mm in the vertical direction.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

In addition, in this embodiment, only one pair of R, G, and B phosphors 120 for two picture elements are provided for one control electrode 105, that is, for one electron beam. Alternatively, three or more picture elements may be provided. In that case, R, G, and B video signals for one picture element or three or more picture elements are sequentially applied to the control electrode 105, and the horizontal deflection is synchronously applied to the control electrode 105. It will be done.

Next, the basic configuration of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, the electron beam is applied to the screen 10.
A driving portion for emitting raster light by irradiating the light beam 9 will be explained.

The electrode circuit 122 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode _of the display element.
3,103' are V ₃ , V ₃ , horizontal focusing electrode 106 is V ₆ , accelerating electrode 108 is V ₈ , screen 10
9, a DC voltage of V ₉ is applied.

Next, a composite video signal of a television signal is applied to the input terminal 123, and a synchronization separation circuit 124 separates and extracts a vertical synchronization signal V and a horizontal synchronization signal H.

The vertical deflection drive circuit 140 includes a vertical deflection counter 125 and a memory 12 for storing vertical deflection signals.
7. Digital to analog converter 139 (hereinafter referred to as D-
(referred to as A converter). As input pulses to the vertical deflection drive circuit 140, a vertical synchronizing signal V and a horizontal synchronizing signal H shown in FIG. 4 are used.
The vertical deflection counter 25 (8 bits) is reset by the vertical synchronizing signal V and then the horizontal synchronizing signal H.
count. This vertical deflection counter 12
5 counts the effective scanning period (in this case, a period of 240H) excluding the vertical retrace period of the vertical period, and this count output is supplied to the address of the memory 127. Vertical deflection signal data corresponding to each address (here, 8
bit) is output, and the D-A converter 139 outputs the fourth
It is converted into vertical deflection signals of v and v shown in the figure. This circuit has memory addresses that store vertical deflection signals corresponding to each line for 240H, and by storing regular data in the memory every 16H, it is possible to obtain 16 levels of vertical deflection signals. can.

On the other hand, the line cathode drive circuit 126 uses the vertical synchronization signal V and the output of the vertical deflection counter 25 to create line cathode drive pulses I to Y. FIG. 5a shows the relationship between the vertical synchronizing signal V, the horizontal synchronizing signal H, and the lower five bits of the vertical deflection counter 125. Fifth
FIG. b shows a method of creating line cathode driving pulses 1' to 16' every 16H using these signals. In Figure 5, LSB indicates the lowest bit, and (LSB+1) is
It means the bit one higher than the LSB.

The first line cathode drive pulse I' is the vertical synchronizing signal V
and the output of the vertical deflection counter 125 (LSB+4)
The line cathode drive pulses LO' to YO' can be created using an R-S flip-flop, etc., and the line cathode drive pulses LO' to YO' are created by inverting the output of the vertical deflection counter 25 (LSB+3) by using a shift register. It can be obtained by using the clock as a clock and transferring it. These drive pulses I' to Y' are inverted and converted into line cathode drive pulses I' to Y, which have a low potential only during each pulse period and a high potential of about 20 volts during other periods, and each line cathode 102A to 10
Added to 2yo.

Each of the line cathodes 102a to 102y is heated by a current flowing through it during the high potential period of the driving pulses y to y, and the heated state is maintained so that electrons can be emitted during the low potential period of the driving pulses y to yo. Ru. As a result, low-potential driving pulses I to Y were applied to each of the 15 line cathodes 102I to 102Y.
Electrons are emitted only during the 16H period. During the period when a high potential is applied, the potential at the line cathode 102 is lower than the potential at the position of the line cathode 102 determined by the bias voltage applied to the back electrode 101 and the vertical focusing electrode 103. Since the applied high potential is positive, the line cathode 102
No electrons are emitted from I~102Yo. Thus, in the line cathode 102, electrons are sequentially emitted from the upper line cathode 102a toward the lower line cathode 102y every 16H period during the effective vertical scanning period. The emitted electrons are pushed forward by the back electrode 101, pass through the opposing slits 110 of the vertical focusing electrode 103, and are vertically focused to form a flat electron beam.

Next, the relationship between the line cathode drive pulses y to y and the vertical deflection signals v and v will be explained using FIG. 6. The vertical deflection signals v and v' change by 1H in 16 steps during the 16H period of each line cathode pulse. The vertical deflection signals V and V' both have a center voltage of _V4 , and are configured to change in opposite directions such that v increases sequentially and v' decreases sequentially. These vertical deflection signals v and v' are applied to vertical deflection electrodes 113 and 113', respectively.
As a result, the electron beams generated from each of the line cathodes 102a to 202y are vertically deflected in 16 steps, and as mentioned earlier, the electron beams scan 16 lines of raster lines from top to bottom on the screen 109. It is deflected to draw one line at a time.

As a result of the above, electron beams are emitted from the top of the 15 line cathodes 102A to 102Y for a period of 16 hours, and each electron beam is sequentially emitted for one line from top to bottom within 15 sections in the vertical direction. As a result, the electron beam is vertically deflected one line at a time on the screen 109 from the 1st line at the top to the 240th line at the bottom.
A raster of 240 lines is drawn.

The electron beam thus vertically deflected is horizontally divided into 180 sections by the control electrode 105 and the horizontal focusing electrode 106 and extracted. 1st
The figure shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 105, and horizontally focused by a horizontal focusing electrode 106 into a single narrow electron beam, which is then controlled by horizontal deflection means described below. 2 on the screen 109 and deflected horizontally in 6 steps.
The R, G, and B phosphors 120 corresponding to picture elements are sequentially irradiated. FIG. 2 shows the vertical and horizontal divisions. 115a to 11 of the control electrodes 105, respectively.
The phosphors corresponding to 5n are R, G, and B for two picture elements, but for convenience of explanation, one picture element is designated as R ₁ , G ₁ , and B ₁ and the other picture element is designated as R ₂ , G ₁ , and B ₂ .

Next, the horizontal deflection drive circuit 141 includes a horizontal deflection counter 128 (11 bits), a memory 129 storing horizontal deflection signals, and a D-A converter 13.
It consists of 8. Horizontal deflection drive circuit 14
The input pulse No. 1 is synchronized with the vertical synchronizing signal V and the horizontal synchronizing signal H, as shown in FIG.
A pulse 6H with a repetition frequency of 6 times is used.

The horizontal deflection counter 128 is reset by the vertical synchronizing signal V and counts horizontal six times pulses 6H. This horizontal deflection counter 128 is 1H
260H×6/H=1440 times during 1V, and this count output is supplied to the address of the memory 129. Horizontal deflection signal data (8 bits here) corresponding to the address is output from the memory 129 and converted by the DA converter 138 into horizontal deflection signals such as h and h' shown in FIG. This circuit has memory addresses for storing horizontal deflection signals corresponding to each of 6 x 240 lines, and by storing 6 pieces of regular data for each line in the memory, 6 step waves are generated in 1H period. horizontal deflection signals can be obtained.

This horizontal deflection signal is a pair of horizontal deflection signals h and h' that change in 6 steps as shown in FIG. 7, both have a center voltage of V ₇ , and h gradually decreases.
h' increases in sequence and changes in opposite directions. These horizontal deflection signals h and h' are applied to electrodes 118 and 118' of horizontal deflection electrode 107, respectively. As a result, each horizontally segmented electron beam hits the screen 109 during each horizontal period.
R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ phosphors in sequence with H/6
It is horizontally deflected so that it is irradiated for each period. Thus, in each line raster, the horizontal direction
For each of the 180 sections, the electron beam is R ₁ , G ₁ , B ₁ ,
Each phosphor 120 of R ₂ , G ₂ , and B ₂ is sequentially irradiated with light.

Therefore, an electron beam is applied to each horizontal section of each line.
A color television image can be displayed on the screen 109 by modulating the video signals R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ .

Next, the modulation control portion of the electron beam will be explained.

First, the composite video signal applied to the television signal input terminal 123 is applied to the color demodulation circuit 130, where the P-Y and B-Y color difference signals are demodulated, and the G-Y color difference signals are matrix-synthesized. and are lazily combined with the volatility signal Y to produce R, G,
B primary color signals (hereinafter referred to as R, G, and B video signals) are output. These R, G, and B video signals are processed by 180 sample and hold circuit sets 131a to 131a.
131n. Each sample and hold circuit set 131a to 131n is for _R1 , _G1 ,
It has six sample and hold circuits for _B1 , _R2 , _G2 , and _B2 . These sample and hold outputs are stored in memory sets 132a to 132 for holding, respectively.
added to n.

On the other hand, the reference clock oscillator 133 is constituted by a PLL (phase locked loop) circuit, etc., and in this embodiment generates a reference clock 6f _sc that is six times the color subcarrier f _sc and a reference clock 2f _sc that is twice the color subcarrier f sc. . The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H.
The reference clock 2f _sc is the deflection pulse generation circuit 142
is added to the signal 6H, which is six times the horizontal synchronization signal H, and a signal switching pulse r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , every H/6.
b We are getting ₂ pulses. On the other hand, the reference clock 6f _sc is added to the sampling pulse generation circuit 134,
Here, the shift register sequentially generates 1080 sampling pulses R _a1 to _{R o2} during the effective horizontal scanning period (approximately 50 μsec) out of the horizontal period (63.5 μsec) by delaying the clock by one cycle. ,
After that, one transfer pulse t is generated. These sampling pulses R _a1 to _{R o2} correspond to each picture element when one line of the image to be displayed is divided into 360 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronizing signal H. controlled as follows.

These 1080 sampling pulses R _a1 to B _o2 are each connected to 180 sample and hold circuit sets 131.
6 circuits are added to each sample and hold circuit set 131a to 131n, so that when one line is divided into 180 circuits, 2 circuits are added to each sample and hold circuit set 131a to 11n.
Each picture element's R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ video signals are individually sampled and held. The sample held 180 pairs of R ₁ , G ₁ , B ₁ ,
The video signals of R ₂ , G ₂ , and B ₂ are transferred to 180 sets of memories 132a to 13 after completing the sample hold for one line.
2n by a transfer pulse t and held here for the next horizontal period. The held signals R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ are applied to switching circuits 135a to 135n. Each of the switching circuits 135a to 135n
It is composed of a tri-state or analog gate having individual input terminals for R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ and a common output terminal for sequentially switching and outputting them.

The output of each switching circuit 135a to 135n is 180 sets of pulse submodulation (PWM) circuits 137a.
~137n, where the reference pulse signal is pulse width modulated according to the magnitude of the sampled and held R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ video signal and is output. . The repetition period of the reference pulse signal is the above signal switching pulse r ₁ , g ₁ , b ₁ , r ₂ , g ₂ ,
It is desirable that the pulse width be sufficiently smaller than the pulse width of b ₂ , for example, a pulse width of about 1:10 to 1:100 is used.

The outputs of the pulse sub-modulation circuits 137a to 137n are used as control signals for modulating the electron beam to the 180 conductive plates 11 of the control electrode 105 of the display element.
5a to 115n, respectively. The switching circuits 135a to 135n are simultaneously controlled by switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , and b ₂ applied from the switching pulse generating circuit 136. The switching pulse generation circuit 136 is controlled by the signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ from the deflection pulse generation circuit 142 described above, and each horizontal period is divided into 6 Divided into H/6 switching circuits 135a to 135n
The video signals of R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ are time-divided and output sequentially, and the pulse sub-modulation circuit 1
Switching signal to be supplied to 37a-137n
Generate r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ .

What should be noted here is that switching circuit 1
R ₁ , G ₁ , B ₁ , R ₂ in 35a to 135n,
G ₂ , B ₂ video signal supply switching and electron beams R ₁ , G ₁ , B ₁ , by the horizontal deflection drive circuit 141
The irradiation switching horizontal deflection of R ₂ , G ₂ , and B ₂ to the phosphors is synchronously controlled so that they completely match both in timing and order.
As a result, when the electron beam is irradiating the R ₁ phosphor, the irradiation amount of the electron beam is controlled by the _{R 1} video signal, and _the irradiation amount of _the electron beam is controlled by the R ₁ video signal _.
B ₂ is controlled in the same way, and R ₁ of each picture element,
The light emission of each phosphor G ₁ , B ₁ , R ₂ , G ₂ , B ₂ is controlled by the video signal of R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ of that picture element. Therefore, each picture element is displayed by emitting light according to the input video signal. Such control is performed simultaneously for 180 sets of one line (2 picture elements each) to display an image of 360 picture elements for one line, and then sequentially for 240 minutes of lines starting from the upper line to display the image on the screen 109. One image will be displayed.

The above operations are repeated for each field of the input television signal, and as a result,
Screen 1 as in a normal television receiver.
The television image on the screen is displayed on 09.

As described above, television images are displayed on this display device.
If the image display element is driven using v' and horizontal deflection signals h and h', an image can ideally be displayed as shown in Figure 2, but in reality, the image display element is deflected in the vertical direction. In this case, the horizontal deflection sensitivity decreases near the vertical division boundary,
As shown in FIG. 8, the irradiation position of the electron beam becomes barrel-shaped.

This occurs because the speed of the electron beam passing through the horizontal deflection electrode 7 is accelerated when the electron beam is deflected in the vertical direction by the acceleration electrode 8.

Therefore, the amplitude of the horizontal deflection signal is changed according to the amount of vertical deflection of the electron beam to make the horizontal deflection uniform. This will be explained with reference to drawings showing essential parts of the circuit. In the apparatus of this embodiment, the amplitudes of the horizontal deflection signals h and h' applied to the electrodes 118 and 118' of the horizontal deflection electrode 7 are changed as shown in FIG. This is configured to dynamically change the amount of vertical deflection of the electron beam.

That is, as shown in FIG. 10, the horizontal deflection signals h and h' applied to the horizontal deflection electrodes 118 and 118' are made to have a larger amplitude in each vertical section where the amount of vertical deflection is larger. It's changing.

A specific example of a circuit for creating such horizontal deflection signals h and h' is shown in FIG. Here, 129 is the first
A memory 144A to 144Y stores the voltage values of each step of the horizontal deflection signals h and h' as digital signals as shown in FIG. 138 is a D/A that converts the digital signal read from the memory 129 into an analog voltage as shown in FIG.
It is a converter. Signal switching pulses r ₁ , g ₁ , b ₁ , r 2 , g 2 , b 2 from the deflection pulse generation circuit 142 are commonly applied to each switching circuit 144a to 144y, and signal switching pulses r 1 , g 1 , b 1 , r ₂ , g ₂ , b ₂ from the line cathode drive circuit 126 are also applied to each switching circuit 144a to 144y. By individually applying line cathode driving pulses I to 102Y and selectively operating the corresponding switching circuits 144I to 144Y during the period when the electron beam is emitted from each of the line cathodes 102I to 102Y, memory is generated. 129 predetermined X address 1H
Specify sequentially every H/6. On the other hand, memory
Y address of 129 is vertical deflection counter 125
The count outputs A ₀ to _{A 7} of the horizontal synchronizing signal H from are added and sequentially designated every 1H in a 16H cycle. In this way, the memory 129 can be sequentially addressed every H/6 by specifying the X address and the Y address, and the digital signals of each stage of the horizontal deflection signals h and h' can be read out from each address. Therefore, by D/A converting this read digital signal by the D/A converter 138, the horizontal deflection electrode 11 as shown in FIG.
Horizontal deflection signals h, h' for 8,118' can be created. Of course, the memory 129 stores a horizontal deflection signal h, which enables irradiation to an accurate predetermined position as shown in FIG. 2 at each stage while observing the position of the beam spot on the screen 109 in advance.
It is necessary to write the digital signal h′.

If it is possible to use horizontal deflection signals h, h' with almost the same waveforms in any of the vertical divisions A to Y, a memory with a storage capacity of one vertical division is used as the memory 129, and the switching circuit 144a to 144y are omitted and the signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ are directly stored in the memory 129.
In addition to the X address terminal of

By applying the horizontal deflection signals h, h' having the waveforms as shown in FIG. 10 to the horizontal deflection electrodes 118, 118' in this way, it is possible to substantially increase the horizontal deflection amount when the vertical deflection amount becomes large. The electron beam is always directed to screen 1 regardless of the amount of vertical deflection.
It is possible to irradiate a predetermined position on the surface 09 (phosphor surface) as shown in FIG. Therefore, it is possible to display an image with good color reproducibility over the entire surface of the screen 109, and it is possible to eliminate the problem of deterioration in color reproducibility, especially at the boundary portions of vertical sections.

In the specific example described above, the horizontal deflection of the above section is composed of 6 stages and the vertical deflection is composed of 16 stages, but the signal waveform of the horizontal deflection is not a uniform 6-stage wave, but a 14-stage waveform. As shown in the figure, in order to correct the difference in horizontal deflection sensitivity depending on the vertical deflection position, the amplitude of the horizontal deflection signal is increased where the deflection is large in the vertical direction. Figure 11a
Shown below.

Furthermore, in order to actually improve the focus characteristics on the screen, a parabolic signal as shown in FIG. 11b is superimposed on the horizontal deflection signal in FIG. 11a, and the final result is shown in FIG. 11c. The horizontal deflection electrode is driven with the waveform shown.

Note that here, FIG. 11 shows only the waveform corresponding to the horizontal deflection signal h shown in FIG. 14. In FIG. 11, H indicates the television horizontal period. When this deflection waveform was small, it was possible to drive the deflection electrode with a driver stage including a single-stage amplifier circuit and a push-pull output circuit as shown in FIG.

FIG. 12 shows the specific circuit. In FIG. 12, 1 is an input terminal for a horizontal balanced signal, and a waveform corresponding to C in FIG. 11 is input. This signal is amplified by a driver stage formed by transistor 2 and resistors 3 and 4, and then amplified by a push-pull output circuit formed by transistors 5, 6, 7 and resistors 8 and 9.
The signal is output from the output terminal 10 to the horizontal deflection electrode. The diode 11 and the variable resistor 12 are used to determine the bias current of the push-pull output circuit, 13 is the input terminal of the positive side power supply (V _cc ) of this circuit, and 14 is the input terminal of the negative side power supply (V _ee ). be.

By the way, in order to increase the volatility or enlarge the display screen, Japanese Patent Application No. 58-26531 (Japanese Unexamined Patent Publication No. 59-1983)
151734), when the voltage applied to the accelerating electrode is increased, the amplitude of the horizontal deflection waveform is also required to be very large. As an example, when the accelerating voltage is 10KV on a 10-inch screen, the amplitudes of the step wave and parabolic wave (a and b in Figure 11) are respectively
Some even reach 140V _PP and 240V _PP . This adds up to 380V _PP . Furthermore, the step wave requires fast rise and fall times. It has been difficult to construct a circuit as shown in FIG. 12 that satisfies these requirements from the viewpoint of elements. In other words, it is generally difficult to obtain high-voltage transistors with good frequency characteristics, and in order to achieve high-amplitude, high-speed response, there is a limit to the power dissipation of the transistors used, so high-speed, large-amplitude amplification is not possible. There was a problem.

Purpose of the Invention The present invention eliminates these conventional drawbacks, and provides an amplification system that does not require high-voltage transistors with particularly good frequency characteristics and can obtain large-amplitude output signals using transistors with low power dissipation. The purpose is to provide circuits.

Configuration of the Invention The signal amplifying circuit of the present invention is effective in amplifying a signal in which a signal including a high frequency component and a signal having a low frequency component are superimposed.

In other words, instead of simultaneously amplifying a signal in which a signal containing a high frequency component and a signal consisting of a low frequency component are superimposed, as in the past, a signal containing a high frequency component and a signal consisting of a low frequency component are first amplified, respectively. Take out the signal. Each signal has an input terminal and an amplifier circuit, and the low-frequency signal amplifier circuit applies the stabilized power supply voltage as is, and its load output is used as the positive power supply for the signal amplifier circuit containing high-frequency components.

Further, a voltage level-shifted from the load output of the low frequency signal amplification circuit is used as a power source for a signal amplification circuit containing a high frequency component. The level shift amount is shifted by the power supply voltage necessary for signal amplification of high frequency components.

With this configuration, a signal containing a high frequency component and a low frequency signal can be obtained from the load output of a circuit that amplifies a signal containing a high frequency component, and at the same time, a signal containing a high frequency component can be obtained. The required breakdown voltage of elements (such as transistors) that amplify the signal can also be significantly reduced, allowing the use of commonly available elements with low breakdown voltage but good frequency characteristics. Also, since the voltage applied to the transistor can be lowered, transistors with lower power dissipation can be used.

Taking the above example, since the step wave (signal containing high frequency components) is 140V _PP , the withstand voltage of the element that amplifies it only needs to be 150V or more in the configuration of the present invention, and the allowable power dissipation of the transistor is also small. That's fine. On the other hand, in the conventional circuit configuration for amplifying the superimposed signal as shown in _FIG.
Parabolic wave 240V _PP is superimposed on the total
Since the voltage is 380V _PP , the element that amplifies it must have a withstand voltage of 400V or more. Moreover, in order to achieve the high-speed response characteristics of the staircase waveform, the load resistance must be made small, and as the bias current of the amplifier circuit increases, the power dissipation of the transistors used is also required to be large. It is extremely difficult to satisfy all of these requirements using existing transistors. However, according to the circuit configuration of the present invention, this can be easily realized as described above.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Figure 13 is its specific circuit diagram, and Figure 14
The figure is a waveform diagram for explaining the operation. In FIG. 13, the same parts as in FIG. 12 are given the same numbers. Also, the explanation of the operation is in the 11th section.
Let us describe the signal amplification shown in the figure.

15 is an input terminal for the parabolic signal (low frequency signal) shown in FIG. 11b, and 16 is an input terminal for the staircase wave (signal containing a high frequency component) shown in FIG. 11a. A signal (low frequency signal) inputted from the input terminal 15 is amplified by an amplifier circuit consisting of a transistor 17, a resistor 18, and a load resistor 19, and the collector output of the transistor 17 is supplied to a load resistor 22 through emitter followers 20 and 21. Further, the emitter output of the emitter follower 20 is level-shifted by a voltage drop determined by the resistor 23 and the current source 24, and is applied to the base of the transistor 26 through the emitter follower 25. The current source 27 is the emitter follower 2
This is a current source that determines the bias current of 1 and 25.

On the other hand, a staircase wave (a signal containing a high frequency component) inputted from the input terminal 16 is inputted to the base of a transistor 28, and is amplified by an amplifier circuit consisting of transistors 28, 26, a resistor 29, and a load resistor 22 connected in series. The collector output of the transistor 26 is a signal obtained by amplifying the signal input from the input terminal 15 as shown in FIG.
A waveform obtained by superimposing a signal obtained by amplifying the input signal is obtained. As mentioned above, the diode 11 and the variable resistor 12 determine the bias current of the push-pull output circuit, and since the resistance value of the variable resistor 12 can generally be made sufficiently smaller than the resistance value of the load resistor 22, the base input of the transistor 15 The amplitude of the base input of the transistor 6 becomes almost the same as that of the base input of the transistor 6. These signals are connected to transistors 5, 6, 7
The current is amplified by a push-pull output circuit including resistors 8 and 9, and is output from an output terminal 10.

Here, set the emitsuta of emitsuta follower 21 to point D,
Assuming that the emitter of the transistor 26 is a point E and the collector of the transistor 26 is a point F, from the above explanation, the signal waveforms at each point D, E, and F will be as shown in FIG. 4 d, e, and f, respectively. The collector voltage of the converter 17 that amplifies the signal input from the input terminal 15 is 2V _BE (V _BE is the voltage between the base and emitter of the transistor, approximately 0.7V) higher than point D, so the collector-emitter breakdown voltage of the transistor 17 is is approximately (V _cc −V _ee ), and a high withstand voltage is required. However, since the output waveform of transistor 17 has a low frequency component as shown in FIG. 14d, the transition frequency f _T of transistor 17 is
It is best to use a special transistor (with high voltage resistance).
_f ) is not required. Also, load resistance 1
9 can also use a high resistance value, so power consumption can be reduced. The signal input from the input terminal 16 is a staircase wave and contains high frequency components, but the transistors 26 and 28 that amplify this are
As shown in Figure 4, the withstand voltage may be low. In other words, the transistor 26 only needs to have a withstand voltage higher than the voltage (d-e) in FIG.
Regarding this, it is sufficient if the withstand voltage is higher than the peak voltage of e in FIG. 14. Since these voltages are very low compared to the voltage (V _cc −V _ee ), it is easy to obtain transistors with high f _T as the transistors 26 and 28. Moreover, since the power supply voltage is low, a transistor with low power dissipation can be used. Therefore, if amplification is performed using a circuit configuration like this specific circuit, the conventional 12th
The circuit shown in the figure first solves the difficulty of amplifying large-amplitude, high-speed signals from the element standpoint, and makes it possible to easily create a signal amplification circuit with large-amplitude output using ordinary, inexpensive transistors. .

Effects of the Invention As described above, according to the present invention, when amplifying a signal in which a signal containing high frequency components and a low frequency signal are superimposed to a large amplitude, firstly, it has a high breakdown voltage and good frequency characteristics. Second, the circuit does not require any special transistors, and secondly, the circuit can be constructed using transistors with small power dissipation, so that a large-amplitude signal amplification circuit can be easily realized at low cost using conventional general transistors.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view of an image display element used in an image display device, FIG. 2 is an enlarged view of a phosphor screen of the image display element, and FIG. Figures 4, 5, 6, and 7 are waveform diagrams of various parts to explain the operation of the drive circuit, and Figure 8 is a block diagram of the drive circuit devised by the same drive circuit. FIG. 9 is an enlarged view showing the displayed state; FIG. 9 is a block diagram of the main parts of an image display device devised prior to the present invention;
The figure is a waveform diagram to explain the operation of the device.
Figure 1 is a waveform diagram showing an example of a signal waveform that produces an effect by applying the signal amplification circuit of the present invention, and Figure 12 is a waveform diagram showing an example of a signal waveform that produces an effect by applying the signal amplification circuit of the present invention.
A circuit diagram showing an example of a conventional circuit for amplifying the signal in the figure,
FIG. 13 is a circuit diagram of a signal amplifying circuit according to an embodiment of the present invention, and FIG. 14 is a waveform diagram for explaining its operation. 5, 6, 7, 17, 26, 28...Transistor, 8, 9, 18, 23...Resistor, 19, 22...
...Load resistance, 10...Output terminal, 11...Diode, 12...Variable low resistance resistor, 13...Positive side power input terminal, 14...Minus side power input terminal,
15... Low frequency signal input terminal, 16... Signal input terminal containing high frequency components, 20, 21... Emitter follower, 24, 25, 27... Emitter follower.

Claims (1)

[Claims] 1. A first amplifier circuit that amplifies a signal having a low frequency component, a circuit that level shifts the output of the first amplifier circuit by a certain voltage, and a signal that includes a high frequency component using the output of the level shift circuit as a power source. a second amplifier circuit that amplifies the signal; the output of the first amplifier circuit is used as one power supply, and the output of the level shift circuit is used as the other power supply; the output of the second amplifier circuit is amplified, and a high frequency component is generated as an output. and a third amplifier circuit that outputs a signal obtained by superimposing a signal consisting of a low frequency component on a signal containing a low frequency component.