JPH029331B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mirror drive circuit suitable for driving a mirror operation mechanism using a toggle spring with a motor.

The mirror operating mechanism, in which a toggle spring is disposed, controls the raising and lowering of the mirror by an operating member that operates in both directions with the neutral point of the toggle spring as a boundary. Since the dead center is held by the tension of the toggle spring, no particular locking mechanism is required. Therefore, on the other hand, if an impact in a certain direction is applied to the camera while the mirror is in the down state, the mirror may be displaced to the up state due to the inertia of the mirror operating mechanism, which may interfere with the next shot. .

The present invention aims to eliminate the above-mentioned drawbacks and aims to provide an actuation device that uses a toggle spring to drive a mirror actuation mechanism using a motor. In the initial state of the release operation, at the same time as power is supplied to the circuit system, power is supplied intermittently to the motor to bring down the mirror operating mechanism, thereby returning the mirror to the down state and ensuring that the mirror operating mechanism is not operating normally. The present invention provides a mirror drive circuit in which the motor is not supplied with power for turning down the motor when it is in the up state when the motor is in the up state and is moved from the down state to the up state.

Embodiments of the present invention will be described in detail below based on the drawings.

First, in FIGS. 1 and 2, reference numeral 1 denotes a side wall of a mirror box, which forms an arcuate long groove 1a. 2
is a mirror, which is pivotally mounted on a shaft 3 inside the side wall 1, and has a support shaft 2b that projects from the long groove 1a to the outside of the side wall 1 (toward the front side of the paper) on the upholstered plate 2a. 4
is a first crank lever, which is pivotally connected to a shaft 5 on the side wall 1, and has a support shaft 4a implanted therein. Reference numeral 6 denotes a second crank lever, which is pivotally connected to a support shaft 4a implanted in the first crank lever 4 and a support shaft 2b implanted in a member integral with the mirror 2. 7 is a toggle spring,
It is hung between the shaft 5 and the support shaft 2b via the support shaft 4a. Reference numeral 8 denotes a mirror operation lever, which is pivotally mounted on a shaft 9 on the side wall 1, and has arms 8a and 8b for operating a support shaft 2b that is integrated with the mirror 2, and a reflection plate portion 8c, and has a pin 8d implanted therein. are doing. 10 and 1
1 (T ₁ ) is a light emitting element and a light receiving element (phototransistor) constituting a position detection circuit, which are supported on the side wall 1.

In addition, there is a yoke 1 at the bottom of the mirror box.
2, 13, permanent magnet 14, iron core 15, coil frame 1
6, a linear motor constituted by a coil 17 (Lm), a piece 18 supported by the coil frame 16 and fitted with the pin 8d of the mirror operation lever 8 is disposed.

Next, in FIG. 3, T ₁ is the phototransistor in FIGS. 1 and 2, BA ₁ to _{BA 3} are buffer amplifiers, FF ₁ and FF ₂ are flip-flops, and CO ₁ to _{CO 6}
is a counter, NAG ₁ ~ NAG ₇ is a NAND gate, I ₁
~ _I14 and _I18 are inverters, _ANG1 ~ _ANG4 are AND gates, _ORG1 , _COG2 are OR gates, _NAG10 ,
NAG ₁₁ is a NAND gate that constitutes flip-flop FF ₃ . NAG ₈ , I ₁₅ , I ₁₆ , C, and R are a NAND gate, an inverter, a capacitor, and a resistor that constitute a well-known oscillator OSC, and the oscillation frequency is set to, for example, ₀ = 32.768 KHz. _CO7 ,
CO ₈ , I ₁₇ , and NAG ₉ are a counter, an inverter, and a NAND gate that together constitute a pulse generation circuit, which generates intermittent output pulses with a width of 64 ms, for example, every 500 ms. _T2 to _T7 are transistors,
Lm is a coil in the linear motor shown in FIGS. 1 and 2, Lo is a coil of an electromagnetic device that controls the release release or opening drive of the shutter, and Lc is a coil of an electromagnetic device that controls the closing release or drive of the shutter.

Note that the circuit is powered, and the oscillator
When the OSC operates, the clock input terminals CK of counters CO ₁ to CO ₆ are connected to the output terminal Q ₂ of counter CO ₇ .
At the falling edge of the time width pulse formed by the NAND gate NAG ₆ and the counter CO ₆ inverter I ₆ , which will be described later, the counters CO ₁ to _{CO 6} and the flip-flop FF ₁ ,
This is what FF ₂ is cleared. Further, each combination circuit of a NAND gate, a counter, and an inverter constitutes a pulse generation circuit with a time width corresponding to each function.

Furthermore, inverters I ₁₃ , I ₁₈ , flip-flop
FF ₃ and NAND gate NAG ₇ constitute an inverting circuit, and AND gate ANG ₃ and flip-flop
It is assumed that FF ₂ constitutes a set circuit.

Next, the operation will be explained with reference to FIGS. 1, 2, 3, and 4.

First, the operation when the mirror operating mechanism is displaced as shown in FIG. 2 and the mirror 2 is in the up state due to some reason before photographing will be explained.

In this state, the camera release operation is performed,
Initially, a power switch (not shown) is closed,
When power is supplied to each part of the circuit, the phototransistor 11 (T ₁ ) receives light from the light emitting element 10 via the reflection plate part 8c, so that a large emitter-collector current flows (second output). As a result,
The flip-flop _FF3 receives a negative pulse through the inverter _I13 , and the output Q is inverted to the "H" level and the output is inverted to the "L" level (first state). Therefore, the output of ORG ₁ is "H"
Since the oscillator OSC starts operating, an output pulse of 64 ms width can be generated every 500 ms at the output of the NAND gate NAG ₉ , as described above. At this time, since the output of flip-flop FF ₂ is at the "H" level (non-set state), the output pulse of NAND gate NAG ₉ passes through the AND gate ANG ₄ constituting the gate circuit and passes through the OR gate.
Appears in the output of ORG ₂ . Therefore, the transistor
T ₅ and T ₂ are turned on, and a current in the direction indicated by the dotted line arrow can intermittently flow through the coil Lm (17). Therefore, the coil 16 around which the coil 17 (Lm) is wound is the second
In the figure, move above the iron core 15 to the upper right. As a result, the mirror operation lever 8 is connected to the pin 8d and the piece 18.
Due to the fitting relationship with the toggle spring 7, it is rotated to the left against the tension of the toggle spring 7. This left rotation of the mirror operation lever 8 causes the arm 8b to push the support shaft 2b, so that the mirror 2 moves down and the first crank lever 4 and the second crank lever 6 swing.

Then, the mirror 2 is lowered and the levers 4 and 6 are
During the swinging process, the toggle spring 7 acts as a force in the direction of raising the mirror 2 while the support shaft 2b is located on the right side with respect to the line connecting the shafts 5 and 3. , when the support shaft 2b moves beyond its neutral point to the left side, the mirror 2
acts as a force in the direction of bringing down the
The mirror operating mechanism is displaced to the state shown in FIG. 1, and is in a normal photographic preparation state.

In addition, during the above-mentioned mirror up state, even if the release operation progresses and the release pulse P is applied to the AND gate ANG ₃ , the flip-flop
Since the output of FF ₃ has been inverted to the "L" level, flip-flop FF ₂ is not set.

When the mirror operating mechanism returns to the mirror-down state shown in Fig. 1, the phototransistor _T1 no longer receives light, and thus the emitter-collector current decreases (first output), and the output of the inverter _I13 goes to the "H" level. Flip to .

Therefore, when the output pulse of the NAND gate NAG ₉ falls and the output of the inverter _I18 is inverted to the "H" level, the output of the NAND gate NAG ₇ is inverted to the "L" level, and as a result, the flip-flop FF ₃ is reset, the output Q is inverted to the "L" level, and the output is inverted to the "H" level (second state). Therefore, the operation of the oscillator OSC is temporarily stopped, the counters CO ₇ and CO ₈ are cleared via the inverter I ₁₄ , and the release pulse P is allowed to pass.

When the release operation proceeds in this state and the release pulse P is applied to the AND gate _ANG3 , the flip-flop _FF2 is set, the output Q is inverted to the "H" level, and the output is inverted to the "L" level ( set state). Therefore, the oscillator OSC starts operating again. Note that the above-mentioned output pulse is generated at the output of NAND gate NAG ₉ due to the operation of oscillator OSC, but since the output of flip-flop FF ₂ is inverted to "L" level, the output does not appear at OR gate ORG ₂ . .

Also, the output Q of flip-flop FF ₂ is “H”.
and gate by flipping to level
Since the output of ANG ₁ is inverted to "H" level, transistors T ₄ and T ₃ are turned on, and coil Lm (17)
A current flows in the direction indicated by the solid line arrow. Therefore, the coil frame 16 around which the coil 17 (Lm) is wound is
In the figure, it moves to the left on the iron core 15. Therefore, the mirror operation lever 8 is turned to the right against the tension of the toggle spring 7 due to the fitting relationship between the pin 8d and the piece 18. By turning the mirror operation lever 8 to the right, the arm 8a pushes the support shaft 2b, so that the mirror 2 is raised and the first crank lever 4 and the second crank lever 6 swing.

Then, the mirror 2 flips up and the lever 4,
6, the toggle spring 7 acts as a force in the direction of lowering the mirror 2 while the support shaft 2b is located on the left side with respect to the line connecting the shafts 5 and 3. However, when the support shaft 2b exceeds its neutral point and comes to be located on the right side, a force acts in the direction of raising the mirror 2, and therefore the mirror operating mechanism is displaced to the state shown in FIG.

Immediately after the support shaft 2b exceeds the neutral point, the reflection plate portion 8c of the mirror operation lever 8 connects the light emitting element 10 and the light receiving element 11 (phototransistor).
Therefore, _{the phototransistor T 1 receives} light from the light emitting element 10 .

As a result, the collector of phototransistor _T1
Since the emitter current increases, and gate
The output of _ANG2 is inverted to the "H" level, the flip-flop _FF1 is set upon receiving the positive input from the set input terminal S, and the output Q is inverted to the "H" level.

Therefore, the output of NAND gate NAG ₁ is inverted to "L" level, so counter CO ₁ reads the clock pulse and outputs Qc after a predetermined time (TD ₁ ).
is inverted to "H" level. As a result, the output of AND gate ANG ₁ becomes "L" through inverter I ₇ .
Since the level is reversed, the transistors T ₄ and T ₃ are also turned off again, and the power supply to the coil Lm (17) is stopped.

As described above, since the toggle spring 7 is already acting as a force to raise the mirror 2, the mirror operating mechanism is displaced to the state shown in FIG. Further, since the output of the NAND gate _NAG1 is inverted to the "H" level via the inverter _I1 , reading of the clock pulse is stopped at that point. and,
This predetermined time TD ₁ is set to correspond to the time from when the mirror operating mechanism exceeds the above-mentioned neutral point until reaching the up state, and the time until the bounce subsides after the up state.

When the output Qc of the counter CO ₁ is inverted to the "H" level, the output of the NAND gate NAG ₄ is inverted to the "L" level, so the transistor T ₆ is
Turns on and power is supplied to coil Lo. As a result, a shutter (opening blade) (not shown) is opened. On the other hand, the counter _CO4 reads the clock pulse, and after a predetermined time ( _T1 ), the output is inverted to the "H" level, and the output is inverted to the "H" level through the inverter _I4 .
Since the output of NAG ₄ is inverted to the "H" level, reading of the clock pulse is stopped at that point. At the same time, transistor _T6 is turned off and the coil
Stop power supply to Lo. This predetermined time _T1 is set to the time required to complete the shutter release or release drive.

Furthermore, when the output Qc of the counter CO ₁ is inverted to the "H" level, the output of _the NAND gate NAG ₂ is inverted to the "L" level.
reads the clock pulse and calculates the specified time (Ts)
Later, the output Qx is inverted to the "H" level, and the output of the NAND gate _NAG2 is inverted to the "H" level via the inverter _I2 , so reading of the clock pulse is stopped at that point. Note that the output terminal (Qx) of the counter CO ₂ is the exposure time (Ts).
It is selected according to the settings.

Furthermore, when the output Qx of the counter CO ₂ is inverted to the "H" level, the output of the NAND gate NAG ₅ is inverted to the "L" level, so that the transistor
_T7 is turned on and power is supplied to the coil Lc. As a result, a shutter (not shown) is closed. On the other hand, the counter _CO5 reads the clock pulse, and after a predetermined time ( _T2 ), the output Qa is inverted to the "H" level, and the output of _{the NAG 5 is} inverted to the "H" level via the inverter I5. , at that point it stops reading the clock pulses. At the same time, transistor _T7 is turned off to stop supplying power to coil Lc. This predetermined time T ₂
is set to the time required to complete the closing release or closing drive of the shutter.

Furthermore, when the output Qx of the counter CO ₂ is inverted to the "H" level, the output of _the NAND gate NAG ₃ is inverted to the "L" level.
reads the clock pulse and waits for a predetermined time (TD ₂ ).
Later, the output Qb is inverted to the "H" level, and the output of the NAG ₃ is inverted to the "H" level via the inverter _I3 , so reading of the clock pulse is stopped at that point. This predetermined time TD ₂ is
This is set to the time it takes for the shutter to completely close (the blades are fully closed).

Furthermore, by inverting the output Qb of the counter CO ₃ to the "H" level, the NAND gate NAG ₆
Since the output of _is inverted to "L _" level, the transistor
T ₂ and T ₅ are turned ON, and a current flows in the direction indicated by the dotted line arrow in the coil Lm (17). Therefore, the coil frame 16 moves to the right in FIG.
goes down to the state shown in FIG.

On the other hand, as the output of NAND gate NAG ₆ is inverted to "L" level, counter CO ₆ reads the clock pulse and outputs it after a predetermined time (T ₃ ).
Qd is inverted to "H" level, and inverter _I6
Since the output of the NAND gate NAG ₆ is inverted to the "H" level via , reading of the tick pulse is stopped at that point. transistor at the same time
T ₂ and T ₅ are turned off, and the power supply to the coil Lm (17) is stopped. This predetermined time T ₃ is set to the time from the up state (top dead center) of the mirror 3 until it exceeds the above-mentioned neutral point or reaches the down state (bottom dead center).

The operation process from the above normal state is as shown in FIG.

Note that the input connection point of inverter _I7 is the counter
Although it is shown as the output terminal Qc of CO ₁ , it may also be the output terminal Q of flip-flop FF ₁ . That is, if a state exceeding the neutral point is detected in the up-operation stroke of the mirror operating mechanism, the power supply to the coil Lm may be stopped.

In addition, the member that detects the position beyond the neutral point during the up process of the mirror operating mechanism may be the mirror itself, in addition to the mirror operating lever, and the detection means is preferably a non-contact type, but it is photoelectric. In addition to the type, a magneto-electric type etc. may be used.

As described above, in the mirror operating mechanism of the present invention, in an operating device in which a motor drives a mirror operating mechanism using a toggle spring, when the mirror is displaced to the top dead center before photographing, in the initial state of the release operation. , at the same time that power is supplied to the circuit system,
The mirror is returned to the bottom dead center by intermittent power supply to the motor that shuts down the mirror operating mechanism, and when the mirror operating mechanism operates normally and is displaced from the bottom dead center to the top dead center. Since power is not supplied to the motor to cause the motor to shut down, it does not interfere with shooting, and normal shooting is always performed, and the power consumption during the recovery operation is low. It's something that can be done.

[Brief explanation of drawings]

Figures 1 and 2 show the mirror operating mechanism down;
FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is an explanatory diagram of its operation. 2... Mirror, 4, 5... Crank lever, 7
...Toggle spring, 8...Mirror operation lever, 10
... Light emitting element, 11 ... Light receiving element, 16 ... Coil frame, 17 ... Coil. T ₁ ... Phototransistor, BA ₁ ~ BA ₃ ... Buffer amplifier, FF ₁ , FF ₂
...Flip-flop, NAG ₁ to NAG ₁₁ ...Nand gate, CO ₁ to CO ₈ ...Counter, I ₁ to _{I 18} ...
...Inverter, ANG ₁ to ANG ₄ ...Andot,
ORG ₁ , ORG ₂ ...OR gate, _T2 to _T5 ...transistor, Lm, Lo, Lc...coil.

Claims (1)

[Scope of Claims] 1. A mirror operating mechanism in which a toggle spring is disposed and has a behavior of operating in the direction of top dead center and in the direction of bottom dead center with the neutral point of the toggle spring as a boundary; a motor driven from top dead center; and a position detection circuit that generates a first output when the mirror actuation mechanism is located on the bottom dead center side and generates a second output when the mirror operation mechanism is located on the top dead center side. a pulse generation circuit that generates an intermittent pulse output when the position detection circuit is in a state of generating a second output; and a pulse generation circuit that generates an intermittent pulse output when the position detection circuit is in a state of generating a second output; and an inverting circuit which assumes a second state by the first output when the mirror operating mechanism is located at the bottom dead center side, and an inverting circuit which takes a second state by the first output when the mirror operating mechanism is located at the bottom dead center side, and a non-inverting circuit when the inverting circuit is in the first state at the beginning of power-on. When it is in the set state and in the second state, a release pulse signal is input,
A set circuit that takes a set state for raising the mirror operating mechanism toward top dead center and maintains the set state even after the reversing circuit is reversed from the second state to the first state; A mirror drive circuit comprising: a gate circuit that opens only when in a set state and allows the output of the pulse generating circuit to pass through to supply power to the motor to move the mirror operating mechanism down toward bottom dead center.