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JPH0312463B2 - - Google Patents
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JPH0312463B2 - - Google Patents

Info

Publication number
JPH0312463B2
JPH0312463B2 JP57086956A JP8695682A JPH0312463B2 JP H0312463 B2 JPH0312463 B2 JP H0312463B2 JP 57086956 A JP57086956 A JP 57086956A JP 8695682 A JP8695682 A JP 8695682A JP H0312463 B2 JPH0312463 B2 JP H0312463B2
Authority
JP
Japan
Prior art keywords
semiconductor
prober
semiconductor wafer
marking
inspection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57086956A
Other languages
Japanese (ja)
Other versions
JPS58218132A (en
Inventor
Masayasu Myake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
Original Assignee
NEC Home Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd filed Critical NEC Home Electronics Ltd
Priority to JP57086956A priority Critical patent/JPS58218132A/en
Publication of JPS58218132A publication Critical patent/JPS58218132A/en
Publication of JPH0312463B2 publication Critical patent/JPH0312463B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 この発明は半導体ウエーハに形成した複数の半
導体素子の特性を検査する工程の検査及び検査後
の処理方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection process for inspecting the characteristics of a plurality of semiconductor elements formed on a semiconductor wafer, and a post-inspection processing method.

一般に、トランジスタやIC等の半導体素子の
特性検査は多数の素子が一斉にパツチ処理形成さ
れた半導体ウエーハの状態で行われ、この時使用
される検査装置はプローバと称されている。この
プローバは1つの半導体素子の表面電極に当るプ
ローブニードルを定位置に配置し、このプローブ
ニードルの下方で半導体ウエーハを目合せして位
置決めしてから水平なX−Y方向及び垂直なZ方
向に間歇送りして、1個ずつの半導体素子をプロ
ーブニードルに当接させて順次に特性検査してい
くもので、半導体ウエーハの目合せを顕微鏡を使
つて手動で行つてから後の検査を全自動で行うセ
ミオートプローバや、半導体ウエーハの目合せも
例えばレーザ光を用いて自動的に行うフルオート
ウエーアプローバがあり、最近は能力向上や後工
程(半導体素子外観チエツク工程など)の省力化
などの優位性からフルオートウエーハプローバが
多く使用されつつある。
Generally, the characteristics of semiconductor elements such as transistors and ICs are inspected on a semiconductor wafer in which a large number of elements have been patch-formed all at once, and the inspection equipment used at this time is called a prober. This prober places a probe needle that corresponds to the surface electrode of one semiconductor element in a fixed position, aligns and positions the semiconductor wafer below the probe needle, and then moves it in the horizontal X-Y direction and the vertical Z direction. The characteristics of each semiconductor wafer are inspected one by one by intermittent feeding and contact with a probe needle.The semiconductor wafer is aligned manually using a microscope, and subsequent inspection is fully automated. There are semi-automatic wafer probers that automatically align semiconductor wafers, and fully automatic wafer probers that automatically align semiconductor wafers using, for example, laser light. Fully automatic wafer probers are increasingly being used due to their superiority.

フルオートウエーハプローバの検査の一例を第
1図で説明する。第1図において、1は半導体ウ
エーハ、2は検査前の半導体ウエーハ1を複数枚
収納するマガジン、3はマガジン2を定ピツチず
つ上昇動させるエレベータ機構で、マガジン2の
1ビツチの上昇毎に1枚の半導体ウエーハ1がベ
ルトコンベア等の搬送体4上に切出されて位置粗
調整ポジシヨンにある粗調整ステージ5上へ送出
される。6はステージ5の上方定位置に配置され
た位置粗調整機構で、例えばステージ5上の半導
体ウエーハ1に光スポツトを照射してその反射光
を読み取り、ステージ5を移動させて半導体ウエ
ーハ1の位置を粗調整する。7は搬送体、8は検
査ステージ、9はプローブニードルを固定配設す
るプローブカード、10は検査不良表示マーカ
で、前記ステージ5で粗調整された半導体ウエー
ハ1は搬送体7を介して検査ステージ8上に移送
され、ここで位置の微調整が行われてから検査ス
テージ8のX、Y、Z方向の間歇移動で1個ずつ
の半導体素子がプローブカード9から下に突出す
るプローブニードル11に当り、特性検査が順次
に行われる。この検査と併行して、検査結果が不
良と出た半導体素子に対してはその検査後にマー
キング機構のマーカ10が下降して不良半導体素
子表面に不良認識マークがマーキングされる。特
性検査の完了した半導体ウエーハ1は検査ステー
ジ8から搬送体12上に取出されて別のマガジン
2′へと収納されてから、外観検査等の後工程へ
送られていく。
An example of inspection using a fully automatic wafer prober will be explained with reference to FIG. In FIG. 1, 1 is a semiconductor wafer, 2 is a magazine that stores a plurality of semiconductor wafers 1 before inspection, and 3 is an elevator mechanism that moves the magazine 2 up by a fixed pitch. A piece of semiconductor wafer 1 is cut out onto a conveyor 4 such as a belt conveyor and sent onto a coarse adjustment stage 5 at a rough position adjustment position. Reference numeral 6 denotes a coarse position adjustment mechanism disposed at a fixed position above the stage 5. For example, the mechanism 6 irradiates a light spot onto the semiconductor wafer 1 on the stage 5, reads the reflected light, moves the stage 5, and adjusts the position of the semiconductor wafer 1. Make coarse adjustments. 7 is a carrier, 8 is an inspection stage, 9 is a probe card on which a probe needle is fixedly arranged, 10 is an inspection defect display marker, and the semiconductor wafer 1 roughly adjusted on the stage 5 is transferred to the inspection stage via the carrier 7. After fine adjustment of the position is performed here, each semiconductor element is moved one by one in the X, Y, and Z directions from the probe card 9 to the probe needle 11 that protrudes downward. If a hit occurs, characteristic tests are performed sequentially. In parallel with this inspection, the marker 10 of the marking mechanism is lowered to mark the surface of the defective semiconductor element with a defect recognition mark after the inspection for the semiconductor element which has been inspected as defective. The semiconductor wafer 1 whose characteristics have been inspected is taken out from the inspection stage 8 onto the carrier 12, stored in another magazine 2', and then sent to post-processes such as appearance inspection.

このようにフルオートウエーハプローバにマー
キング機能を持たせて、特性検査と併行してマー
キング動作を行わせる検査システムでは半導体ウ
エーハにおける半導体素子の不良品がマークによ
つて一目で判別され、後工程ではこの不良マーク
の付いた半導体素子を外観検査などの対象から外
して能率的に処理される。しかし、マーキング動
作を併行させる検査システムはマーカが下降して
上昇するマーキング動作の間プローバを休止させ
ておかねばならず、時間的な無駄があつて特性検
査の作業性が悪かつた。またマーキングは半導体
素子の表面にインクを付着させたり、引つ掻き傷
のような打痕を付けたりして行われるが、インク
の場合はインクの飛散が、打痕の場合は切削屑の
飛散が回りの良品の半導体素子の特性に悪影響を
与えることがあり、そのため1枚の半導体ウエー
ハの特性検査完了後に半導体ウエーハ上をエアー
ブロー等で清浄にする工程を必要とし、尚更に1
枚の半導体ウエーハの特性検査に要する時間や工
数が多くなる問題があつた。
In this way, in an inspection system in which a fully automatic wafer prober is equipped with a marking function and the marking operation is performed in parallel with the characteristic inspection, defective semiconductor elements on semiconductor wafers can be identified at a glance by the mark, and in the subsequent process. Semiconductor elements with this defective mark are excluded from visual inspection, etc., and processed efficiently. However, in an inspection system that performs marking operations concurrently, the prober must be kept at rest during the marking operations in which the marker descends and rises, which wastes time and degrades the workability of characteristic inspection. Marking is also done by applying ink to the surface of the semiconductor element or by making scratch-like impressions. may have an adverse effect on the characteristics of the surrounding non-defective semiconductor elements. Therefore, after the characteristic test of one semiconductor wafer is completed, a process of cleaning the semiconductor wafer with air blowing etc. is required, and an additional step is required.
There was a problem in that the time and man-hours required to inspect the characteristics of a single semiconductor wafer increased.

上記問題の解決策として、プローバからマーキ
ング機能を除き、代りにメモリ機能を持たせる次
の検査システムがある。即ち、マーキング動作は
一切行わず、半導体ウエーハの各半導体素子の特
性をプローバで1回ずつ検査してその良否判定結
果を磁気テープなどの記録媒体に記憶させ、そし
て、1つのマガジン内の所定枚数の半導体ウエー
ハの全ての特性検査が完了すると、この1ロツト
数の半導体ウエーハを特性検査のメモリ内容と共
に後工程に送る。後工程はメモリ内容から1枚ず
つの半導体ウエーハにおける不良半導体素子を検
出して処理対象から外す。
As a solution to the above problem, there is the following inspection system in which the marking function is removed from the prober and a memory function is provided instead. That is, without performing any marking operation, the characteristics of each semiconductor element on the semiconductor wafer are inspected once with a prober, and the pass/fail judgment results are stored in a recording medium such as a magnetic tape, and the predetermined number of wafers in one magazine is When all the characteristic tests of the semiconductor wafers are completed, this one lot of semiconductor wafers is sent to the subsequent process together with the memory contents of the characteristic test. In the post-process, defective semiconductor elements on each semiconductor wafer are detected from the memory contents and removed from the processing target.

このようなマーキング動作を省いた検査システ
ムは作業能率を大幅に改善し、且つマーキング機
構が無くて機構的に簡略化され、プローバのコス
トダウンが図れる等の長所を有する。ところが、
現実の問題として、半導体ウエーハに数百、数千
と形成された半導体素子のアドレスとプローバの
記録媒体に記憶されたメモリ内容のアドレスがず
れて対応しないことがあり、検査後工程で良品を
不良品として誤つて処理、或は不良品を良品とし
て処理することがあつて信頼性に欠ける問題があ
る。
An inspection system that eliminates such a marking operation has advantages such as greatly improving work efficiency, and being mechanically simplified since there is no marking mechanism, thereby reducing the cost of the prober. However,
As a real problem, the addresses of hundreds or thousands of semiconductor elements formed on a semiconductor wafer may not correspond to the addresses of the memory contents stored in the prober's recording medium. There is a problem of lack of reliability as there are cases where products are mistakenly treated as non-defective products or defective products are treated as non-defective products.

本発明はかかる問題点に鑑みてなされたもの
で、プローバのメモリ内容を抜き取り的に確認す
る工程を加えて、メモリ内容の信頼性を増大せし
めた検査システムを提供する。
The present invention has been made in view of these problems, and provides an inspection system that increases the reliability of the memory contents by adding a step of checking the memory contents of the prober at random.

本発明はフルオートウエーハプローバにマーキ
ング機能とメモリ機能を持たせ、1つのマガジン
に収納された1ロツト数の半導体ウエーハの特性
検査をマーキング動作なしで全て行うと、任意の
枚数の半導体ウエーハを抜き取つてその半導体ウ
エーハの特性検査結果のメモリ内容のデータでマ
ーキングのみを行い、後でこのマーキングされた
半導体ウエーハを使つてプローバのメモリ内容の
精度確認を行うことを特徴とする。このようにプ
ローバのメモリ内容を抜き取り的に検査確認する
ことにより、後工程を常に正しくデータ処理する
ことができ、信頼性が増す。
The present invention provides a fully automatic wafer prober with a marking function and a memory function, and when all characteristics of one lot of semiconductor wafers stored in one magazine are inspected without marking operations, an arbitrary number of semiconductor wafers can be extracted. The present invention is characterized in that only marking is performed using the data of the memory contents of the characteristic test results of the semiconductor wafer, and later the accuracy of the memory contents of the prober is confirmed using the marked semiconductor wafer. By inspecting and confirming the contents of the memory of the prober in this way, it is possible to always correctly process data in subsequent processes, increasing reliability.

例えば本発明は第2図に示すプログラムに従
う。先ず1つのマガジン2に収納された1ロツト
数、例えば50枚の半導体ウエーハ1をマーキング
機能とメモリ機能を有するフルオートウエーハプ
ローバaで1枚ずつ順次に特性検査し、全ての検
査結果を磁気テープなどの記録媒体bに記憶さ
せ、同時に記録紙などにマツピングデータcとし
てメモリ内容を印刷表示させておく。この特性検
査の際、半導体ウエーハの各半導体素子のアドレ
スを明確にするため、例えば第3図に示すように
1つの半導体素子上に全面金属蒸着によつて不良
チエツクマーキングとしてのスタートアドレスパ
ターンmを形成し、このスタートアドレスパター
ンmを基準にして他の半導体素子のアドレスを求
めるようにする。このようなスタートアドレスパ
ターンmはレーザ光を使用しなくとも簡単に検出
でき、後のマーキングのスタートアドレス捜しに
利用される。尚、第3図のn1,n2は目合せ専用パ
ターンである。
For example, the present invention follows the program shown in FIG. First, characteristics of one lot, for example, 50 semiconductor wafers 1 stored in one magazine 2 are sequentially inspected one by one using a fully automatic wafer prober a that has a marking function and a memory function, and all inspection results are recorded on a magnetic tape. etc., and at the same time print and display the memory contents as mapping data c on recording paper or the like. During this characteristic inspection, in order to clarify the address of each semiconductor element on the semiconductor wafer, for example, as shown in FIG. This start address pattern m is used as a reference to determine the addresses of other semiconductor elements. Such a start address pattern m can be easily detected without using a laser beam, and is used to search for a start address for later marking. Note that n 1 and n 2 in FIG. 3 are patterns exclusively for alignment.

50枚の半導体ウエーハ1の特性検出が全て完了
すると、次は検査済みの50枚の中から任意の数
枚、例えば3枚の半導体ウエーハ1を抜き取り、
これを1枚ずつ同じプローバaの検査ステージま
で移送させてマーキングを行う。このマーキング
は先に記録媒体bに記憶されたメモリを読み出し
て不良品データを求め、そのデータに基づいて抜
き取り半導体ウエーハ1の不良半導体素子上に不
良マークを選択的に付す動作で行われる。このよ
うなマーキング動作は50枚中の3枚の半導体ウエ
ーハ1に対してのみであり、而もメモリ内容のデ
ータ読み出しのみで行われるので、工数的に及び
時間的にあまり問題はない。次に3枚の抜き取り
半導体ウエーハのマーキング情報とプローバaに
おけるメモリ内容のマツピングデータcとを照合
して両者が一致しているか否かを調べ、情報精度
の確認をする。そして、照合結果が良好であれば
50枚全ての半導体ウエーハ1と記録媒体bのメモ
リ内容がずれ無く一致していると見なして後工程
に送り、照合結果が悪ければ再検査等する。
Once the characteristics of all 50 semiconductor wafers 1 have been detected, the next step is to pick out an arbitrary number of semiconductor wafers 1, for example, 3 semiconductor wafers 1, from among the 50 inspected wafers.
The sheets are transferred one by one to the inspection stage of the same prober a and marked. This marking is performed by first reading the memory stored in the recording medium b to obtain defective product data, and then selectively attaching defective marks to the defective semiconductor elements of the sampled semiconductor wafer 1 based on the data. Such a marking operation is performed only on three semiconductor wafers 1 out of 50, and is performed only by reading data from the memory contents, so there is no problem in terms of man-hours and time. Next, the marking information of the three sampled semiconductor wafers is compared with the mapping data c of the memory contents in the prober a to check whether they match or not, thereby confirming the accuracy of the information. And if the matching result is good
It is assumed that the memory contents of all 50 semiconductor wafers 1 and the recording medium b match without any deviation and are sent to the subsequent process, and if the comparison results are bad, a re-inspection is performed.

尚、上記マーキング動作はプローバ以外に設け
た専用のマーキングマシーンで行うことも可能で
工数低減上有利であるが、50枚中の3枚などと小
数枚数の半導体ウエーハのみにマーキングする場
合は本発明のようにプローバにマーキング機能を
付設してプローバで行うことが設備投資的には有
利である。さらに、この発明は、ウエーハ情報と
記録媒体のメモリ内容とを照合する時に、特性不
良表示打点マーキングを不良素子の一部か又は、
不良全数にわたり行う場合にも適用でき、また全
く特性不良表示打点マーキングを行わない場合に
でも適用できるものである。
Note that the above marking operation can be performed with a dedicated marking machine installed in addition to the prober, which is advantageous in terms of reducing man-hours, but when marking only a small number of semiconductor wafers, such as 3 out of 50, the present invention is suitable. It is advantageous in terms of equipment investment to add a marking function to the prober and use the prober to carry out the marking. Furthermore, when comparing the wafer information and the memory contents of the recording medium, the present invention detects whether the characteristic defect display dot marking is a part of the defective element or
This method can be applied to cases in which marking is performed on all defective items, and can also be applied in cases in which marking is not performed at all to indicate defective characteristics.

以上のように、本発明はプローバにマーキング
機能とメモリ機能を持たせて、抜き取り的にメモ
リ内容の精度を確認するようにしたので、特性検
査の後工程に入る情報の信頼性が増大し、歩留り
向上が図れる。
As described above, in the present invention, the prober is equipped with a marking function and a memory function, and the accuracy of the memory contents can be checked on a sample basis, thereby increasing the reliability of information that enters the post-process of characteristic inspection. Yield can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はフルオートウエーハプローバの検査シ
ステムの一例を説明するための概略側面図、第2
図は本発明の方法の一例を示す動作プログラム、
第3図は半導体ウエーハの一例を示す平面図であ
る。 1……半導体ウエーハ、a……プローバ、b…
…記録媒体、m……スタートアドレスパターン、
n1,n2……目合せ専用パターン。
Figure 1 is a schematic side view for explaining an example of a fully automatic wafer prober inspection system;
The figure shows an operating program illustrating an example of the method of the present invention.
FIG. 3 is a plan view showing an example of a semiconductor wafer. 1... Semiconductor wafer, a... Prober, b...
...Recording medium, m...Start address pattern,
n 1 , n 2 ... Patterns exclusively for alignment.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体ウエーハに形成された複数の半導体素
子の特性を個々に検査する機能に、各半導体素子
の特性検査結果を記憶するメモリ機能を持たせた
プローバで所定枚数の半導体ウエーハの特性検査
を行ないその結果を、マーキング動作することな
く順次記録媒体に記憶させる工程と、検査された
所定枚数の半導体ウエーハの内の任意の枚数を抜
き取つて、同一のプローバで、半導体ウエーハの
特性不良素子に選択的に不良チエツクマーキング
を付す工程と、抜き取り半導体ウエーハに付した
マーキング情報とプローバの記録媒体のメモリ内
容とを照合する工程を有することを特徴とする半
導体ウエーハ特性検査処理方法。
1 Testing the characteristics of a predetermined number of semiconductor wafers using a prober that has a function of individually testing the characteristics of multiple semiconductor elements formed on a semiconductor wafer and a memory function that stores the characteristics test results of each semiconductor element. A process of sequentially storing the results in a recording medium without performing a marking operation, and a process of extracting an arbitrary number of semiconductor wafers from a predetermined number of inspected semiconductor wafers and selectively detecting elements with defective characteristics on the semiconductor wafers using the same prober. 1. A semiconductor wafer characteristic inspection processing method comprising the steps of: attaching a defective check mark to a sampled semiconductor wafer; and comparing marking information attached to a sampled semiconductor wafer with memory contents of a recording medium of a prober.
JP57086956A 1982-05-21 1982-05-21 Inspecting and treating method for characteristic of semiconductor wafer Granted JPS58218132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57086956A JPS58218132A (en) 1982-05-21 1982-05-21 Inspecting and treating method for characteristic of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57086956A JPS58218132A (en) 1982-05-21 1982-05-21 Inspecting and treating method for characteristic of semiconductor wafer

Publications (2)

Publication Number Publication Date
JPS58218132A JPS58218132A (en) 1983-12-19
JPH0312463B2 true JPH0312463B2 (en) 1991-02-20

Family

ID=13901319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57086956A Granted JPS58218132A (en) 1982-05-21 1982-05-21 Inspecting and treating method for characteristic of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS58218132A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669053B2 (en) * 1984-04-06 1994-08-31 株式会社東京精密 Probing machine
JPH0692882B2 (en) * 1986-06-12 1994-11-16 松下電器産業株式会社 Printed circuit board inspection equipment

Also Published As

Publication number Publication date
JPS58218132A (en) 1983-12-19

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