JPH0312481B2 - - Google Patents
Info
- Publication number
- JPH0312481B2 JPH0312481B2 JP20768481A JP20768481A JPH0312481B2 JP H0312481 B2 JPH0312481 B2 JP H0312481B2 JP 20768481 A JP20768481 A JP 20768481A JP 20768481 A JP20768481 A JP 20768481A JP H0312481 B2 JPH0312481 B2 JP H0312481B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- operational amplifier
- flexible wiring
- output
- ground line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明はカメラの演算回路、特に回路の配線に
フレキシブル基板等の箔を用いたカメラの演算回
路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a camera arithmetic circuit, and more particularly to a camera arithmetic circuit using a foil such as a flexible substrate for circuit wiring.
カメラの演算回路は一眼レフカメラ等の場合ス
ペース的な問題からペンタプリズム部等に配設す
ることが要求され第１図の如くフレキシブル基板
に配線して、配置部の型状に合わせて自由に配線
することが出来る様構成されている。 In the case of single-lens reflex cameras, etc., the camera's arithmetic circuit is required to be placed in the pentaprism part etc. due to space issues, so it is wired on a flexible board as shown in Figure 1, and can be wired freely according to the shape of the part where it is placed. It is configured so that it can be wired.
しかしながら、回路の配線にフレキシブル基板
を用いた場合、通常フレキシブル基板は銅箔を使
用しており、その銅箔の厚みが薄く、かつ配線幅
も小さなため配線間で若干の抵抗を有し、該抵抗
に生ずる電圧の影響により演算誤差が生ずる欠点
があつた。 However, when a flexible board is used for circuit wiring, the flexible board usually uses copper foil, and because the copper foil is thin and the wiring width is small, there is some resistance between the wiring. There was a drawback that calculation errors occurred due to the influence of the voltage generated across the resistor.
第１図は従来のフレキシブル基板に配線される
カメラの演算回路例を示すもので、１は電源、２
はスイツチであり、シヤツターボタン第１ストロ
ークに連動してオンする。３は定電圧源でありそ
の電圧をｅとする。４，５は抵抗、６は演算増幅
器（以下OPアンプと称する）、１１，１２は抵
抗、１３はOPアンプ、１４，１６は抵抗、１７
はOPアンプ、１８はフレキシブル基板の配線に
よつてアースラインに生じる上述の配線間に生じ
る抵抗である。１９はフレキシブル基板の配線に
よつて電源ラインに生じる上述の抵抗である。尚
１０はフレキシブル基板内に実装されるものを示
す。 Figure 1 shows an example of a camera arithmetic circuit wired to a conventional flexible board, where 1 is the power supply, 2
is a switch, which is turned on in conjunction with the first stroke of the shutter button. 3 is a constant voltage source, and its voltage is designated as e. 4 and 5 are resistors, 6 is an operational amplifier (hereinafter referred to as an OP amplifier), 11 and 12 are resistors, 13 is an OP amplifier, 14 and 16 are resistors, 17
is an OP amplifier, and 18 is a resistance generated between the above-mentioned wirings, which is generated in the ground line due to the wiring of the flexible board. 19 is the above-mentioned resistance generated in the power supply line by the wiring of the flexible substrate. Note that 10 indicates what is mounted within the flexible substrate.
上述の如く構成された従来の回路において、シ
ヤツターボタンの第１ストロークを押圧するとス
イツチ２がオンし電源１からの電圧が所用の各部
に供給される。今抵抗４，５の抵抗比をG1とす
るとOPアンプ６の出力V1はV1＝G1eとなる。ま
たフレキシブル基板の配線によつて生じる抵抗１
８にOPアンプ１３，１７の消費電流が流れるこ
とにより生ずる抵抗１８の両端の電圧をe0とし抵
抗１１と１２の抵抗比をG2とするとOPアンプ１
３の出力V2は
V2＝e0＋（V1−e0）G2
となる。さらに抵抗１４，１６の抵抗比をG3と
するとOPアンプ１７の出力V3は
V3＝e0＋（V2−e0）G3
＝e0＋（G1e−e0）G2G3
＝（G1G2G3）ｅ＋e0（１−G2G3）
となる。フレキシブル基板に抵抗１８が存在しな
ければ、
V3＝（G1G2G3）ｅ
となるものであるため
e0（１−G2G3）
に相当する誤差が生ずることとなる。また抵抗１
９はOPアンプが全て対アース増幅であるため、
出力振幅等に影響を与えるだけで、演算には無関
係である。 In the conventional circuit configured as described above, when the first stroke of the shutter button is pressed, the switch 2 is turned on and voltage from the power source 1 is supplied to each required part. Now, assuming that the resistance ratio of the resistors 4 and 5 is G 1 , the output V 1 of the OP amplifier 6 becomes V 1 =G 1 e. In addition, resistance 1 caused by the wiring of the flexible board
If the voltage across resistor 18 caused by the current consumption of OP amplifiers 13 and 17 flowing through 8 is e 0 , and the resistance ratio of resistors 11 and 12 is G 2 , then OP amplifier 1
The output V 2 of No. 3 becomes V 2 = e 0 + (V 1 − e 0 )G 2 . Further, if the resistance ratio of the resistors 14 and 16 is G3 , the output V3 of the OP amplifier 17 is V3 = e 0 + (V 2 − e 0 ) G 3 = e 0 + (G 1 e−e 0 ) G 2 G 3 =(G 1 G 2 G 3 )e+e 0 (1−G 2 G 3 ). If the resistor 18 does not exist on the flexible substrate, V 3 =(G 1 G 2 G 3 )e, and therefore an error equivalent to e 0 (1−G 2 G 3 ) will occur. Also resistance 1
9 is because all OP amplifiers are ground amplification,
It only affects the output amplitude, etc., and is unrelated to calculations.
本発明は上述の欠点を解消せんとするものであ
り、フレキシブル基板外に上記誤差電圧を補正す
るための出力電圧を供給する増巾回路を設け、該
増巾回路出力をフレキシブル基板に配線された演
算回路に入力することにより上記誤差電圧を取り
除き常時正確な演算出力を得られる様になしたカ
メラの演算回路を提供するものである。 The present invention aims to solve the above-mentioned drawbacks, and includes an amplifying circuit that supplies an output voltage for correcting the above-mentioned error voltage outside the flexible substrate, and the output of the amplifying circuit is wired to the flexible substrate. The object of the present invention is to provide an arithmetic circuit for a camera in which the error voltage is removed by inputting the voltage to the arithmetic circuit so that an accurate arithmetic output can always be obtained.
次いで本発明に係るフレキシブル基板用演算回
路について説明する。第２図は本発明の一実施例
を示す回路図で、第１図と同素子、同動作のもの
は同一番号を用いている。 Next, a flexible substrate arithmetic circuit according to the present invention will be explained. FIG. 2 is a circuit diagram showing an embodiment of the present invention, in which the same elements and the same operations as in FIG. 1 are denoted by the same numbers.
第２図において、９はOPアンプ、７はOPアン
プ９の反転入力端に接続された抵抗、８はOPア
ンプ９の帰還路に接続された抵抗、１５はOPア
ンプ９の出力とOPアンプ１７の反転入力端間に
接続された抵抗である。該OPアンプ及び抵抗を
設けることで上述の誤差電圧を補正している。上
記抵抗７，８の抵抗比はG0、抵抗１５，１６の
抵抗比はG4に設定されていると共にG0G4＝G2G3
−１（G2は上述の如く抵抗１１，１２の抵抗比、
G3は上述の如く抵抗１４，１６の抵抗比）とな
る様、各抵抗７，８，１５，１６，１１，１２，
１４の抵抗値が決定されている。 In Fig. 2, 9 is an OP amplifier, 7 is a resistor connected to the inverting input terminal of the OP amplifier 9, 8 is a resistor connected to the feedback path of the OP amplifier 9, and 15 is the output of the OP amplifier 9 and the OP amplifier 17. is a resistor connected between the inverting input terminals of . By providing the OP amplifier and resistor, the above-mentioned error voltage is corrected. The resistance ratio of the resistors 7 and 8 is set to G 0 , and the resistance ratio of the resistors 15 and 16 is set to G 4 , and G 0 G 4 = G 2 G 3
-1 (G 2 is the resistance ratio of resistors 11 and 12 as described above,
G3 is the resistance ratio of resistors 14 and 16 as described above.
14 resistance values have been determined.
該第２図において、シヤツターボタンの第１ス
トロークを押圧するとスイツチ２がオンとなり、
電源１が所用の各部供給される。OPアンプ６の
出力V1は第１図と同様に
V1＝G1e
である。また同様にOPアンプ１３の出力V2は
V2＝e0＋（V1−e0）G2
である。 In FIG. 2, when the first stroke of the shutter button is pressed, switch 2 is turned on,
Power supply 1 is supplied to each required part. The output V 1 of the OP amplifier 6 is V 1 =G 1 e as in FIG. Similarly, the output V2 of the OP amplifier 13 is V2 = e0 +( V1 - e0 ) G2 .
OPアンプ９の出力V4はOPアンプ９の非反転
入力端子がOPアンプ１３，１７の非反転入力端
子と接続されているため
V4＝（１＋G0）e0
となり、その電圧が抵抗１５，１６、OPアンプ
１７により演算される。またOPアンプ１７では
OPアンプ１３の出力も抵抗１４，１６にて演算
されるためその出力V3は
V3＝e0＋（V2−e0）G3＋（V4−e0）G4
＝e0＋（G1e−e0）G2G3＋G0G4e0
＝（G1G2G3）ｅ＋e0（１−G2G3＋G0G4）
となる、従つて、上述の如くG0G4＝G2G3−１と
なる様各抵抗７，８，１５，１６，１１，１２，
１４の抵抗値が決定されているので
１−G2G3＋G0G4
の項が零となりV3＝G1G2G3eとなる。よつて抵
抗１８により生ずる誤差が補正され、正確な演算
結果が得られることとなる。 The output V 4 of the OP amplifier 9 becomes V 4 = (1 + G 0 ) e 0 because the non-inverting input terminal of the OP amplifier 9 is connected to the non-inverting input terminals of the OP amplifiers 13 and 17, and the voltage is applied to the resistor 15, 16, it is calculated by the OP amplifier 17. Also, in OP amp 17
Since the output of the OP amplifier 13 is also calculated by the resistors 14 and 16, its output V 3 is V 3 = e 0 + (V 2 − e 0 ) G 3 + (V 4 − e 0 ) G 4 = e 0 + (G 1 e−e 0 )G 2 G 3 +G 0 G 4 e 0 = (G 1 G 2 G 3 )e+e 0 (1−G 2 G 3 +G 0 G 4 ).Therefore, as mentioned above, Each resistor 7, 8, 15, 16, 11, 12, so that G 0 G 4 = G 2 G 3 -1,
Since the resistance value of 14 has been determined, the term 1-G 2 G 3 +G 0 G 4 becomes zero, and V 3 =G 1 G 2 G 3 e. Therefore, the error caused by the resistor 18 is corrected, and accurate calculation results can be obtained.
以上の如く、本発明はフレキシブル基板外に増
巾回路を設け、該回路の出力を演算回路に入力す
ることによつてフレキシブル基板に配線されるこ
とにより生ずる抵抗に起因する演算誤差を補償し
たものであるため、フレキシブル基板に配線され
るカメラの演算回路において多大な効果を戻すも
のである。 As described above, the present invention provides an amplification circuit outside the flexible substrate and inputs the output of the circuit to an arithmetic circuit to compensate for calculation errors caused by resistance caused by wiring on the flexible substrate. Therefore, it brings back a great effect in the arithmetic circuit of the camera wired to the flexible substrate.
第１図は従来のフレキシブル基板に配線された
演算回路例を示す回路図、第２図は本発明に係る
演算回路の一実施例を示す回路図である。
９……演算増巾器、７，８，１５……抵抗。
FIG. 1 is a circuit diagram showing an example of an arithmetic circuit wired on a conventional flexible substrate, and FIG. 2 is a circuit diagram showing an example of an arithmetic circuit according to the present invention. 9... Arithmetic amplifier, 7, 8, 15... Resistor.
Claims (1)
成回路からの出力電圧をフレキシブル配線基板内
に設けられる第１の演算増巾器の一方の入力端に
伝え演算処理を行なうとともに、前記信号形成回
路に対してフレキシブル配線基板外に設けられる
電源ライン及びアースラインを介して給電し前記
第１の演算増巾器に対して前記電源ライン及びア
ースラインから延長されフレキシブル配線基板内
に設けられる電源ライン及びアースラインを介し
て給電するフレキシブル配線基板用演算回路にお
いて、一方の入力端を前記フレキシブル配線基板
外のアースラインと接続し他方の入力端を前記フ
レキシブル配線基板内のアースラインの前記第１
の演算増巾器側に接続する第２の演算増巾器を設
け、該第２の演算増巾器の出力を前記第１の演算
増巾器の前記一方の入力端に入力し、前記第２の
演算増巾器の出力を前記フレキシブル配線基板内
のアースラインによつて生じる抵抗に発生する電
位差に相応した値となし、該抵抗に発生する電位
差による演算出力の誤差を補正したことを特徴と
するフレキシブル配線基板用演算回路。1 The output voltage from the signal forming circuit provided outside the flexible wiring board is transmitted to one input terminal of a first operational amplifier provided within the flexible wiring board to perform calculation processing, and the signal forming circuit is Power is supplied to the first operational amplifier via a power line and a ground line provided outside the flexible wiring board, and a power line and a ground line extended from the power line and ground line and provided inside the flexible wiring board are connected to the first operational amplifier. In an arithmetic circuit for a flexible wiring board, one input end is connected to the ground line outside the flexible wiring board, and the other input end is connected to the first ground line of the flexible wiring board inside the flexible wiring board.
A second operational amplifier connected to the operational amplifier side is provided, the output of the second operational amplifier is input to the one input terminal of the first operational amplifier, and the output of the second operational amplifier is inputted to the one input terminal of the first operational amplifier. The output of the operational amplifier No. 2 is set to a value corresponding to the potential difference generated in the resistance caused by the ground line in the flexible wiring board, and the error in the calculation output due to the potential difference generated in the resistance is corrected. Arithmetic circuit for flexible wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20768481A JPS58107704A (en) | 1981-12-21 | 1981-12-21 | Operation circuit for flexible wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20768481A JPS58107704A (en) | 1981-12-21 | 1981-12-21 | Operation circuit for flexible wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58107704A JPS58107704A (en) | 1983-06-27 |
| JPH0312481B2 true JPH0312481B2 (en) | 1991-02-20 |
Family
ID=16543857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20768481A Granted JPS58107704A (en) | 1981-12-21 | 1981-12-21 | Operation circuit for flexible wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58107704A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112021002027T5 (en) | 2020-03-30 | 2023-01-12 | Ube Material Industries, Ltd. | Polypropylene resin composition, process for producing a polypropylene resin composition and molded article |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH084206B2 (en) * | 1986-07-18 | 1996-01-17 | 株式会社日立製作所 | Amplifier circuit |
-
1981
- 1981-12-21 JP JP20768481A patent/JPS58107704A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112021002027T5 (en) | 2020-03-30 | 2023-01-12 | Ube Material Industries, Ltd. | Polypropylene resin composition, process for producing a polypropylene resin composition and molded article |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58107704A (en) | 1983-06-27 |
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