JPS6019543B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic unit, and more particularly to an improvement in an arithmetic unit used as an electronic industrial instrument that uses a signal with a constant bias as an input signal and a signal with the same bias as an output signal. .

In general, input/output signals of industrial instruments used for control of process industries, etc., are often electrical signals including a constant bias DCIV, which is unrelated to the signal, such as DCI to 5V.

Therefore, adder/subtractor, multiplier/divider,
When various arithmetic units such as a square root arithmetic unit perform their respective calculations, they subtract DCIV, which is a constant bias in the input signal, and add DCI to the resulting signal.
By adding V, a signal of DCI to 5V is made into an output signal. By the way, bias processing of input/output signals of this type of arithmetic unit has conventionally been performed using a circuit shown in FIG.

In Fig. 1, 1, ~ln are input terminals, lc is a common input terminal, and input terminals 1, 12, ......, ln
and common input terminal lc, respectively, input signals DCI~5
V is input, the calculation is executed in the calculation circuit 2, and the output terminal 3
An output signal DCI~5V is obtained between and 3c. However, the common input terminal lc and the output terminal 3c are connected by a common line 4, and the reference potential line 2a of the arithmetic circuit 2
A bias power supply (DCIV) 5 is connected between the arithmetic circuit 2 and the common line 4, and when the arithmetic circuit 2 is an adder circuit, the respective input signals are
2, . . . , Vn, the following equation is calculated. V.

=K. (V, 11) 10K2 (V2-1) 10...
・・・10Kn(Vn-1) ・・・・・・・・・
・{1' Here, K, ~Kn: Coefficients respectively. Vo: Output voltage of the arithmetic circuit 2.

Then, the voltage DCI of the bias power supply 5 is applied to this world voltage Vo.
V is added and V=V.

11. A signal V represented by ■ is sent out as an output signal from the output terminals 3 and 3c. However, in the conventional circuit configuration shown in FIG. 1 in which the input signal is directly input to the arithmetic circuit 2, for example, when setting the coefficient K of the m formula, each input signal V2, V3, . . .
..., Vn must be set as IV, excluding the influence of terms other than the K and (V, -1) terms.

However, at this time, it is necessary to accurately set the input signal to IV, and for this purpose, a constant voltage source that can be accurately adjusted is required. In addition, if any of the input signals Vi (i=1 to n) is short-circuited to the common line 4, it is equivalent to -
This means that IV has been input, and as a result, the arithmetic circuit 2 may be destroyed. Furthermore, since the input impedance of the arithmetic circuit 2 in the voltage signal system is large, in an arithmetic unit that inputs multiple input signals, it is better to short-circuit it to the unused input terminal lc. However, it is not possible for the reasons mentioned above. Therefore, there was an inconvenience that a short circuit had to be made within the arithmetic circuit 2. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide an arithmetic unit in which coefficients can be easily set.

The present invention provides an arithmetic unit in which an arithmetic operation is performed by subtracting a predetermined bias level from input signals applied to a plurality of input terminals, and outputting the result by adding the predetermined bias level to the arithmetic result. A signal is connected between each of the plurality of input terminals and the arithmetic unit, and when the input signal is below the bias level, the signal is held at the bias level, and when the input signal is above the bias level, the signal is held at the bias level. The present invention is characterized in that it includes an input signal processing circuit that generates a signal proportional to the portion above the bias level, and a coefficient setting circuit that multiplies the output signal of the input signal processing circuit by a coefficient.

Embodiments of the present invention shown in FIGS. 2 and 4 and 3.
This will be explained in detail using figures.

FIG. 2 is a circuit diagram showing an embodiment of the arithmetic unit of the present invention, illustrating the case of an adder, and only a portion of the input terminals and related input circuits are shown.

In Figure 2, 1., 12, ......, li-., li,
......, ln are input terminals, among which li-,,
Only li is shown. lc is a common input terminal. The input terminal lH is connected to the non-inverting input terminal of the operational amplifier 6, the output side of the operational amplifier 6 is connected to the anode side of the diode 7, and the cathode side of the diode 7 is connected to the inverting input terminal of the operational amplifier 6. The terminal is connected to one end of a variable resistor 8 for setting the coefficient Ki-. The intermediate terminal of the variable resistor 8 is connected to the input side of the arithmetic circuit 2, and the other end is connected to the common line 4 via the bias power supply 5. The operational amplifier 6 and the diode 7 form an idealized diode circuit, and this and the variable resistor 8 form an input circuit 9.
It consists of The input terminal 1 is connected to the inverting input terminal of an operational amplifier 11 via a resistor 10, and the output side of the operational amplifier 11 is connected to the cathode side of a diode 12. It is connected to the inverting input terminal of the operational amplifier 11, forming an inverting amplifier.

The anode side of the diode 12 is connected via a resistor 15 to the inverting input terminal of the operational amplifier 11, and to one end of a variable resistor 16 for setting the coefficient Ki. The intermediate terminal of the variable resistor 16 is connected to the input side of the arithmetic circuit 2.
Further, the terminal is connected to the common line 4 via the bias power supply 5, and further connected to the non-inverting input terminal of the operational amplifier 11 via the resistor 17. The inverting amplifier and the diode 12 constitute an inverting idealization diode circuit, and this and the variable resistor 16 constitute an input circuit 18. Next, the operation will be explained.

The input signal Vi-, which is input between the input terminal li- and the common input terminal lc, is input to the input circuit 9, and the output Vi-, of the idealized diode circuit is divided by the variable resistor 8 to give the signal a coefficient Ki. -, are multiplied and input to the arithmetic circuit (in the embodiment, an adder circuit) 2. In addition, the input signal Vi input between the input terminal li and the common input terminal lc is input to the input circuit 18.
Input the inverted idealization, . Output of the diode circuit -V'
i is divided by the variable resistor 16 to give the signal a coefficient Ki
is multiplied and input to the arithmetic circuit 2. At this time, since the bias component of the signal is removed by the bias power supply 5, the signals input to the arithmetic circuit 2 are respectively K, -, (V'i-
, -1), and Ki (V'i-1). The input/output characteristics of the idealized diode circuit are as shown in Figure 3a, and the input/output characteristics of the inverted idealized diode circuit are as shown in Figure 3a.
The result is as shown in Figure b. That is, in FIG. 3a, when the input signal VI-, is below the bias level (DCIV), the output signal V'i-, is held at the bias level, and when Vi-, is above the bias level, Vi-
, becomes a signal proportional to the portion of Vi-, which is above the bias level, and in Fig. 3b, when the input signal Vi is below the bias level, the output signal V'i is held at the bias level, and when Vi When it is above the level, V
'i becomes an inverted signal that increases in the negative direction in proportion to the portion of Vi that is equal to or higher than the bias level. Therefore, the arithmetic expression performed by the arithmetic circuit 2 is V, assuming that an input circuit similar to the input circuit 9 is connected to the input terminal li. =K,
(V', 11) 10...Ki-, (V;-, 11) 10K
, (V'i-1) ten...... ten Kn (V'n-1) ...
...{3' becomes. Then, the voltage DCIV of the bias power supply 5 is added to this output voltage Vo, and V=V.

A signal V represented by 11 is sent out as an output signal from between the output terminals 3 and 3c.

That is, the input circuit 9 is used for signal addition, and the input circuit 18 is used for signal subtraction. According to the embodiment of the present invention, even if the input terminal is short-circuited to the common input terminal lc, the voltage input to the arithmetic circuit 2 becomes OV, and the arithmetic circuit 2 is not destroyed.

Therefore, when setting the coefficient Ki of an arbitrary term, input terminals other than the input terminal lj can be shorted to the common input terminal lc to eliminate the influence of other terms, and the setting can be made accurately as before. This eliminates the need for an adjustable constant voltage source, making it easy to set coefficients. In addition, unnecessary input terminals of the multi-input arithmetic unit can be short-circuited to the common input terminal lc, which eliminates the trouble of short-circuiting within the arithmetic circuit 2 as in the conventional case. This has the advantage of being countermeasureable. Figure 4 shows the input circuit 9 of Figure 2.
In FIG. 4, the cathode side of the diode 7 is connected to the operational amplifier 6 via a resistor 19.
It is the same as that shown in FIG. 2 except that the end of the variable resistor 8 on the bias power supply 5 side is connected to the inverting input terminal of the operational amplifier 6 via a resistor 20.

In this case, the portion of the input signal Vi-, which is equal to or higher than the bias level, is amplified by the input circuit 21 before being input to the arithmetic circuit 2, so the signal range for arithmetic operations in the arithmetic circuit 2 is widened, and the accuracy of the arithmetic operation is improved. There is a new effect that can be improved.
Other effects are the same as in FIG. As explained above, according to the present invention, it becomes easy to set a coefficient to be multiplied by a signal, and furthermore, it is possible to short-circuit unnecessary input terminals to a common input terminal in the input arithmetic unit to reduce the influence of external noise. It has the remarkable effect of being able to

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional arithmetic unit, Fig. 2 is a circuit diagram showing an embodiment of the arithmetic unit of the present invention, and Fig. 3 is an input/output characteristic diagram of each input circuit in Fig. 2. FIG. 4 is a circuit diagram showing another embodiment of the input circuit of the arithmetic unit of the present invention. 1・~ln, li-,, li...input terminal, lc...
・Common input terminal, 2... Arithmetic circuit, 3, 3c・
...Output terminal, 4...Common line, 5...Bias power supply, 6,11...Operation amplifier, 7,1
2... Diode, 8, 16... Variable resistor, 9, 18, 21... Input circuit. Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. An operation in which an operation is performed by subtracting a predetermined bias level from input signals applied to a plurality of input terminals and inputting the result, and adding the predetermined bias level to the operation result and outputting the result. in the device, between each of the plurality of input terminals and the arithmetic unit, when the input signal is below the bias level, the signal is held at the bias level,
An input signal processing circuit that generates a signal proportional to a portion above the bias level when the input signal is above the bias level, and a coefficient setting circuit that applies a coefficient to the output signal of the input signal processing circuit are provided. A computing unit characterized by: 2. The arithmetic unit according to claim 1, wherein the input signal processing circuit is a diode. 3. The input signal processing circuit is an idealizing diode circuit consisting of an operational amplifier or an inverting amplifier and a diode, and the coefficient setting circuit is connected between the output end of the idealizing diode circuit and the bias setting power source. The computing unit according to claim 1, which is a connected resistor.