JPH0318355B2 - - Google Patents

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having a pnp or npn structure or a composite structure thereof, and particularly relates to a semiconductor integrated circuit suitable for preventing leakage current due to an inversion layer peculiar to a MOS structure. circuit.

[Conventional technology]

Figure 3 shows the so-called metal-insulating layer-semiconductor structure.
The structure of the MOS element 101 and the state of the inversion layer configuration due to voltage application are shown.

In the same figure a, 1 is an n-type semiconductor layer, 2 is
The SiO ₂ insulating layers 3a and 3b are electrodes attached to the bottoms of the insulating layer 2 and the n-type semiconductor layer 1, respectively. When a negative voltage (positive if the semiconductor layer 1 is p-type) is applied to the electrode 3a on the insulating layer 2 side (positive if the semiconductor layer 1 is p-type), the majority carriers in the n-type semiconductor layer 1 are applied as shown in FIG. 3b. An electron moves to electrode 3 due to electric field 4.
b, and only positive fixed charges (donors) remain at the boundary between the insulating layer 2 and the n-type semiconductor layer 1, forming a so-called depletion layer 5. Furthermore, when the voltage applied to the electrode 3a is strengthened in the negative direction, positive charges are induced at the boundary between the depletion layer 5 and the insulating layer 2, as shown in FIG. 3c, and a conductive p-type inversion layer 6 is formed. be done.

In FIG. 4, p-type conductive layers 7a and 7b are formed on one main surface side of the n-type semiconductor layer 1, and p-type conductive layers 7a,
7b, electrodes 3 respectively provided on the insulating layer 2;
MOS transistor 10 consisting of a, 3b, 3c
2 is shown. As shown in _FIG .
When a positive voltage is applied to the insulating layer 2 (abbreviated as p ₂ ) and the electrode 3c on the insulating layer 2 is opened, the voltage changes from p ₁ layer 7a to p ₂ layer 7b.
A depletion layer 5a is formed at the boundary between the n-type semiconductor layer 1 (hereinafter abbreviated as _nB ) _p2 layer 7b due to the electric field 4a directed toward . Normally, the concentration of the n _B layer 1 is sufficiently lower than that of the p ₁ layer 7a or the p ₂ layer 7b, so the depletion layer _5a is
It spreads out to the side, and there is a fixed positive charge inside it.

In this state, p ₂ is applied to the electrode 3c as shown in FIG. 4b.
When a negative voltage is applied to the layer 7b, a depletion layer 5b is formed by the electric field 4b directed from the _p1 layer 7a toward the electrode 3c, due to the same phenomenon as in the MOS element 101 shown in FIG. Inversion layer 6
is also formed.

Since the inversion layer 6 is inverted to p-type, the p _-1 layer 7a
- A channel due to positive charge is formed between the _{p 2} layers 7b, and a voltage is applied between the p ₁ layers 7a and the p ₂ layers 7b, so between the p ₁ layers 7a and the p ₂ layers 7b. Leakage current can easily flow through. It is easily inferred that this current is greatly influenced by the potential of the electrode 3c.

Now, with reference to FIG. 5, we will explain the phenomenon in which the increase in leakage current due to the MOS transistor effect occurs even in lateral type PNP elements, and the field plate structure that is a typical defense against this phenomenon.

FIG. 5a shows the MOS transistor 102 of FIG.
The state in which the electrode 3c is removed is shown in FIG.

In the actual device 103, charges such as Na ions are present in the insulating layer 2 made of SiO ₂ , for example.
Further, surface deposits 8 such as resin used for surface protection are also present on the insulating layer 2.

Now, when a positive voltage is applied between the _p1 layer 7a and the _p2 layer 7b, an electric field 4c is generated on the surface in addition to the electric field 4a, and this electric field 4c causes the movement of charges in the insulating layer 2 and surface deposits 8, so-called polarization. A phenomenon occurs. As a result, a negative polarization charge 9 is generated on the _p1 layer 7a side, and the state is the same as when a negative voltage is applied to the electrode 3c on the insulating layer 2 of the MOS transistor 102 shown in FIG. 4b. As described above, as a result, the leakage current due to the formation of the inversion layer 6 increases.

One of the solutions to this problem is the field plate structure. FIG. 5b shows that a part 10 of the electrode 3a on the _p1 layer 7a to which a positive voltage is applied in the lateral type pnp element 103 is expanded as a field plate electrode to a size larger than the width of the _p1 layer 7a. This is what I did.

With this structure, the electric field 4c is generated near the end 10a of the field plate electrode 10, so the polarized charges 9 are also generated closer to the _p2 layer 7b than near the end, and the depletion layer 5b is also generated closer to the p2 layer 7b than near the end 10a of the field plate electrode 10. The inversion _layer 6 was formed on the _p2 layer 7b side, and as a result, the inversion layer 6 emitted from the p2 layer 7b was cut off at the lower end 10b before reaching the _p1 layer 7a.

Lateral type using field plate structure
A conventional example of a pnpn element (so-called thyristor) is shown in FIG.

Figure 6 shows an island surrounded by island boundaries 13 that are mutually insulated by dielectric isolation or pn junction isolation method.
A p-type conductive layer 7 is formed in the type semiconductor layer 1 (hereinafter abbreviated as _nB ).
b (hereinafter abbreviated as _pE layer) and 7a (hereinafter abbreviated as _pB layer), and furthermore, an n-type conductive layer 15 (hereinafter abbreviated as _pB layer) is formed in pB layer 7a.
(abbreviated as _nE ), and electrodes 3b, 3a and 14 are formed in the respective conductive layers through holes provided in the insulating layer 2.
A lateral type pnpn element 104 is shown. In FIG. 6a, in order to facilitate understanding, the insulating layer 2 is omitted, and the portion surrounded by the two-dot chain line indicates the contact area between each electrode and the semiconductor layer. Each electrode 3a, 3b, 14 is provided with a field plate electrode 10, respectively. The electrode 1
The 0 portion is shaded.

In the same figure a, when looking at the cross section along the - cutting line, as shown in the same figure b, the p _B layer 7a and the p _E layer 7b
It can be seen that the structure between the holes is as shown in FIG. 5b, and the structure can prevent channel formation.

However, when looking at the cross section along the cutting line including the so-called gate-cathode gap of the thyristor between the _pB layer 7a and the _nE layer 15, as shown in figure c,
It is not possible to form an electrode on the p _B layer 7a due to its structure, and even if an exposed portion 16 where no field plate is formed is formed, the cross-sectional structure is equivalent to the cross-sectional structure of FIG. 5a in which the width of the p-type conductive layer and the electrode are equal. It's getting old. Therefore, a channel is formed in this portion, and leakage current flows through this channel.

[Problem that the invention seeks to solve]

As mentioned above, in lateral type thyristors, due to the provision of the gate electrode, there are areas where the field plate cannot be formed on the gate electrode or the main electrode on the side adjacent to the gate electrode, resulting in the problem of increased leakage current. Was.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit having a lateral type element that prevents channel formation and reduces leakage current.

[Means for solving problems]

A feature of the present invention is that an electrode and a high concentration region are formed in the vicinity of the conductive layer receiving the channel in place of the field plate.

Specifically speaking, the features of the present invention are as follows:
In a semiconductor layer of one conductivity type insulated from other semiconductor layers by an island boundary, first and second semiconductor regions of the other conductivity type are provided adjacent to the surface of the semiconductor layer and separated from each other. a third semiconductor region of one conductivity type extending inward from the surface;
The first, second and third semiconductor regions include first and second semiconductor regions.
and a third electrode are in low resistance contact, these electrodes are spaced apart from each other and are arranged on the surface of the semiconductor layer with an insulating layer interposed therebetween, and extend beyond the island boundary,
One side of the first and third electrodes has an anti-inversion electrode portion extending on the insulating layer toward the island boundary, and one side of the first and third electrodes has an anti-inversion electrode portion extending on the insulating layer toward the island boundary, and a portion of the semiconductor layer extends from a portion of the semiconductor layer corresponding to an end of the anti-inversion electrode portion. A high concentration region of one conductivity type having a higher impurity concentration than the semiconductor layer reaching the island boundary is provided, and when viewed from above the surface of the semiconductor layer, the electrode on one side, the anti-inversion electrode portion, the high concentration region and The present invention is characterized in that the island boundary surrounds the other side of the first and third electrodes.

[Effect]

With this configuration, when the depletion layer and/or inversion layer extends from the second semiconductor region side, the depletion layer and/or inversion layer extends from the first and third semiconductor regions.
The extension is stopped at one side of the electrode, the anti-inversion electrode portion, the high concentration region and the island boundary, and the possibility that the depletion layer and/or inversion layer reaches the first semiconductor region can be eliminated.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings shown as examples.

FIG. 1 shows an n-type semiconductor layer 1 (hereinafter referred to as _nB layer) surrounded by island boundaries 13 that are mutually insulated by dielectric insulation isolation or pn junction isolation method, and which is adjacent to the surface of _nB layer. A p-type dielectric layer 7a (hereinafter referred to as _pB layer) and 7b (hereinafter referred to as _pE layer) are formed which are separated from each other, and an n-type dielectric layer 15 (hereinafter referred to as _nE layer) extending from the surface to the inside is formed in the _PB layer 7a. A lateral type pnpn element is formed in which a gate electrode 3a, an anode electrode 3b, and a cathode electrode 14 are in ohmic contact with each conductive layer 7a, 7b, and 15 through holes provided in an insulating layer 2. It shows. 17 is a gate electrode 7a formed integrally with the cathode electrode 14;
An anti-inversion electrode portion extends from the side end toward the island boundary 13 on the insulating layer 2 between the anode electrode 3b and the gate electrode 7a, and 18 is an end portion of the anti-inversion electrode portion 17 of the semiconductor layer 1 on the island boundary 13 side. An n-type high concentration layer (hereinafter referred to as an
n ⁺ layer). The anti-inversion electrode portion 17 and the n ⁺ layer 18 are configured to surround the gate electrode 3a in cooperation with the cathode electrode 14 and the island boundary 13 when viewed from the surface of the n _B layer 1. In other words, the inversion prevention electrode portion 17 and the n ⁺ layer 18 block the depletion layer and/or inversion layer extending from the _pE layer 7b side to the _pB layer 7a side before reaching the _pB layer 7a. It is structured as follows.

The depletion layer and the inversion layer are prevented from extending from the _pE layer 7b side to the _pB layer 7a side.

The blocking mechanism will be explained with reference to FIG. 1b.

When a reverse voltage is applied that makes the p _B layer 7a positive with respect to the p _E layer 7b, this voltage causes the deposits to 8
Polarization occurs inside, and a negative electrode 9 is formed on the gate electrode 3a side.
are attracted, and an inversion layer 6 is generated accordingly. On the other hand, the inversion layer prevention electrode portion 17 and the island boundary 13
An n ⁺ layer 18 is present in the area between.
This n ⁺ layer 18 contains a large amount of electrons. As explained in FIG. 4b, the inversion layer 6
There is a positive charge inside. Inversion layer 6 is n ⁺ layer 1
8, the electrons in the n ⁺ layer 18 and
A neutralization effect occurs between the positive charges of the inversion layer 6, and the extension of the inversion layer 6 is stopped at this portion.

That is, the n ⁺ layer 18 acts as a channel stopper.

Therefore, the n ⁺ layer 18 cooperates with the anti-inversion electrode portion 17 to prevent the inversion layer 6 from connecting the p _B layer 7a and the p _E layer 7b.

FIG. 2 shows an example of the frequency distribution of reverse leakage current in a pnpn element to which the present invention is applied. The graph with diagonal lines is the result of the conventional example,
It will be understood that according to the present invention, the reverse leakage current is reduced to 1/10000.

The present invention has been described above by taking one implementation as an example.
The present invention is not limited to this, but may be modified in various ways,
For example, it is possible to form the anti-inversion electrode part integrally with the gate electrode, and to apply it to other than pnpn elements.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a semiconductor integrated circuit having a lateral type element that prevents channel formation and reduces leakage current.

[Brief explanation of the drawing]

Figure 1 shows a semiconductor integrated circuit to which the present invention is applied, where a is a plan view, b is a sectional view taken along the - line, and Figure 2 is the degree of reverse leakage current in pnpn elements according to the present invention and conventional examples. Distribution map, Figure 3
Figure 4 is a cross-sectional view explaining the principle of a MOS element.
FIG. 5 is a cross-sectional view explaining the principle of a MOS transistor, FIG. 5 is a cross-sectional view explaining the principle of a MOS transistor having a field plate electrode, and FIG. 6 is a plan view and cross-sectional view showing a semiconductor integrated circuit having a conventional pnpn element. be. 1... N-type semiconductor layer, 3a, 3b, 14... Electrode, 7a, 7b... P-type conductive layer, 13... Island boundary, 17... Inversion prevention electrode portion, 18... N-type high concentration layer.

Claims (1)

[Claims] 1. In a semiconductor layer of one conductivity type insulated from other semiconductor layers by an island boundary, first and second semiconductor regions of the other conductivity type are provided adjacent to the surface thereof and separated from each other. A third semiconductor region of one conductivity type is provided in the first semiconductor region and extends inward from the surface, and first, second and third electrodes are provided in the first, second and third semiconductor regions. are in low resistance contact, these electrodes are spaced apart from each other and are arranged on the surface of the semiconductor layer via an insulating layer and extend beyond the island boundary, one side of the first and third electrodes is connected to the It has an anti-inversion electrode portion that extends on the insulating layer toward the island boundary, and has a higher impurity concentration than the semiconductor layer that reaches the island boundary from a location corresponding to the end of the anti-inversion electrode portion of the semiconductor layer. A high concentration region of one conductivity type is provided, and when viewed from above the surface of the semiconductor layer, the electrode on one side, the anti-inversion electrode portion, the high concentration region, and the island boundary form one of the first and third electrodes. A semiconductor integrated circuit, characterized in that the semiconductor integrated circuit surrounds the other side of the circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the island boundary is formed by a dielectric isolation method.