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JPH031855B2 - - Google Patents
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JPH031855B2 - - Google Patents

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Publication number
JPH031855B2
JPH031855B2 JP9445481A JP9445481A JPH031855B2 JP H031855 B2 JPH031855 B2 JP H031855B2 JP 9445481 A JP9445481 A JP 9445481A JP 9445481 A JP9445481 A JP 9445481A JP H031855 B2 JPH031855 B2 JP H031855B2
Authority
JP
Japan
Prior art keywords
signal
input
monaural
circuit
pulse train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9445481A
Other languages
Japanese (ja)
Other versions
JPS57208745A (en
Inventor
Tadashi Noguchi
Koji Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP9445481A priority Critical patent/JPS57208745A/en
Publication of JPS57208745A publication Critical patent/JPS57208745A/en
Publication of JPH031855B2 publication Critical patent/JPH031855B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H40/00Arrangements specially adapted for receiving broadcast information
    • H04H40/18Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/72Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for noise suppression
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/1646Circuits adapted for the reception of stereophonic signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Stereo-Broadcasting Methods (AREA)

Description

【発明の詳細な説明】 本発明はステレオ復調回路に関し、特にスイツ
チング方式によるマルチプレツクスステレオ復調
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stereo demodulation circuit, and more particularly to a multiplex stereo demodulation circuit using a switching method.

FM検波信号であるコンポジツト信号から左右
チヤンネル信号に分離復調するマルチプレツクス
復調回路には、コンポジツト信号と38KHzのサブ
キヤリヤ信号との乗算を行つて復調する方式があ
る。第1図はかゝる乗算方式による復調回路の原
理を説明するブロツク図であり、コンポジツト信
号V(t)は乗算器1,2に夫々入力されて、サ
ブキヤリヤ信号の正及び逆相信号と乗算される。
これら各乗算出力が加算器3,4に夫々入力され
ており、一方、コンポジツト信号が抵抗5,6を
それぞれ介して入力されている。従つて、各加算
器3,4では各乗算出力V1(t),V2(t)とコン
ポジツト信号中のメイン信号成分とがそれぞれ加
算されて、左右チヤンネル信号成分が分離される
ようになつている。
A multiplex demodulation circuit that separates and demodulates a composite signal, which is an FM detection signal, into left and right channel signals has a method of demodulating by multiplying the composite signal by a 38KHz subcarrier signal. FIG. 1 is a block diagram illustrating the principle of a demodulation circuit using such a multiplication method. A composite signal V(t) is input to multipliers 1 and 2, respectively, and multiplied by the positive and negative phase signals of the subcarrier signal. be done.
These multiplication outputs are input to adders 3 and 4, respectively, while composite signals are input via resistors 5 and 6, respectively. Therefore, in each of the adders 3 and 4, the respective multiplication outputs V 1 (t) and V 2 (t) are added to the main signal component in the composite signal, and the left and right channel signal components are separated. ing.

かゝる構成において、コンポジツト信号V(t)
は、 V(t)=L(t)+R(t)+ {L(t)−R(t)}cosωSt ……(1) で示される。ここに、L(t),R(t)は左右チ
ヤンネル信号であり、ωSはサブキヤリヤ信号の
角周波数である。この信号V(t)とサブキヤリ
ヤ信号の正逆信号±cosωStとの乗算出力V1
(t),V2(t)は、メイン信号をM(t)、サブ信
号をS(t)として整理すれば、 V1(t)=1/2S(t)+M(t)cosωSt +1/2S(t)cos2ωSt ……(2) V2(t)=−1/2S(t)−M(t)cosωSt −1/2S(t)cos2ωSt ……(3) となる。従つて、抵抗器5,6によりコンポジツ
ト信号V(t)を1/2に減衰せしめて加算器3,4 にて(2),(3)式で示される乗算出力とそれぞれ加算
すれば、各加算器3,4の出力における低周波数
成分(オーデイオ成分)VA1(t),VA2(t)は、 VA1(t)=1/2S(t)+1/2M(t)=L(
t) ……(4) VA2(t)=−1/2S(t)+1/2M(t)=R
(t) ……(5) となり、左右チヤンネル信号が夫々分離されるこ
とになる。
In such a configuration, the composite signal V(t)
is expressed as: V(t)=L(t)+R(t)+ {L(t)−R(t)}cosω S t (1). Here, L(t) and R(t) are left and right channel signals, and ω S is the angular frequency of the subcarrier signal. The product output V 1 of this signal V(t) and the positive/inverse signal ±cosω S t of the subcarrier signal is
(t), V 2 (t) are arranged as M(t) for the main signal and S(t) for the sub signal, then V 1 (t) = 1/2S(t) + M(t) cosω S t +1/2S(t)cos2ωS t ...(2) V 2 (t)=-1/2S(t)-M(t) cosωS t -1/2S(t)cos2ωS t ...(3) becomes. Therefore, if the composite signal V(t) is attenuated to 1/2 by resistors 5 and 6 and added to the multiplication outputs shown by equations (2) and (3) by adders 3 and 4, each The low frequency components (audio components) V A1 (t) and V A2 (t) in the outputs of adders 3 and 4 are as follows: V A1 (t) = 1/2S (t) + 1/2M (t) = L(
t) ...(4) V A2 (t)=-1/2S(t)+1/2M(t)=R
(t) ...(5) Thus, the left and right channel signals are separated.

第2図及び第3図は上述した乗算方式による復
調回路の具体例を示す回路図であり、共に38KHz
の正弦波状サブキヤリヤ信号を(1)式で示されるコ
ンポジツト信号の周波数スペクトラムを有するパ
ルス列信号によりスイツチングして乗算をなすい
わゆるスイツチング方式によるマルチプレツクス
ステレオ復調回路の例である。両図において第1
図と同等部分は同一符号により示されている。
Figures 2 and 3 are circuit diagrams showing specific examples of the demodulation circuit using the multiplication method described above, and both are 38KHz.
This is an example of a multiplex stereo demodulation circuit using a so-called switching method in which a sinusoidal subcarrier signal is switched and multiplied by a pulse train signal having a frequency spectrum of a composite signal expressed by equation (1). In both figures, the first
Parts equivalent to those in the figures are designated by the same reference numerals.

先ず、第2図を参照すれば、コンポジツト信号
としてFM信号をパルスカウント検波方式により
検波して得られるパルス列信号が用いられてお
り、これがアナログスイツチング素子7,8をオ
ンオフ制御する制御信号となつている。またこの
パルス列信号の逆相信号がアナログスイツチング
素子9,10をオンオフ制御する。サブキヤリヤ
信号の正相信号は抵抗11及び12を介し更には
スイツチング素子7及び10を介して加算器3,
4の1入力となつている。一方、サブキヤリヤ信
号の逆相信号は抵抗13及び14を介し更にはス
イツチング素子9及び8を介して加算器3,4の
1入力となる。
First, referring to FIG. 2, a pulse train signal obtained by detecting an FM signal using a pulse count detection method is used as a composite signal, and this becomes a control signal for controlling the analog switching elements 7 and 8 on and off. ing. Further, the reverse phase signal of this pulse train signal controls on/off of the analog switching elements 9 and 10. The positive phase signal of the subcarrier signal is passed through resistors 11 and 12 and further through switching elements 7 and 10 to the adder 3,
It is one input of 4. On the other hand, the negative phase signal of the subcarrier signal becomes one input of adders 3 and 4 via resistors 13 and 14 and further via switching elements 9 and 8.

各スイツチング素子7〜10は制御入力が高レ
ベルのときオンで、低レベルのときオフとなるよ
うにすれば、スイツチング素子7及び9の出力の
合成信号すなわち乗算器1の出力には(2)式で示す
ようにサブ信号S(t)の正相成分が得られる。
また、スイツチング素子8及び10の出力の合成
信号すなわち乗算器2の出力には(3)式で示すよう
にサブ信号の逆相成分が得られる。
If each switching element 7 to 10 is set to be on when the control input is high level and off when the control input is low level, the composite signal of the outputs of switching elements 7 and 9, that is, the output of multiplier 1 will be (2). As shown in the equation, the positive phase component of the sub-signal S(t) is obtained.
Further, as a composite signal of the outputs of the switching elements 8 and 10, that is, an output of the multiplier 2, an opposite phase component of the sub-signal is obtained as shown in equation (3).

加算器3,4はオペアンプ15,16及び抵抗
17,18よりなつており、各乗算出力±S(t)
とコンポジツト信号のメイン信号成分M(t)と
の加算が行われて左右チヤンネル信号がそれぞれ
得られる。
Adders 3 and 4 consist of operational amplifiers 15 and 16 and resistors 17 and 18, and each multiplication output ±S(t)
and the main signal component M(t) of the composite signal are added to obtain left and right channel signals, respectively.

かゝる回路において、モノラル時にはサブキヤ
リヤ信号がなくなるから、サブキヤリヤ信号端子
は接地状態にあるが、各スイツチング素子7〜1
0はコンポジツト信号(この場合はモノラルであ
るからメイン信号のみである)によりオンオフ動
作している。従つて、各スイツチング素子のオン
状態においては各加算器の入力と接地間に第4図
に示すように各抵抗11〜14Rgが等価的に挿
入されたことになる。一般に、増幅器における入
力と接地間に等価的に挿入される信号源抵抗Rg
は大なる程、増幅器の雑音指数は良好となる事実
よりすれば、第2図の回路ではモノラル時にスイ
ツチング素子のオン動作時における信号源抵抗に
よる雑音が大となつてS/Nの劣化を招来する。
尚、第4図において、OPは加算器のオペアンプ
を、Rfは帰還抵抗をそれぞれ示している。
In such a circuit, since there is no subcarrier signal when monaural, the subcarrier signal terminal is in a grounded state, but each switching element 7 to 1
0 is turned on and off by a composite signal (in this case, since it is monaural, it is only the main signal). Therefore, when each switching element is in the ON state, each of the resistors 11 to 14Rg is equivalently inserted between the input of each adder and the ground, as shown in FIG. In general, a signal source resistance Rg equivalently inserted between the input and ground in an amplifier
Considering the fact that the larger the value, the better the noise figure of the amplifier is, in the circuit shown in Figure 2, the noise due to the signal source resistance when the switching element is turned on during monaural operation becomes large, leading to deterioration of the S/N ratio. do.
In FIG. 4, OP indicates an operational amplifier of the adder, and Rf indicates a feedback resistor.

第3図の回路においては、サブキヤリヤ信号の
正相成分を抵抗13a,13b及び14a,14
bを介して加算器3及び4の各1入力とし、抵抗
13a,13b及び14a,14bの各接続点と
接地間にスイツチング素子9及び8を夫々挿入し
ており、これらスイツチング素子8及び9をパル
スカウント検波方式により得られたパルス列信号
の正及び逆相信号によりそれぞれオンオフ制御し
ている。また、サブキヤリヤ信号の逆相成分を抵
抗11a,11b及び12a,12bを介して加
算器3及び4の各1入力とし、抵抗11a,11
b及び12a,12bの各接続点と接地間にスイ
ツチング素子7及び10を夫々挿入し、これらス
イツチング素子7及び10をパルス列信号の正及
び逆相信号によりそれぞれオンオフ制御してい
る。他の構成は第2図の回路のそれと同一となつ
ている。
In the circuit of FIG. 3, the positive phase component of the subcarrier signal is connected to resistors 13a, 13b and 14a, 14.
One input each of adders 3 and 4 is provided through the adders 3 and 4, and switching elements 9 and 8 are inserted between the connection points of the resistors 13a, 13b and 14a, 14b and the ground, respectively. On/off control is performed by the positive and negative phase signals of the pulse train signal obtained by the pulse count detection method. Further, the opposite phase component of the subcarrier signal is input to each of adders 3 and 4 via resistors 11a, 11b and 12a, 12b, and resistors 11a, 11
Switching elements 7 and 10 are respectively inserted between the connection points of 12a and 12b and the ground, and these switching elements 7 and 10 are controlled on and off by the positive and negative phase signals of the pulse train signal, respectively. The other configuration is the same as that of the circuit shown in FIG.

こうすることにより、第2図の例と同様に加算
器3及び4の出力から左右チヤンネル信号が分離
されて復調がなされるが、本例でもモノラル時に
おいて各スイツチング素子がオンとなれば、加算
器の入力と接地間に抵抗11b〜14bが夫々挿
入されて、第4図の信号源抵抗Rgが等価的に小
となりやはりS/Nの劣化となる。
By doing this, the left and right channel signals are separated from the outputs of adders 3 and 4 and demodulated as in the example shown in FIG. Resistors 11b to 14b are inserted between the input of the device and the ground, respectively, and the signal source resistance Rg shown in FIG. 4 becomes equivalently small, resulting in a deterioration of the S/N ratio.

本発明の目的はスイツチングによる乗算方式に
よりステレオ復調をなす場合モノラル時における
S/Nの劣化を防止するようにした復調回路を提
供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a demodulation circuit which prevents deterioration of S/N when monaural when performing stereo demodulation using a multiplication method using switching.

本発明によるステレオ復調回路は、FM検波信
号であるコンポジツト信号の周波数スペクトラム
を含むパルス列信号によりスイツチング素子をオ
ンオフ制御してサブキヤリヤ信号をスイツチング
しパルス列信号とサブキヤリヤ信号との乗算出力
を得てこの乗算出力とコンポジツト信号とを所定
比にて加算することによつて左右チヤンネル信号
を夫々分離出力するようにしたステレオ復調回路
であり、その特徴とするところはモノラル時にス
イツチング素子をオフ状態に制御するようにした
ことにある。 以下に本発明を図面により説明す
る。
The stereo demodulation circuit according to the present invention switches a subcarrier signal by controlling a switching element on and off using a pulse train signal that includes the frequency spectrum of a composite signal, which is an FM detection signal, and obtains a multiplication output of the pulse train signal and the subcarrier signal. This is a stereo demodulation circuit that separates and outputs the left and right channel signals by adding the left and right channel signals at a predetermined ratio.The main feature of this circuit is that it controls the switching element to be in the OFF state when monaural. It's what I did. The present invention will be explained below with reference to the drawings.

第5図は本発明の一実施例の回路図であり、第
2図の従来例に本発明を適用したものであつて両
図において同等部分は同一符号により示されてい
る。第2図と異なる部分についてのみ述べれば、
FM検波信号であるコンポジツト信号の周波数ス
ペクトラムを有するパルス列信号は、2つの縦続
接続されたノアゲート19,20を介して正相信
号となり、スイツチング素子7及び8のオンオフ
制御信号となる。また、ノアゲート19の出力か
ら逆相信号が得られて、これがスイツチング素子
9及び10のオンオフ制御信号となつている。両
ノアゲート19,20の各他入力にはモノラル、
ステレオモードに応じて切換わるスイツチ21の
切換出力が印加されており、モノラル時には高レ
ベル信号が、またステレオ時には低レベル信号が
夫々印加されるようになつている。このスイツチ
21としては、FM検波出力中に含まれる19KHz
のステレオパイロツト信号の有無を検知して自動
的に制御される方式の電子スイツチである。他の
構成は第2図の回路と同一となつている。
FIG. 5 is a circuit diagram of an embodiment of the present invention, in which the present invention is applied to the conventional example shown in FIG. 2, and equivalent parts in both figures are designated by the same reference numerals. If we only mention the parts that differ from Figure 2,
A pulse train signal having a frequency spectrum of a composite signal, which is an FM detection signal, becomes a positive phase signal through two cascaded NOR gates 19 and 20, and becomes an on/off control signal for switching elements 7 and 8. Further, a negative phase signal is obtained from the output of the NOR gate 19, and this serves as an on/off control signal for the switching elements 9 and 10. The other inputs of both NOR gates 19 and 20 are monaural,
A switching output from a switch 21 that changes depending on the stereo mode is applied, and a high level signal is applied when monaural, and a low level signal is applied when stereo. This switch 21 uses the 19KHz included in the FM detection output.
This is an electronic switch that is automatically controlled by detecting the presence or absence of a stereo pilot signal. The other configurations are the same as the circuit shown in FIG.

こうすることにより、ステレオモードにあつて
は、ノアゲート19,20の各他入力が共に低レ
ベルにあるから、両ノアゲートは共にインバータ
として動作する。従つて、第2図の回路と全く同
等の動作を行つて左右チヤンネル信号が夫々分離
して導出される。
By doing this, in the stereo mode, since the other inputs of the NOR gates 19 and 20 are both at a low level, both NOR gates operate as an inverter. Therefore, the left and right channel signals are separately derived by performing the same operation as the circuit shown in FIG.

一方、モノラルモードになると、ノアゲート1
9,20の各他入力は高レベルとなるから、両ゲ
ートは閉となり、その出力は共に低レベルにクラ
ンプされることになる。従つて、この低レベル信
号によりすべてのスイツチング素子7〜10がオ
フとなるように制御されるから、各加算器3,4
の入力から各乗算器1,2を見た信号源インピー
ダンスは略無限大となる。これは、第4図の抵抗
Rgが無限大になつたことを意味し、よつてモノ
ラル時に抵抗11〜14による雑音の増大はなく
なり、S/N劣化が防止される。
On the other hand, in monaural mode, Noah Gate 1
Since each of the other inputs 9 and 20 will be at a high level, both gates will be closed and their outputs will both be clamped at a low level. Therefore, since all the switching elements 7 to 10 are controlled to be turned off by this low level signal, each adder 3, 4
The signal source impedance seen from the input of each multiplier 1 and 2 is approximately infinite. This is the resistance in Figure 4.
This means that Rg has become infinite, and therefore the increase in noise due to the resistors 11 to 14 during monaural recording is eliminated, and S/N deterioration is prevented.

第6図は本発明の他の実施例の回路図であり、
第3図の従来例に本発明を適用したものである。
第6図において第3図及び第5図と同等部分は同
一符号により示されている。第3図と異なる部分
についてのみ述べれば、コンポジツト信号成分を
有するパルス列信号は縦続接続された2つのノア
ゲート19,20を介して正相信号となり、スイ
ツチング素子7及び8のオンオフ制御信号とな
り、また、ノアゲート19の出力から逆相信号が
得られてこれがスイツチング素子9及び10のオ
ンオフ制御信号となる。両ノアゲート19,20
の各他入力にはスイツチ21の切換出力が印加さ
れており、ステレオモード時には低レベルの信号
がノアゲート19,20に印加されるから、両ゲ
ートは共にインバータとして動作し、よつて第3
図と同様の動作をなし左右チヤンネル分離が可能
となる。
FIG. 6 is a circuit diagram of another embodiment of the present invention,
The present invention is applied to the conventional example shown in FIG.
In FIG. 6, parts equivalent to those in FIGS. 3 and 5 are designated by the same reference numerals. To describe only the parts that are different from FIG. 3, the pulse train signal having a composite signal component becomes a positive phase signal through two cascade-connected NOR gates 19 and 20, and becomes an on/off control signal for switching elements 7 and 8. A negative phase signal is obtained from the output of the NOR gate 19, and this becomes an on/off control signal for the switching elements 9 and 10. Both Noah Gates 19, 20
Since the switching output of the switch 21 is applied to each other input of the switch 21, and a low level signal is applied to the NOR gates 19 and 20 in the stereo mode, both gates operate as an inverter, and therefore the third
The operation is similar to that shown in the figure, and left and right channels can be separated.

モノラルモード時には、ノアゲート19,20
の各入力は高レベルであるから、両ゲートは閉と
なつてその出力は共に低レベルになる。従つて、
スイツチング素子7〜10はすべてオフ状態とな
るから、各加算器3,4の入力から各乗算器1,
2を見た信号源インピーダンスは抵抗11a,1
1bの和、12a,12bの和、13a,13b
の和、14a,14bの和となる。これは第3図
の回路の場合の抵抗11b,12b,13b及び
14bによる信号源インピーダンスに比しより大
となり、S/Nの改善が可能となる。
In monaural mode, Noah Gate 19, 20
Since each input of is high, both gates are closed and their outputs are both low. Therefore,
Since all switching elements 7 to 10 are in the off state, the inputs of each adder 3 and 4 are connected to each multiplier 1,
2, the signal source impedance is resistor 11a, 1
Sum of 1b, sum of 12a, 12b, 13a, 13b
, and the sum of 14a and 14b. This is larger than the signal source impedance due to the resistors 11b, 12b, 13b, and 14b in the case of the circuit shown in FIG. 3, and the S/N ratio can be improved.

このように、本発明によれば極めて簡単な構成
でモノラル時の抵抗雑音を抑圧することが可能と
なるのでS/Nの良好なステレオ復調回路が得ら
れる。
As described above, according to the present invention, it is possible to suppress resistance noise during monaural sound with an extremely simple configuration, so that a stereo demodulation circuit with a good S/N ratio can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は乗算方式によるステレオ復調回路の原
理を説明するブロツク図、第2図及び第3図は従
来のステレオ復調回路の具体例を示す図、第4図
は第2,3図の回路のモノラル時における各スイ
ツチングのオン時の加算器入力からみた信号源イ
ンピーダンスを説明する等価回路図、第5図及び
第6図は本発明の各実施例の回路図である。 主要部分の符号の説明、1,2……乗算器、
3,4……加算器、7〜10……スイツチング素
子、19,20……ノアゲート、21……モード
スイツチ。
Figure 1 is a block diagram explaining the principle of a stereo demodulation circuit using the multiplication method, Figures 2 and 3 are diagrams showing specific examples of conventional stereo demodulation circuits, and Figure 4 is a block diagram of the circuit shown in Figures 2 and 3. FIGS. 5 and 6 are equivalent circuit diagrams illustrating the signal source impedance seen from the adder input when each switching is on in monaural mode, and are circuit diagrams of each embodiment of the present invention. Explanation of the signs of the main parts, 1, 2...multiplier,
3, 4... Adder, 7 to 10... Switching element, 19, 20... Noah gate, 21... Mode switch.

Claims (1)

【特許請求の範囲】[Claims] 1 FM検波信号であるコンポジツト信号の周波
数スペクトラムを含むパルス列信号によりスイツ
チング素子をオンオフ制御してサブキヤリヤ信号
をスイツチングし前記パルス列信号と前記サブキ
ヤリヤ信号との乗算出力を得てこの乗算出力と前
記コンポジツト信号とを所定比にて加算すること
により左右チヤンネル信号をそれぞれ分離出力す
るようにしたステレオ復調回路であつて、モノラ
ル時に前記スイツチング素子をオフ状態に制御す
る手段を含むことを特徴とするステレオ復調回
路。
1. A switching element is controlled on/off by a pulse train signal including the frequency spectrum of a composite signal, which is an FM detection signal, to switch a subcarrier signal, and a multiplication output of the pulse train signal and the subcarrier signal is obtained, and this multiplication output and the composite signal are combined. A stereo demodulation circuit configured to separate and output left and right channel signals by adding them at a predetermined ratio, the stereo demodulation circuit comprising means for controlling the switching element to an off state when monaural.
JP9445481A 1981-06-18 1981-06-18 Stereo demodulation circuit Granted JPS57208745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9445481A JPS57208745A (en) 1981-06-18 1981-06-18 Stereo demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9445481A JPS57208745A (en) 1981-06-18 1981-06-18 Stereo demodulation circuit

Publications (2)

Publication Number Publication Date
JPS57208745A JPS57208745A (en) 1982-12-21
JPH031855B2 true JPH031855B2 (en) 1991-01-11

Family

ID=14110706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9445481A Granted JPS57208745A (en) 1981-06-18 1981-06-18 Stereo demodulation circuit

Country Status (1)

Country Link
JP (1) JPS57208745A (en)

Also Published As

Publication number Publication date
JPS57208745A (en) 1982-12-21

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