JPH0318767B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to a gain control circuit, and more particularly to a bias circuit of a gain control circuit that controls the output level of a demodulated signal by changing the gain of an amplifier according to the input signal strength in an FM tuner. . [Prior Art] A conventional bias circuit of this type will be explained with reference to FIG. Stabilized voltage terminal 2 is connected to transistor 12
The emitter of this transistor 12 is connected to voltage application current output type rectifier circuits 46, 47, 48.
It is connected to the. The rectifier circuits 46, 47, and 48 have transistors 16, 17, and 18, respectively, and the emitter of the transistor 12 is connected to the collectors of these transistors. The emitters of transistors 16, 17, and 18 are connected via resistors 33, 34, and 35, respectively.
These bases are connected to the second power supply terminal 4, respectively.
25 and is connected to the other stabilized voltage terminal 3 via diodes 28 and 27. The collector of the transistor 12 is connected to the first power supply terminal 1 via a resistor 30, and is further connected to a constant current source 9 for supplying bias current to the rectifier circuits 46, 47, and 48. Furthermore, it is connected via a resistor 31 to the input signal strength detection terminal 6 and to the base of a transistor 14 whose collector is connected to the first power supply terminal 1 . The emitter of the transistor 14 is connected to the second power supply terminal 4 via a resistor 38,
Furthermore, two of the transistors 19 and 20 constituting the differential amplifier are connected through the resistor 42.
Connected to the base of 0. A collector of the transistor 20 is connected to the first power supply terminal 1. The collector of the other transistor 19 constituting the differential amplifier is connected to the demodulation output terminal 7 and also to the power supply terminal 1 via a resistor 41. The emitters of transistors 19 and 20 are commonly connected to current source 10. The current source 10 replaces the demodulated signal with a current. The stabilized voltage terminal 2 is further connected to the base of a transistor 13 whose collector is connected to the first power supply terminal 1 . The emitter of the transistor 13 is connected to resistors 36 and 37 and a plurality of (n) diodes 29.
is connected to the second power supply terminal 4 through the resistor 3.
The connection point between 6 and 37 is connected via a resistor 43 to the base of a transistor 19 that constitutes a differential amplifier. A power supply voltage is applied to the first power supply terminal 1, and a power supply voltage is applied to the first power supply terminal 1.
It is preferable to supply a ground potential to the power supply terminals of the respective power supply terminals. Diode 23-24, 25-26, 27-2
8 At each connection point, the output of the intermediate frequency amplifier is connected to terminal 5.
Input via . Therefore, each rectifier circuit 4
6, 47, and 48 rectify the intermediate frequency signal and output it as a current output to the resistor 30 serving as a load via the transistor 12. The signal appearing at the resistor 30 is smoothed by the resistor 31 and the capacitor 44, and is output to the input signal strength detection terminal 6 to drive the signal strength display device. The smoothed output is further supplied to the base of one transistor 20 constituting the differential amplifier via an emitter follower made up of a transistor 14 and a resistor 38. Since the current source 10 converts a demodulated signal into a current, a demodulated signal corresponding to the electric field strength can be obtained from the terminal 7. That is, the circuit shown in FIG. 1 controls the demodulated signal level using the field strength display signal. In the circuit shown in FIG. 1, if the voltages at terminal 6 and the bases of transistors 19 and 20 when there is no signal are V ₆ , V ₁₉ , and V ₂₀ , respectively, the respective voltages V ₆ , V ₁₉ ,
V ₂₀ are shown below, respectively. V ₆ =V _cc −R ₃₀ ×I ₉ −(I ₄₆ +gm ₄₆・v ₄₆ ) −(I ₄₇ G＋gm ₄₇・v ₄₇ ) −(I ₄₈ +gm ₄₈・v ₄₈ ) =V _cc −R ₃₀ [(I ₉ −(I ₄₆ +I ₄₇ +I ₄₈ )] −R ₃₀ [gm ₄₆・v ₄₆ +gm ₄₇・v ₄₇ +gmv ₄₈ ] …(1) V ₂₀ =V ₆ −V _BE …(2) V ₁₉ =( V ₂ −V _BE )・R ₃₇ +nV _BE・R ₃₆ /R ₃₆ +R ₃₇ …(3) However, gm ₄₆ , gm ₄₇ , gm ₄₈ : Rectifier circuit 46, 47, 48
Mutual conductance I ₄₆ , I ₄₇ , I ₄₈ : Bias current I ₉ of rectifier circuits 46, 47, 48 : Constant current value of constant current source 9 R ₃₆ , R ₃₈ : Resistance value of resistors 36, 37 n: Diode 29 Number of V ₄₆ , V ₄₇ , V ₄₈ : Input voltage of current circuits 46, 47, 48 V ₂ : Voltage of stabilized voltage terminal V ₂ Therefore, demodulated output level of the differential amplifier made up of transistors 19 and 20 V ₇ is v ₇ = R ₄₁ i ₁₀ /1 + l _xp (V ₂₀ −V ₁₉ /V _T )...(4) However, R ₄₁ : Resistor 41 i ₁₀ : Demodulation signal source current value V _T = KT/q Usually, transistor 19 , 20 base voltage difference
When V ₂₀ −V ₁₉ is constant, the demodulation level v ₇ is
Since it is designed to be constant against variations in R ₄₁ , i ₁₀ , and V _T , (V ₂₀ −V ₁₉ ) in equation (4)
It is necessary to reduce the variation in On the other hand, the base bias voltage difference between transistors 19 and 20 is V ₂₀ −
From equations (2) and (3), V ₁₉ is calculated as follows: V ₂₀ −V ₁₉ = V _cc n(1+R ₃₆ )/R ₃₆ +R ₃₇ V _BE −R ₃₇ /R _3
6 +R ₃₇ V ₂ −R ₃₀ [gm ₄₆・v ₄₆ +gm ₄₇ +gm ₄₈ ×v ₄₈ ] −R ₃₀ [I ₉ − (I ₄₆ + I ₄₇ + I ₄₈ )] …(5) Therefore, temperature compensation and resistance by diode It has been extremely difficult to compensate for variations in [Object of the Invention] An object of the present invention is to provide a gain control circuit that allows easy base bias setting and has a simpler circuit configuration than conventional ones. [Structure of the Invention] The present invention has a signal level detection circuit that outputs a DC output proportional to the signal level of an AC input, and a bias circuit that has a symmetrical circuit configuration, and detects a DC voltage based on the outputs of these two circuits. The feature is that the differential amplifier is biased with. [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. Incidentally, the same constituent elements as in FIG. 1 are indicated by the same numbers, and their explanation will be omitted. In the present invention, a bias circuit 45 having the same configuration (symmetrical configuration) as the rectifier circuits 46 to 48 is provided.
The bias circuit 45 includes a constant current circuit 8 as a collector.
A bias current is supplied through a transistor 11 connected to the first power supply terminal 1 through the transistor 11 .
The base of transistor 11 is connected to stabilized voltage terminal 2, and its emitter is connected via resistor 49 to the collector of transistor 15 in bias circuit 45. The emitter of the transistor 15 is connected to the second power supply terminal 4 via a resistor 32,
Its base is connected via diodes 22, 21 to another stabilized voltage terminal 3. resistance 49
The connection point between and the collector of the transistor 15 becomes the bias voltage output terminal, and the bias voltage is applied to the resistor 43.
is supplied to the base of one transistor 19 constituting the differential amplifier. transistor 12
A resistor 50 is connected between the rectifying circuit 46 and each of the rectifying circuits 46 to 48. Resistor 50 and each rectifier circuit 46 to 48
The connection point between the two is connected to the second power supply terminal 4 via a resistor 42 and a capacitor 44. resistance 42
The connection point between the capacitor 44 and the capacitor 44 is connected to the base of the other transistor 20 constituting the differential amplifier. The connection point between the resistor 30 and the transistor 12 is directly connected to the signal output terminal 6 for signal strength display. The output of the intermediate frequency amplifier is input to rectifier circuits 46, 47, and 48 from terminal 5, respectively, and rectified. The output currents are added together and appear as a voltage across resistor 50 and resistor 30, respectively. resistance 5
The voltage output across the terminal 0 is smoothed by a resistor 42 and a capacitor 44 and input to the base of the transistor 20 in the differential amplifier.
A bias voltage from a bias circuit 19 is applied to the base of 9. Since the current source 10 converts the demodulated signal into a current, the demodulated signal level is controlled according to the electric field strength. Further, a signal for displaying signal strength is obtained from the terminal 6. Here, if the voltage at the terminal 6 is V ₆ and the base input voltages of the transistors 19 and 20 forming the differential amplifier are V ₁₉ and V ₂₀ , then using the above-mentioned constants, V ₆ = V _cc - R ₃₀ I ₉ − (I ₄₆ + gm ₄₆・v ₄₆ ) − (I ₄₇ + gm ₄₇・v ₄₇ ) − (I ₄₈ + gm ₄₈・v ₄₈ ) = V _cc −R ₃₀ (I ₉ − I ₄₆ − I ₄₇ − I ₄₈ ] −R ₃₀・(gm ₄₆・v ₄₆ +gm ₄₇・v ₄₇ +gm ₄₈ v ₄₈ ) V ₁₉ ≒V ₂ −V _BE −R ₄₉・I ₄₅ V ₂₀ ≒V ₂ −V _BE R ₅₀ +I ₄₆ +gm ₄₆・v ₄₆ +I ₄₇ +gm ₄₇・v ₄₇
+I ₄₈ +gm ₄₈・v ₄₈ =V ₂ −V _BE −R ₅₀ (I ₄₆ +I ₄₇ +I ₄₈ )−R ₅₀ (gm ₄₆・v ₄₆ +gm ₄₇ +
v ₄₇ +gm ₄₈・v ₄₈ )…(8). However, I ₄₅ is the current flowing through the bias circuit 45, and R ₄₉ is the resistance of the resistor 49. Therefore, the base voltage difference between transistors 19 and 20 is V ₂₀ −V ₁₉ =R ₄₉・I ₄₅ −R ₅₀ (I ₄₆ +I ₄₇ +I ₄₈ )−R ₅₀ (gm ₄₆ v ₄₆ +
gm ₄₇・v ₄₇ +gm ₄₈ v ₄₈ )…(9) In equation (9), if R ₄₉・I ₄₅ = R ₅₀ (I ₄₆ +I ₄₇ +I ₄₈ )…(10), then V ₂₀ − V ₁₉ = −R ₅₀ (gm ₄₆・v ₄₆ +gm ₄₇ +v ₄₇ +gm ₄₈・v ₄₈
)…(11) becomes. As is clear from comparing equations (5) and (11), according to this circuit, factors such as the bias current of each rectifier circuit and the stabilizing voltage (voltage at terminal 2) are included in the base voltage difference. It can be seen that it has been removed and does not depend on these. In other words, in the rectifier circuits 46 to 48,
R ₅₀・gm ₄₆ , R ₅₀・gm ₄₇ , and R ₅₀・gm ₄₈ can be designed so that they always remain constant despite resistance variations and temperature changes, and they are proportional to the output voltage of the intermediate frequency amplifier. , it is possible to stably and easily control the demodulated output signal voltage gain. The relationship shown in equation (10) is that transistors 15, 16, 17, 1
Emitter area ratio of 8 and resistance 32, 33, 34,
This can be easily achieved by adjusting the relative ratios of resistors 49 and 50, and obtaining accurate emitter area ratios and resistor relative ratios is a specialty of integrated circuits. As described above, according to the present invention, it is possible to provide a circuit that is stable, has a simple circuit configuration, has a small number of elements, and can be integrated into an IC. Although the above embodiment shows a three-stage rectifier circuit, the number of stages is of course not limited to this.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1 is a first power supply terminal, 2 and 3 are stabilized voltage terminals, 4 is a second power supply terminal, 5 is an output level input terminal for intermediate frequency amplification, 6 is an input signal strength detection terminal, and 7 is a demodulated signal output terminal. , 8, 9, 10 are constant current sources, 11-20 are transistors, 21-29 are diodes, 30-43, 49, 50 are resistors, 4
4 is a capacitor, 46 to 48 are rectifier circuits, and 45 is a bias circuit.

Claims (1)

[Scope of Claims] 1. A rectifier circuit that receives an alternating current signal, rectifies the signal, and generates the rectified current together with a bias current as an output current, and converts the output current from the rectifier circuit into a voltage to generate a signal of the alternating current signal. A gain comprising a signal level detection circuit including circuit means for generating a DC voltage according to the level, and a circuit for controlling the signal level of another AC signal according to the DC voltage from the signal level detection circuit and a reference voltage. The control circuit includes a circuit that has the same circuit configuration as the rectifier circuit and generates a bias current according to the bias current of the rectifier circuit, and a circuit that converts the bias current from this circuit into a voltage to generate the reference voltage. A gain control circuit characterized in that it is provided with a circuit. 2. The gain control circuit according to claim 1, wherein the AC signal is an intermediate frequency signal, and the other AC signal is a demodulated signal.