JPH0320108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device that reads out optical information stored in a photoelectric conversion element formed on a semiconductor substrate, and particularly to a fixed-state imaging device that suppresses fixed pattern noise.

FIG. 1 shows an example of a conventional solid-state imaging device. 1 and 2 are horizontal and vertical scanning circuits, respectively.
Normally, by applying 2- to 4-phase clock pulses CP _H , CP _V and start pulses SP _H , SP _V ,
Horizontal and vertical scanning circuits 1 and 2 respectively receive horizontal scanning pulses H ₁ , H ₂ ,...H _o and vertical scanning pulses V ₁ , V ₂ ,
..., V _n are output to the output lines of each stage of the scanning circuit. Vertical scanning pulses sequentially open and close vertical MOS switches 6, and horizontal scanning pulses sequentially open and close horizontal MOS switches 7. As a result, signals from each photoelectric conversion element 3 are sequentially read out to the vertical signal line 4 and the horizontal signal line 5. Since the signal from the photoelectric conversion element 3 corresponds to the optical image projected thereon, the video signal can be extracted by the above operation. In FIG. 1, 8 is a signal output terminal, 11 is a constant voltage source, and 12 is a resistor.

Figure 2 shows vertical scanning pulse V _n and horizontal scanning pulse.
A structural diagram focusing on a path for reading optical information from a photoelectric conversion element selected by H _o is shown. In the figure, 1
3 is an insulating oxide film, 14 and 15 are gate electrodes, 16
is a p-type well, 17, 18, 19 are n-type diffusion layers,
20 is an n-type substrate, and 21 and 22 are constant voltage sources.
n-type diffusion layer 17, p-type well 16, n-type substrate 20
A photoelectric conversion section is formed. n-type diffusion layer 17
It has a three-layer structure consisting of a HP diode (photodiode) in the p-type well 16 and an n-type substrate 20, and a bias _E1 is applied to the p-type well 16 by a constant voltage source 22, which will be described later. When reading optical information accumulated in the photoelectric conversion element, gate 1
This is done by opening two MOS switches consisting of 4, 15 and n-type diffusion layers 17, 18 and 19.

After optical information is read out from the photoelectric conversion section (hereinafter abbreviated as mn photodiode) shown in Fig. 2,
Optical information from other photoelectric conversion units is sequentially read out. Then, until the mn photodiode is read out again, the mn photodiode is in the signal accumulation mode, and electrons proportional to the amount of incident light are accumulated in the capacitance of the n-type diffusion layer 17. The accumulated electrons are read out during the next readout. Normally, the above cycle is repeated, but when strong light is incident on the photodiode, a large amount of electrons is accumulated,
Excess electrons overflow and a so-called blooming phenomenon occurs.

In order to suppress this blooming, a constant potential E ₁ is applied to the p-type well 16 from a constant voltage source 22 as shown in FIG. 2 with respect to the ground. That is, the photoelectric conversion section with the npn structure shown in FIG. 2 has a transistor structure, and when a potential E ₁ is applied to the p-type well 16 corresponding to its gate, the potential of the n-type diffusion layer 17 becomes E ₁ −V _BE (V _BE : the base of the transistor 23;
When the voltage is about to drop below (the emitter voltage), the transistor 23 becomes conductive, and electrons flow from the n-type diffusion layer 17 to the n-type substrate 20. That is, E ₁
By setting =V _BE , excess electrons that cause blooming flow to the n-type substrate 20, and blooming no longer occurs.

On the other hand, the optical information accumulated in the photoelectric conversion section is transferred to the MOS
In the solid-state imaging device having the configuration shown in FIG. 1, in which reading is performed by a signal transfer section including a switch, noise called fixed pattern noise (hereinafter abbreviated as FPN) occurs.

Below, we will explain how FPN occurs.

FIGS. 3a to 3d show potential relationships of various parts of the signal readout system, and FIG. 3e shows a circuit diagram. FIG. 5e shows a signal readout circuit focusing on an arbitrary photoelectric conversion element in FIG.

When the horizontal MOS switch 7 becomes conductive in order to transfer the signal charge transferred to the vertical signal line 4 to the horizontal signal line 5, an inversion layer charge 51 is induced under the gate as shown in FIG. As a result, an upward spike noise 40 shown in FIG. 4 is generated. Next, when the horizontal MOS switch 7 becomes non-conductive, downward spike noise 41 shown in FIG. 4 is generated.

Subsequently, by sequentially reading out the signal charges of other photoelectric conversion elements, a continuous output waveform shown in FIG. 4 is obtained at the output terminal 8. This spike noise 4
0 to 47 are generally much larger than signal 50, as shown in FIG. But each horizontal
If the spike noises generated by the MOS switch 7 are exactly the same, the spike noises can be removed by signal processing using a low-pass filter in the subsequent stage. However, in reality, each horizontal
The spike noise generated by the MOS switch 7 fluctuates, and FPN occurs due to the fluctuation.

In order to suppress this FPN, an integration method has been devised that integrates and cancels the upper and lower spike noises (40 and 41, 42 and 43, etc.). The FPN is suppressed by the integration method, but the spike noise cancels it out.
For example, if 40 and 41 in FIG. 4 are different, a DC component remains, and if this DC component varies among the horizontal MOS switches 7, it becomes FPN. The cause of this DC component is the charge pumping current described below.
This is emphasized by applying a bias potential E ₁ to the p-well.

The charge pumping current will be explained with reference to FIG.
Figure a shows the horizontal scanning pulse H, T ₁ , T ₂ , T ₃
represent the rise time, high level time, and fall time, respectively. Further, b, c, and d of the same figure show the state under the gate of the horizontal switch MOS 7 at each timing of T ₁ , T ₂ , and T ₃ , respectively.
At the rise time _T1 , electrons begin to collect under the gate and a channel begins to form, as shown in FIG. At T ₂ , the channel is completely formed, as shown in c.
Next, when the horizontal scanning pulse falls at _T3 , as shown in d, the electrons forming the channel are pushed toward the source and drain, and at the same time are pushed toward the substrate. At this time p-well 1
When the bias E ₁ is applied to 6, the low level of the horizontal traveling pulse H is relatively lowered, and the electrons pushed toward the substrate 20 are attracted to the substrate 20 rather than the source and drain. That is, a DC power source is connected to the source or drain, and the spike noises shown in the upper and lower portions of FIG. 4 are no longer equal.

As is clear from the above description, in the conventional solid-state imaging device, blooming can be suppressed by applying bias E ₁ to the p-well, but when FPN is suppressed by the integral method, a DC component is generated due to charge pumping. This DC component is
The drawback was that FPN caused by charge pumping occurred due to variations in the MOS switch.

The above conventional example is explained using a solid-state imaging device having a photoelectric conversion section with an npn structure as an example.
For the same reason as above, NPN is also used in solid-state imaging devices that have a photoelectric conversion section with a PNP structure as shown in the figure.
It had the same drawbacks as solid-state imaging devices that have a photoelectric conversion section. In FIG. 6, 24 is an insulating oxide film, 25 and 26 are gate electrodes, 27 is an n-type well, 28, 29, and 30 are p-type diffusion layers, 31 is a p-type substrate, and 32 and 34 are constant voltage sources. shows.

The purpose of the present invention is to use the above-mentioned integral method.
It is an object of the present invention to provide a solid-state imaging device with a higher signal-to-noise ratio by removing a portion of residual FPN after FPN suppression, and to improve the yield of the solid-state imaging device.

Before describing embodiments of the present invention, the principle of the present invention will be explained. The following methods can be considered to suppress the charge pumping current.

() Reduce the gate width of the MOS switch.

() Increase the fall time of the horizontal scanning pulse.

As a result of considering these methods, we found that () has limitations due to breakdown voltage or semiconductor process, and ()
It turns out that there are constraints on the period of the horizontal scanning pulse.

Therefore, the present inventors devised a method different from the above method, that is, a method of floating the low level potential of the horizontal scanning pulse to a positive level (hereinafter referred to as a low level floating method). As a result of studying this low-level floating method, I was convinced that the following two effects would be achieved by using this method, and the purpose of the present invention would be achieved.

(a) The effect of pushing the electrons that formed a channel when the MOS switch was in the on state toward the substrate when the MOS switch turned off is reduced.

(b) Even when the MOS switch is off, a slight channel remains, making it easier for electrons from the gate to be absorbed by the source or drain.

The present invention has been made from the above viewpoint,
Embodiments of the present invention for implementing the low level floating method will be described below.

FIG. 7 shows an embodiment of the present invention. A constant voltage source 73 applies a bias to the horizontal pulses output from the solid-state image sensor drive system 70 . Along with this,
A bias is applied from a constant voltage source 74 to a line 75 that determines the low level potential of the horizontal scanning pulse of the horizontal shift register 1 of the solid-state imaging device.

Now, the waveform of the horizontal pulse from the drive system 70 passed through the capacitor 71 is p-p as shown by _A1 .
Assuming that the value V _A is the average value and the potential difference between the low level and the low level V _B , when a bias is applied by the constant voltage source 73 by V _a , the low level potential becomes V _a − as shown in A ₂
It becomes V _B. Therefore, by setting the bias V _b given to the horizontal shift register 1 by the constant voltage source 74 to be V _b =V _a -V _B , _the low level potential becomes p-
A horizontal scanning pulse H having a p value of V _A is obtained.

FIGS. 8 and 9 show other embodiments of the invention using diodes. In the embodiment of FIG.
An appropriate bias is applied with a DC voltage V _D , and the seventh
A diode 78 is connected in place of the resistor 72 shown in the figure. According to this circuit, the horizontal pulse _B1 , which is the same as _A1 above, becomes _B2 . That is, high level V _c +V〓 (V〓: diode forward drop voltage),
The p-p value is V _A and the low level potential is V _c +V〓-V _A. Therefore, the constant voltage source 76 is connected to the horizontal shift register 1 so that V _d =V _c +V〓−V _A.
When bias is applied, the low level potential becomes V _d ,
A horizontal scanning pulse H having a pp value of V _A is obtained.

The embodiment of FIG. 9 shows an apparatus in which the pulse is clipped at the low level, whereas the embodiment of FIG. 8 clips at the high level of the pulse. That is, the low level of the horizontal pulse C ₂ is V _e −V〓. Therefore, the horizontal shift register 1 is adjusted so that V _f =V _e −〓.
When bias is applied by constant voltage source 83 to p-
Horizontal scanning pulse H with p value V _A and low level potential V _f
is obtained.

FIG. 10 shows another embodiment in which the low level and high level of the horizontal scanning pulse H can be adjusted individually using a buffer. Batsuhua 85 is C
- The high level of the output pulse is determined by V _g and the low level by V _h . Since the phase of the input and output pulses is inverted by the buffer 85, the phase is matched by connecting the buffer 84. The horizontal pulse D ₁ having a high level V _A and a low level O (V) becomes a horizontal pulse D ₂ having a high level V _g and a low level V _h by the buffer 85 . Therefore p-p
The value is V _g −V _h =V _A ′. Therefore, when a bias is applied to the horizontal shift register 1 by the constant voltage source 88 so that V _j =V _h , a horizontal scanning pulse H having a pp value V _A ' and a low level potential V _j is obtained.

FIG. 11 is an explanatory diagram of the effects of the present invention. In the figure, A is the output waveform with FPN before countermeasures when there is no signal, B is the output waveform with FPN suppressed by the integral method, and C is the output with FPN further suppressed when the present invention and the integral method are used together. Shows the waveform.

Condition C is that the low level of the horizontal scanning pulse is p
The potential was set to be equal to the well potential _E1 , and the high level was set to the same potential as the high level of the horizontal pulse from the drive system. When FPN was measured under these conditions, a waveform with suppressed FPN as shown in Figure C was obtained. When operated under these conditions, the p-p value of the horizontal scanning pulse becomes small and there is a concern that signals may be left unread, but image evaluation confirmed that there were no adverse effects.

Furthermore, an effect of suppressing FPN can be obtained when the low level potential of the horizontal scanning pulse H is up to twice the well potential _E1 , but when it is made more than twice as high, FPN is emphasized depending on the device as a result of experiments. I was sure that. Therefore, the low level potential of the horizontal scanning pulse H needs to be set to a value greater than O volts and less than twice the well potential.

As described above, according to the present invention, in a solid-state imaging device, the potential that makes the gate of the scanning pulse non-conductive applied to the gate electrode of the horizontal switch MOS transistor is greater than O volts and less than twice the well potential. Therefore, FPN can be suppressed and the signal-to-noise ratio can be improved.

[Brief explanation of the drawing]

Figure 1 is a schematic circuit diagram of a conventional solid-state imaging device, and Figures 2 and 6 are conventional photoelectric conversion elements and MOS
A schematic configuration diagram of the switch, Figure 3 is an explanatory diagram of the potential relationship of each part of the signal readout system, Figure 4 is a waveform diagram of spike noise that causes FPN, and Figure 5 is an explanation of the cause of charge pumping current. 7 to 10 are circuit diagrams and waveform diagrams of embodiments of the present invention, and FIG. 11 is an output waveform of the solid-state imaging device during no signal to explain the effects of the present invention. Show the diagram. 1...Horizontal scanning circuit, 2...Vertical scanning circuit, 3
...Photoelectric conversion element, 6...Vertical MOS switch,
7...Horizontal MOS switch, 14, 15, 25,
26... Gate electrode, 16... P-type well, 17
... n-type diffusion layer, 20 ... n-type substrate, 27 ... n
shaped well, 28... p-type diffusion layer, 31... p-type substrate.

Claims (1)

[Claims] 1. A photoelectric conversion section consisting of the pn junction or np junction of a transistor structure having a pn junction and a p-type substrate or an np junction and an n-type substrate, and a horizontal MOS that transmits a detection signal of the photoelectric conversion section. switch and the horizontal MOS
a horizontal scanning circuit that sequentially applies scanning pulses to the gate electrode of the switch; A solid-state imaging device that applies a constant potential to the MOS, further comprising a constant voltage source that applies a bias to the scanning pulse output from the horizontal scanning circuit,
A solid-state imaging device characterized in that a potential of a scanning pulse applied to a gate electrode of a switch that makes the gate non-conductive is greater than 0 volts and less than twice a constant potential applied to the well.