JPH0322000B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, particularly a MOS gate array LSI (hereinafter referred to as a gate array). The present invention relates to a semiconductor integrated circuit device that can have a built-in device.

[Prior art]

Generally, ROM using MOS transistors is
It has the circuit configuration shown in the figure. Here, a ROM with a 16 word x 1 bit configuration will be explained. In the figure, 1 is a row decoder constituting the first decoder, and its inputs include an upper (or lower) address 2,
The row decoder outputs 4a to 4d are orthogonal to the bit lines 5a, 5b, 5c, and 5d through which information is transmitted so as not to be connected to each other, and are arranged so that they form a mesh. Bit lines 5a-5
d, each source (or drain, hereinafter referred to as one electrode) of the MOS transistors 6a to 6d;
The drains (or sources, hereinafter referred to as the other electrodes) of MOS transistors 7a-7d for selecting a required bit line among bit lines 5a-5d are connected to each other. One electrode of each of the bit line selection MOS transistors 7a to 7d is all connected to the input of a logic inversion type buffer 9 constituting a reading means for reading out the memory contents, and the output of the buffer 9 is connected to an information output terminal. 1
Connected to 0. Each gate of the bit line selection MOS transistors 7a to 7d is connected to a decode output 14a to 14d of a column decoder 13 forming a second decoder to which lower (or upper) addresses 11, 12 are connected. ing.
Information storage transistors 15a to 15h, which are MOS transistors that store information, are arranged at the intersections of the row decode outputs 4a to 4d arranged in a mesh pattern and the bit lines 5a to 5d. are connected to the row decode outputs 4a to 4d, and each source (or drain) is connected to the bit line 5a to 5d.
, each other electrode is respectively connected to ground.

The number and intersections of these information storage MOS transistors to which they are connected vary depending on the type of information for the address required by the ROM. However, a MOS transistor that stores information always has its gate connected to the row decode output, one electrode connected to the bit line, and the other electrode connected to ground.

Next, the operation will be explained. In Figure 1,
Input the address to read the information 2, 3,
Add to 11 and 12. The address is decoded by the row decoder 1 and column decoder 13, and the selected output outputs the power supply voltage value. Note that other decoder outputs are approximately at ground potential.

Here, address input 2,
3 to the address input 1 by the column decoder 13.
As a result of decoding 1 and 12, row decode output 4
Assume that the power supply voltage value is output to b and the column decode output 14b. Since the row decode output 4b outputs the power supply voltage value, the MOS transistor 15d
becomes conductive, and the MOS transistor 6b becomes conductive in advance.
The bit line 5 was charged to the power supply voltage value by
Lower the potential of b to near ground potential. Bit line 5
The potential of b is propagated to the common bit line 5e through the MOS transistor 7b which is in a conductive state as the column decode output 14b outputs the power supply voltage value. The logic of the voltage propagated to the common bit line 5e is inverted by the logic inversion type buffer 9, that is, the power supply voltage value is output, and a logic "1" is output to the information output terminal 10.
Outputs (power supply voltage value). The above is a case where the information of the selected address of the ROM is "1", but if the information of the selected address is "0", the following operation is performed.

Now, assume that the address from which information is to be read is added to address inputs 2, 3, 11, and 12, and as a result of being decoded by row decoder 1 and column decoder 13, power supply voltage values are output to row decode output 4b and column decode output 14c. . When the row decode output 4b outputs the power supply voltage value, the MOS transistor 15d becomes conductive, but the MOS transistor 1
The source (or drain) of 5d is bit line 5c
MOS transistor 6c because it is not connected to
The potential of the bit line 5c, which has been charged in advance, does not change. The resulting column decode output 14
The potential of the bit line 5c is propagated to the common bit line 5e by the MOS transistor 7c, which is turned on by the power supply voltage value outputted to A logic "0" (approximately the ground voltage value) is output to the information output terminal 10.

As described above, the "1" output selected from the decoded outputs 4a to 4d by the row decoder 1 and the MOS transistors 7a to 7a selected by the column decoder 13
The type of information is determined by whether or not a MOS transistor is placed at a position where the bit lines 5a to 5d, which are electrically connected to the common bit line 5e by 7d, intersect.

Conventional semiconductor integrated circuit devices are configured as described above, so when trying to incorporate ROM into a gate array, it is difficult to implement ROM on a horizontally structured transistor row within the gate array. As shown, in addition to the logic circuit area 18, a ROM dedicated area 19 must be provided on the gate array chip 16. I'll try to incorporate it again
The size of the ROM is also limited to the size of the ROM dedicated area, so there is no degree of freedom, and the size of the ROM is
If it is smaller than the ROM-only area, there are drawbacks such as poor usage efficiency of the ROM-only area. Note that 17 in FIG. 2 is an I/O buffer.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the ROM configured with other logic circuits is arranged on the same straight line, and the MOS A plurality of memory blocks each having a plurality of information storage transistors and an address selection transistor each consisting of a transistor, a first decoder for selectively bringing on a plurality of information storage transistors in each memory block, and a memory block. By providing a second decoder for selectively turning on the address selection transistor in the ROM, the ROM can be mixed with logic circuits without providing a ROM-dedicated area, and any size It is possible to incorporate a ROM with high performance into the gate array, and also
DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment of the invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 3 shows a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 2 indicate the same parts. In the device of this embodiment, the logic circuit area 18 has a built-in ROM configured using transistors arranged horizontally in the same column (row) as information storage and address selection transistors, as well as logic elements. The ROM dedicated area 19 as shown in FIG. 2 is not required.

Further, FIG. 4 shows a ROM provided in the logic circuit area of FIG. 3. However, the bit configuration of this ROM is the same as in FIG. 1, 16×1 bit configuration. In the figure, ROM transistors 15i to 15l, 20a, and 6e are arranged horizontally in a row in the gate array, and the sources (or drains) of the MOS transistors 15i to 15l that store information are connected to the bit line 5f. Gate is upper (or lower)
Each memory block 2 takes addresses 2 and 3 as input.
A plurality of MOS transistors 15 within 1a to 21d
The first step for selectively bringing i to 15l into a conductive state.
is connected to decode outputs 4a to 4d of row decoder 1 constituting the decoder of
The other electrodes of 5i and 15k are address selection transistors for selecting the address to be read.
It is connected to the source (or drain) of MOSFET 20a, the drain (or source) of MOSFET 20a is grounded as a low potential point, and the gate receives lower (or upper) addresses 11 and 12 as input.
MOSFET 20 in memory blocks 21a to 21d
Decode output 14 of column decoder 13 constituting a second decoder for selectively bringing a into conduction state.
each connected to a. MOS transistor 6e for charging the bit line 5f to a predetermined potential
The source (or drain) of is connected to bit line 5f,
The gate and drain (or source) are connected to a power supply terminal 8, which is a high potential point. Bit line 5f
is connected to the input of the logic inversion type buffer 9, and the output of the logic inversion type buffer 9 is connected to the information output terminal 10. The MOS transistors 15i to 15l and 20a of the memory block 21a have the above structure, but the other memory blocks 21b to 21d
also has a similar MOS transistor connection structure. Memory blocks 21b-21d are connected to row decode outputs 4a-4d and bit line 5f, respectively, in the same way as memory block 21a. Further, the column decode output 14a is output from the MOS in the memory block 21a.
Column decode outputs 14b-14d are connected to the gates of MOS transistors in storage blocks 21b-21d, respectively, just as they are connected to the gate of transistor 20a. The above memory blocks 21a to 21d and the MOS transistor 6
The ROM main body 22 is configured by horizontally combining the ROM 2 and the logic inversion type buffer 9.

Next, the operation will be explained. It is assumed that the necessary information is set in advance for all addresses in the ROM.

Now, in FIG. 4, as a result of decoding the upper (or lower) address inputs 2 and 3 by the row decoder 1 and the lower (or upper) address inputs 11 and 12 by the column decoder 13, the row decode output 4a and Assume that a power supply voltage value is output to the column decode output 14a. Because the row decode output 4a and column decode output 14a output the power supply voltage value,
MOS transistors 15i and 20a are turned on, and the potential of bit line 5f, which has been previously charged to the power supply voltage value by MOS transistor 6e, is lowered to near the ground potential. The logic of the voltage on the bit line 5f is inverted by the logic inversion type buffer 9, that is, the power supply voltage value is outputted, and the logic "1" (power supply voltage value) is outputted to the information output terminal 10. The above is a case where the information of the selected address of the ROM is "1", but if the information of the selected address is "0", the following operation is performed.

Now, assume that the address from which information is to be read is added to address inputs 2, 3, 11, and 12, and as a result of being decoded by row decoder 1 and column decoder 13, a power supply voltage value is output to row decode output 4b and column decode output 14a. . Decode output 4b,1
4a outputs the power supply voltage value, MOS transistors 15j and 20a become conductive, but the MOS
Since the other electrode of the transistor 15j is not connected to the source (or drain) of the MOS transistor 20a, the bit line 5f is charged to the power supply voltage value by the MOS transistor 6e.
The potential does not change, and the logic of the potential is inverted by the logic inversion buffer 9, that is, a value close to the ground voltage is output, and a logic "0" (approximately the ground voltage value) is output to the information output terminal 10.

As described above, the row decode outputs 4a to 4d are connected to the gates of the memory blocks 21a to 21d.
The information to be stored depends on whether the other electrode of the MOS transistor in the block is connected to the source (or drain) of the MOS transistor in the same storage block 21a to 21d whose gate is connected to the column decode outputs 14a to 14d. Select the type.

In this way, in this embodiment, the ROM is constructed using transistors arranged horizontally in the gate array as information storage and address selection transistors in the same column (or row). There is no need to provide a dedicated ROM area, and a ROM of any size can be efficiently formed within the gate array.

Furthermore, by increasing or decreasing the number of memory blocks and the number of MOS transistors within the memory blocks along with the row and column addresses, it is possible to realize an arbitrarily large ROM within the gate array.

In the above embodiment, as shown in FIG.
The storage information is distinguished by connecting the gates of the MOS transistors 15i to 15l to the row decode outputs 4a to 4d or by connecting them to the ground, as shown in FIG. You can do this depending on whether you connect it to

In other words, what is shown in FIG.
One electrode of the transistor 5l is commonly connected to the logic inverting buffer 9, and the other electrode is commonly connected to the plurality of MOS transistors in the memory block 21a.
selected among transistors 15i to 15l
The gate electrodes of the MOS transistors 15i and 15k are connected to the row decoder outputs 4a and 4c, and the MOS transistor 20a of the memory block 21a is connected to the MOS transistors 15i to 15k in the memory block 21a.
15l and the other commonly connected electrode and ground, and the gate electrode is connected to the column decoder output 14a.

Further, in the above embodiment, the ROM is constructed using all the transistors arranged in a horizontal row, but it may be constructed using some of the transistors in the horizontal row. Also, if one horizontal row of transistors is not enough, use multiple rows of transistors.
ROM may also be configured.

Further, in the above embodiment, an example in which the present invention is applied to an N-channel MOS gate array has been described, but the present invention may also be applied to a complementary MOS gate array, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device according to the present invention, the semiconductor integrated circuit device is configured together with other logic circuits.
The ROM is arranged on the same straight line and has a plurality of information storage transistors and address selection transistors made of MOS transistors arranged on the same straight line, and a plurality of memory blocks in each memory block. Since the device is equipped with a first decoder for selectively turning on the information storage transistors and a second decoder for selectively turning on the address selection transistors in the memory block, for example, , easily within the gate array
ROM can be realized, there is no need to provide a dedicated ROM area, it can be mixed with logic elements, and it is possible to achieve high usage efficiency and high integration of LSI.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional ROM, Figure 2 is
A configuration diagram of a gate array with a dedicated ROM area,
3 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 4 is a circuit diagram showing an example of a ROM formed in the device of FIG. 3, and FIG.
FIG. 6 is a circuit diagram showing another example of the ROM formed in the device of FIG. 3, which is a partial excerpt of the circuit diagram. 1... Row decoder, 2, 3... Row address input, 4a-4d... Row decode output, 5a-5d
...Bit line, 5e...Common bit line, 6a-6
e, 7a-7d, 15a-15l, 20a...N
Channel MOS transistor, 8...Power terminal,
9...Logic inversion type buffer, 10...Information output terminal, 11, 12...Column address input, 13...Column decoder, 14a to 14d...Column decode output,
16... Gate array chip, 17... I/O buffer, 18... Logic circuit area, 19... ROM
Dedicated area, 21a to 21d...Memory block, 2
2... Mainly ROM. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A plurality of memory blocks arranged on the same straight line and having a plurality of information storage transistors and address selection transistors made of MOS transistors provided on the same straight line, each of the above-mentioned memory blocks a ROM comprising: a first decoder for selectively bringing on a plurality of information storage transistors in the memory block; and a second decoder for selectively bringing on an address selection transistor in the memory block. A semiconductor integrated circuit device characterized in that it is configured together with other logic circuits. 2 One electrode of the plurality of information storage transistors in each memory block is commonly connected to a readout means for reading out the memory contents, and the gate electrode receives a signal from the first decoder, and each memory block The address selection transistor in the memory block is connected between the other electrode of the information storage transistor selected from among the plurality of information storage transistors in the corresponding memory block and a low potential point, and has a gate electrode connected to a second decoder. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device receives a signal from the semiconductor integrated circuit device. 3 One electrode of the plurality of information storage transistors in each memory block is commonly connected and connected to a reading means for reading out the memory contents, and the other electrode is commonly connected, and the plurality of information storage transistors in each memory block The gate electrode of a selected information storage transistor among the transistors receives a signal from the first decoder, and the address selection transistor in each memory block is connected to the commonly connected other of the plurality of information storage transistors in the corresponding memory block. is connected between the electrode and the low potential point, and
2. The semiconductor integrated circuit device according to claim 1, wherein the gate electrode receives a signal from the second decoder.