JPH0533542B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, particularly a MOS gate array LSI (hereinafter referred to as gate array), and a read-only memory circuit (hereinafter referred to as The present invention relates to a semiconductor integrated circuit device that can have a built-in ROM (ROM).

[Conventional technology]

Generally, a ROM using MOS transistors has a circuit configuration shown in FIG. Here, a ROM with a 16 word x 1 bit configuration will be explained. In the figure, 1 is a row decoder, upper (or lower) addresses 2 and 3 are connected to its input, and row decoder outputs 4a to 4d are bit lines 5 through which information is propagated.
They are orthogonal to a to 5d so as not to be connected to each other, and are arranged so that they form a mesh. MOS transistors 6a to 6a are connected to bit lines 5a to 5d.
6d and each source (or drain) of bit line 5
Select the required bit line from a to 5d
The drains (or sources) of MOS transistors 7a to 7d are connected to each other. The sources (or drains) of the bit line selection MOS transistors 7a to 7d are all connected to the input of a logic inversion type buffer 9, and the output of the buffer 9 is connected to an information output terminal 10. For bit line selection
Each gate of the MOS transistors 7a to 7d is connected to the decode output 1 of the column decoder 13 to which the lower (or upper) address 11, 12 is connected.
4a to 14d. Row decoder outputs 4a to 4d and bit networks 5a to 4d arranged in a mesh pattern
MOS transistors 15a to 15h that store information are arranged at the intersections with 5d, and their respective gates output row decode outputs 4a to 4d.
Each source (or drain) is connected to a bit line 5a to 5d.
, each drain (or source) is connected to ground.

The number and intersections of these information storage MOS transistors to which they are connected vary depending on the type of information for the address required by the ROM. However, in a MOS transistor that stores information, the gate always connects to the row decoder output, and the drain (or source) connects to the row decoder output.
is connected to the bit line, and its source (or drain) is connected to ground.

Next, the operation will be explained. In Figure 6,
Input the address to read the information 2, 3,
Add to 11 and 12. The address is decoded by the row decoder 1 and column decoder 13, and the selected output outputs the power supply voltage value. Note that other decode outputs are approximately at ground potential.

Here, address input 2,
3 to the address input 1 by the column decoder 13.
As a result of decoding 1 and 12, row decode output 4
Assume that the power supply voltage value is output to b and the column decode output 14b. As the row decode output 4b outputs the power supply voltage, the MOS transistor 15d becomes conductive and lowers the potential of the bit line 5b, which had been previously charged to the power supply voltage value by the MOS transistor 6b, to near the ground potential. The potential of the bit line 5b is changed to the MOS transistor 7 which is in a conductive state as the column decode output 14b outputs the power supply voltage value.
b to the common bit line 5e. The logic of the voltage propagated to the common bit line 5e is inverted by the logic inversion type buffer 9, that is, the power supply voltage value is outputted, and the logic "1" (power supply voltage value) is outputted to the information output terminal 10. The above is a case where the information of the selected address of the ROM is "1", but if the information of the selected address is "0", the following operation is performed.

Now, assume that the address from which information is to be read is added to address inputs 2, 3, 11, and 12, and as a result of being decoded by row decoder 1 and column decoder 13, power supply voltage values are output to row decode output 4b and column decode output 14c. . When the row decode output 4b outputs the power supply voltage value, the MOS transistor 15d becomes conductive; however, the MOS transistor 15
Since the source (or drain) of d is not connected to the bit line 5c, the potential of the bit line 5c, which was previously charged by the MOS transistor 6c, does not change. As a result, conduction occurs due to the power supply voltage value output to the column decode output 14c.
The potential of the bit line 5c is propagated to the common bit line 5e by the MOS transistor 7c, and the logic of the voltage is inverted by the logic inversion type buffer 9, that is, a value close to the ground voltage is output, and a logic "0" is output to the information output terminal 10. ” (approximately the ground voltage value).

As described above, the "1" output selected from the decode outputs 4a to 4d by the row decoder 1 and the MOS transistor 7a selected by the column decoder 13
The type of information is determined by whether or not a MOS transistor is placed at a position where the common bit line 5e and the conductive bit lines 5a to 5d intersect with each other by 7d.

[Problem that the invention seeks to solve]

Conventional semiconductor integrated circuit devices are configured as described above, so when trying to incorporate ROM into a gate array, it is difficult to implement ROM on a horizontally structured transistor row within the gate array. As shown, in addition to the logic circuit area 18, a ROM dedicated area 19 must be provided on the gate array chip 16. I'll try to incorporate it again
The size of the ROM is also limited by the size of the ROM dedicated area, so there is no flexibility, and the size of the ROM is
If it is smaller than the ROM-only area, there are drawbacks such as poor usage efficiency of the ROM-only area. In FIG. 7, 17 is an I/O buffer.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and allows ROM to be mixed with logic circuits without providing a ROM-dedicated area. It is an object of the present invention to provide a semiconductor integrated circuit device that can be built into an array and has high efficiency in the use of MOS transistors within an LSI.

[Means for solving problems]

A semiconductor integrated circuit device according to the present invention configures a ROM using transistors arranged on the same straight line as information storage transistors and address selection transistors in the same column (or row), and also includes information storage transistors in each column (or row). Either "1" or "0" in the address (or row) is provided only at the address to be stored.

[Effect]

In this invention, a ROM is configured by directly connecting an information storage transistor and an address selection transistor, and the information storage transistor selects "1" or "0" among binary information to be stored in the same row (or column). Since either one is provided only for addresses that are to be stored, a ROM is configured using transistors arranged in the row (or column) direction, and an LSI
The efficiency of use of the MOS transistors within is increased.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor integrated circuit device according to an embodiment of the present invention. In the device of this embodiment, the logic circuit area 18 is located in the same column (or row) as the logic elements.
A ROM that uses transistors arranged horizontally in an address selection transistor to store information in
It has a built-in ROM as shown in Figure 7.
The dedicated area 19 is not required.

Here, the process of forming the ROM circuit by dividing the ROM to be built into the gate array into blocks and making each block adjacent to each other will be sequentially explained using FIGS. 2, 3, and 4.

In FIG. 2, blocks 32, 20 to 25 are comprised of basic cells, which are the basic constituent units of a gate array, and each basic cell is comprised of a pair of N-channel enhancement and depletion transistors. The block 32 has X address input terminals 33a to 3.
3d, and each block internal wiring 26 to 29 is connected to each X address input terminal, and the other end of the internal wiring is located at a certain position above the right side of the block 32. The block 20 has a transistor 20 inside.
t, which is realized by an enhancement transistor. The gate of this MOS transistor 20t is the Y address input terminal 34.
Furthermore, the source is connected to the ground, and the drain is connected to the intra-block wiring 31, respectively. The end of the intra-block wiring 31 in the block 20 is placed at a fixed position below the left side of the block 20. The block 21 has a MOS transistor 6e and a logic inversion type buffer 9 inside. The gate and drain of the MOS transistor 6e are connected to the power supply terminal 8, and the source is connected to the intra-block wiring 30, respectively. In addition, the input of the logic inversion type buffer 9 is connected to the internal wiring 30.
The output is connected to the information output terminal 35.
Each of the blocks 22 to 25 has MOS transistors 22a to 25a within the block, and the sources of the MOS transistors 22a to 25a are connected to each intrablock wiring 31, and the drains are connected to each intrablock wiring 30. Each MOS transistor 22a-2
Each gate of 5a is connected by a second layer wiring so as not to be the same intrablock wiring as another block among the intrablock wirings 26 to 29 realized by the first layer wiring on the depletion transistor.

Figure 3 shows the basic block shown in Figure 2 as a ROM.
Arrange the information required by the ROM, prepare the necessary number of each block to perform the ROM function,
This is a rearranged diagram. FIG. 4 is a diagram in which the blocks shown in FIG. 3 are placed adjacent to each other to form a ROM main body 36, so that the circuit functions are activated.

In FIG. 4, the intra-block wiring 26 to 30, which were separated in FIGS. It is connected to the internal wiring 31.

FIG. 5 is a configuration diagram for using the ROM main body 36 as a ROM, in which the upper addresses 2 and 3 are connected to the row decoder 1, and the row decoder outputs 4a to 4d are the row decode inputs 33a of the ROM main body 36, respectively.
~33d. Lower address 11,
12 is connected to a column decoder 13, and column decode outputs 14a to 14d are connected to column decode inputs 34a to 34d of the ROM main body 36, respectively.
The information output terminal 35 of the ROM body 36 is connected to the information output 10. Note that the transistors 20a to 20d are address selection transistors, and the transistors 15i to 15m are information storage transistors, which are provided only at addresses where "1" is to be stored.

Next, the operation will be explained. Note that this operation is performed with reference to FIG. 5, which is a diagram in which peripheral circuits are connected so that the ROM body to which each transistor block is connected is operable. It is assumed that necessary information is set in advance for all addresses in the ROM.

Now, in FIG. 5, the upper (or lower) address inputs 2 and 3 are decoded by the row decoder 1,
Assume that as a result of decoding the lower (or upper) address inputs 11 and 12 by the column decoder 13, a power supply voltage value is output to the row decode output 4a and the column decode output 14a. As the row decode output 4a and the column decode output 14a output the power supply voltage value, the MOS transistors 15j and 20a become conductive, and the potential of the bit line 5f, which had been previously charged to the power supply voltage value by the MOS transistor 6e, drops to near the ground potential. Lower it. The logic of the voltage on the bit line 5f is inverted by the logic inversion type buffer 9, that is, the power supply voltage value is outputted, and the logic "1" (power supply voltage value) is outputted to the information output terminal 10. The above is a case where the information of the selected address of the ROM is "1", but if the information of the selected address is "0", the following operation is performed.

Now, assume that the address from which information is to be read is added to address inputs 2, 3, 11, and 12, and as a result of being decoded by row decoder 1 and column decoder 13, a power supply voltage value is output to row decode output 4b and column decoder output 14a. . Decode output 4b,1
4a outputs the power supply voltage value, MOS transistors 15m and 20a become conductive, but the MOS
Source (or drain) of transistor 15m
Since it is not connected to the drain (or source) of the MOS transistor 20a, the potential of the bit line 5f, which is charged to the power supply voltage value by the MOS transistor 6e, does not change, and the potential is changed to a logic level by the logic inverting buffer 9. is inverted, that is, outputs a value close to the ground voltage, and outputs logic "0" (approximately the ground voltage value) to the information output terminal 10.

In this way, in this embodiment, the ROM is constructed using transistors arranged horizontally in the gate array as information storage and address selection transistors in the same column (or row), so the ROM-dedicated area is ROM can be formed within the gate array without the provision of a ROM.

Further, by increasing or decreasing the number of row address lines in a basic block and the number of basic blocks having address selection transistors together with the row address and column address, it is possible to realize a ROM of any size.

Furthermore, since information storage transistors are provided only at addresses where "1" information is to be stored, the efficiency of use of transistors in the gate array can be extremely increased.

Note that in the above embodiment, a block with a memory transistor is used only for the address where the information to be stored is "1", but conversely, a block with a memory transistor is used only for the address where the information to be stored is "0". Good too. In this case, a logic non-inversion type buffer is used instead of a logic inversion type buffer. In addition, although the above embodiment describes an example applied to an N-channel MOS gate array, complementary type
The present invention may be applied to a MOS gate array, and the same effects as those of the above embodiments can be obtained.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device of the present invention, when a ROM is built into a gate array, the information storage transistor and the address selection transistor in the same column (or row) are arranged on the same straight line in the gate array. using a MOS transistor
configuring ROM and information storage transistors,
Since either "1" or "0" in the same column (or row) is provided only at the address to be stored, ROM can be easily implemented in the gate array, and the storage transistor can also be used as ROM. It is not necessary for all addresses, it only needs to be formed for one of the types of information, there is no need to provide a dedicated ROM area, it can be mixed with logic elements, and LSI
It is possible to achieve high usage efficiency and high integration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit device including only a logic gate area according to one embodiment of the present invention, FIG. 2 is a circuit block diagram of blocks constituting the present invention, and FIG.
The figure is a diagram arranging the blocks in Figure 2, and Figure 4 is a diagram of the blocks in Figure 2.
Figure 5 is a diagram of the ROM body consisting of the blocks shown in Figure 5. Figure 5 is a diagram of the ROM configuration when the ROM body of Figure 4 is used. Figure 6 is a diagram of the configuration of a conventional ROM. Figure 7 is
FIG. 2 is a configuration diagram of a gate array having a ROM dedicated area. 1... Row decoder, 2, 3... Lower address input,
4a-4d... Row decode output, 5a-5e... Bit line, 6a-6d, 7a, 20t, 20a-20
d, 21a, 22a, 23a, 24a, 25a...
MOS transistor, 8...Power supply terminal, 9...Logic inversion type buffer, 10...Information output, 11, 12...Upper address input, 13...Column decoder, 14a-1
4d...Column decode output, 16...Gate array chip, 17...I/O buffer, 18...Logic circuit area, 19...ROM dedicated area, 20-25, 32...
Basic block, 26-31... Wiring within basic block, 33a-33d... Row address input terminal, 34
...Column address input terminal, 35...Information output terminal, 3
6...ROM body. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a MOS gate array LSI including a ROM configured with MOS transistors, the information storage transistor in the same column (or row) of the ROM and the address selection transistor in the column (or row) are the same It is formed using transistors arranged in a line, and the address selection transistors are provided in the same number as the column decoder outputs of the ROM, and the output of the column decoder is connected to the gate, and one main electrode is connected to a predetermined potential. , and the information storage transistor is provided only at an address where one of the binary information is to be stored,
A gate is connected to a desired row decoder output of the ROM, one main electrode is connected to the other main electrode of the address selection transistor that selects the address, and the other main electrode is connected to a common bit line. . A semiconductor integrated circuit device, wherein the other main electrode of the address selection transistor that selects an address for which no information storage transistor is provided is in an open state.