JPH0322638B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a circuit for generating LCD (liquid crystal) display control signals, and more particularly to a liquid crystal display control integrated circuit device that connects to a CRT display control IC to enable LCD display.

Prior Art CRTs have been used as display devices for a long time, and many CRT display-related ICs have been developed.
In addition, LCD display devices have recently become widely used, and their spread and development is progressing, with color displays soon to be put into practical use. And CRT display control circuit and LCD
Provide both a display control circuit and a CRT and
What is done is to enable any display on the LCD. However, in that case, the CRT display control
At least two chips, an IC and an IC for LCD display control, must be provided, resulting in disadvantages such as increased cost and power consumption. LCD display control requires unique timing, different from CRT.

Figure 1 shows an LCD display panel 1, and its common side is equipped with a shift register 2 and an analog driver 3.LP (latch pulse) is input as the clock of the shift register 2, and the common start signal is DY. . In addition, the segment side is equipped with a shift register 4, a latch 5, and an analog driver 6.
DOT (display data) is written into the shift register 4, and its contents are transferred to the latch 5 by the next latch pulse signal LP, where it is displayed in the next display period.
Common side, segment side analog driver 3,
Frame signal FRM is input to frame 6, and frame 1
The voltage applied to the LCD is changed to alternating current at regular intervals. Conventionally, such LCD display control signals have been generated by a unique IC, leading to increased costs and power consumption.

Purpose of the Invention The present invention has been made to solve the above-mentioned problems.
The object is to provide a liquid crystal display control integrated circuit device that generates display control signals.

Means for Solving Problems In the present invention, an LCD display control signal is obtained using the output of a CRT display control circuit. Unlike CRTs, LCDs require unique timing, but there are many common operations when it comes to display. The present invention focuses on this and uses the output of CRT display control as the input for LCD display control.

FIG. 2 shows an example of the system configuration of the present invention. The contents of the display data memory 21 are stored in the display control IC 2.
2, the required display timing and display data are supplied to the CRT 23 to form a display screen, and the LCD display 24 is also performed at the same time. As a display device, it is not necessary to use both at the same time; only one is normally used. Display control
As shown in Figure 3, IC22 has a CRT on one chip.
A display control circuit 25 and an LCD display control circuit 26 are built-in. The present invention is particularly designed to make this possible.
The configuration of the LCD display control circuit 26 will be described in detail below using embodiments.

Embodiment of the Invention In FIG. 4, CLK is a clock signal synchronized with display data and is an arbitrary number of clocks (integral multiple) with respect to display data. HSYNC on the left is horizontal synchronization signal input, VSYNC is vertical synchronization signal input,
BLNK is a signal input indicating the start of each raster scan display screen, and these are CRT display timings. SCK, DY, FRM, LP on the right side are
This is the LCD display timing, SCK is the data clock and indicates the display data synchronization timing, and DY
is a common start signal, indicating the beginning or end of the display screen. FRM is a frame signal and is an AC timing signal for the LCD display device. LP is a latch pulse output, which is a timing signal for displaying display data on the LCD.

In Fig. 4, the LCD display control circuit includes CLK,
LCD with BLNK, VSYNC, HSYNC as input
Outputs display control signals SCK, DY, FRM, and LP. The circuit 31 is a circuit block that controls CLK and outputs SCK according to the display period of the BLNK signal, and is an AND gate in this example. The circuit 32 is
VSYNC indicates the beginning or end of the display screen
This is a circuit block that generates DY, and is shown as an S-R flip-flop in the example. The circuit 33 is a circuit block that alternately generates "1" and "0" for each input of VSYNC, and the example shows a frequency dividing circuit using a T-type flip-flop. The circuit 34 is a circuit block for generating "1" and "0" generated in the circuit 33 in synchronization with HSYNC, and is shown as a D-type flip-flop as an example. Note that the circuits 35 to 38 are
This is a circuit block that synchronizes each output signal with the CLK signal, and is shown as a D-type FF, but these circuits may be provided separately outside. Next, circuit 3
Reference numeral 9 is a circuit block that converts display data from parallel to serial and outputs it as display data to DOT using the SCK signal, but since the speed is very fast, it may be attached externally depending on the case.

FIG. 5 shows a waveform diagram showing the timing of each of the above signals. BLNK goes from “L” to “H”
The period when HSYNC is "H" is the horizontal synchronizing signal period, and the BLNK signal is used to prevent this period from being displayed. The waveforms shown in the fourth column and below are compressed and displayed as shown by the broken line (the duty is 50% for convenience of explanatory display). There is HSYNC in each section corresponding to BLNK, and VSYNC becomes "H" and becomes one screen. SCK controls and outputs CLK during the display period of the BLNK signal, DY is generated by VSYNC, and FRM alternately generates “1” and “0” every time VSYNC is input, and is synchronized with HSYNC. LP is generated in synchronization with HSYNC.

Although the present invention has been described above with reference to embodiments, it is clear that the present invention is not limited thereto, and many other equivalent circuit configurations can be adopted for the circuits 31 to 39.

Effects of the Invention As described above, the present invention inputs a clock signal synchronized with display data, a horizontal synchronization signal for CRT display, a vertical synchronization signal, and a display start signal indicating the start of the display screen of each raster scan. a liquid crystal display control integrated circuit that outputs a liquid crystal display control signal; a circuit block that controls the clock according to the display period of the display start signal to output a data clock; and a circuit block that outputs a data clock by controlling the clock according to the display period of the display start signal; A circuit block that generates a common start signal indicating the start or end of a liquid crystal display screen by control with a signal, and a circuit block that divides the vertical synchronization signal with a frequency divider circuit to generate a signal whose polarity is alternately inverted, and the inversion. and a circuit block that outputs a frame signal in which a signal is synchronized with the horizontal synchronization signal. According to the present invention, BLNK, VSYNC, HSYNC,
The LCD display control signal is controlled by the CLK input signal.
Can generate SCK, DY, FRM, LP,
Can be connected to CRT display control IC to enable LCD display. In addition, CRT display control circuit and
This also makes it possible to integrate the LCD display control circuit into a single chip.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an LCD display panel section, FIG. 2 is a diagram showing an example of a system configuration to which the present invention is applied, and FIG. 3 is a diagram showing an example of a liquid crystal display control integrated circuit device to which the present invention is applied. 4 is a circuit diagram of an embodiment of the liquid crystal display control integrated circuit device of the present invention, and FIG.
The figure is a waveform diagram of each display control signal in the present invention. Main symbols: 1...LCD panel, 21...Display data memory, 23...CRT, 24...LCD,
25...CRT display control circuit, 26...LCD display control circuit, 31...AND circuit, 32...S-
RFF, 33...T type FF, 34...D type FF.

Claims (1)

[Claims] 1 A clock signal synchronized with display data,
A liquid crystal display control integrated circuit that inputs a horizontal synchronization signal, a vertical synchronization signal for a CRT display, and a display start signal indicating the start of a display screen for each raster scan, and outputs a liquid crystal display control signal, the display start signal a circuit block that outputs a data clock by controlling the clock according to the display period; and a circuit block that generates a common start signal indicating the start or end of the liquid crystal display screen by controlling the vertical synchronization signal and the display start signal. and a circuit block that divides the frequency of the vertical synchronization signal by a frequency dividing circuit to generate a signal whose polarity is alternately inverted, and outputs a frame signal in which the inverted signal is synchronized with the horizontal synchronization signal. A liquid crystal display control integrated circuit device characterized by: